| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 
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| 2 | #ifndef _ASM_X86_I8259_H | 
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| 3 | #define _ASM_X86_I8259_H | 
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| 4 |  | 
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| 5 | #include <linux/delay.h> | 
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| 6 | #include <asm/io.h> | 
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| 7 |  | 
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| 8 | extern unsigned int cached_irq_mask; | 
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| 9 |  | 
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| 10 | #define __byte(x, y)		(((unsigned char *)&(y))[x]) | 
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| 11 | #define cached_master_mask	(__byte(0, cached_irq_mask)) | 
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| 12 | #define cached_slave_mask	(__byte(1, cached_irq_mask)) | 
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| 13 |  | 
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| 14 | /* i8259A PIC registers */ | 
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| 15 | #define PIC_MASTER_CMD		0x20 | 
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| 16 | #define PIC_MASTER_IMR		0x21 | 
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| 17 | #define PIC_MASTER_ISR		PIC_MASTER_CMD | 
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| 18 | #define PIC_MASTER_POLL		PIC_MASTER_ISR | 
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| 19 | #define PIC_MASTER_OCW3		PIC_MASTER_ISR | 
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| 20 | #define PIC_SLAVE_CMD		0xa0 | 
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| 21 | #define PIC_SLAVE_IMR		0xa1 | 
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| 22 | #define PIC_ELCR1		0x4d0 | 
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| 23 | #define PIC_ELCR2		0x4d1 | 
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| 24 |  | 
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| 25 | /* i8259A PIC related value */ | 
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| 26 | #define PIC_CASCADE_IR		2 | 
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| 27 | #define MASTER_ICW4_DEFAULT	0x01 | 
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| 28 | #define SLAVE_ICW4_DEFAULT	0x01 | 
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| 29 | #define PIC_ICW4_AEOI		2 | 
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| 30 |  | 
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| 31 | extern raw_spinlock_t i8259A_lock; | 
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| 32 |  | 
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| 33 | /* the PIC may need a careful delay on some platforms, hence specific calls */ | 
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| 34 | static inline unsigned char inb_pic(unsigned int port) | 
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| 35 | { | 
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| 36 | unsigned char value = inb(port); | 
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| 37 |  | 
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| 38 | /* | 
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| 39 | * delay for some accesses to PIC on motherboard or in chipset | 
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| 40 | * must be at least one microsecond, so be safe here: | 
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| 41 | */ | 
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| 42 | udelay(usec: 2); | 
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| 43 |  | 
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| 44 | return value; | 
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| 45 | } | 
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| 46 |  | 
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| 47 | static inline void outb_pic(unsigned char value, unsigned int port) | 
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| 48 | { | 
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| 49 | outb(value, port); | 
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| 50 | /* | 
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| 51 | * delay for some accesses to PIC on motherboard or in chipset | 
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| 52 | * must be at least one microsecond, so be safe here: | 
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| 53 | */ | 
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| 54 | udelay(usec: 2); | 
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| 55 | } | 
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| 56 |  | 
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| 57 | extern struct irq_chip i8259A_chip; | 
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| 58 |  | 
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| 59 | struct legacy_pic { | 
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| 60 | int nr_legacy_irqs; | 
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| 61 | struct irq_chip *chip; | 
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| 62 | void (*mask)(unsigned int irq); | 
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| 63 | void (*unmask)(unsigned int irq); | 
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| 64 | void (*mask_all)(void); | 
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| 65 | void (*restore_mask)(void); | 
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| 66 | void (*init)(int auto_eoi); | 
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| 67 | int (*probe)(void); | 
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| 68 | int (*irq_pending)(unsigned int irq); | 
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| 69 | void (*make_irq)(unsigned int irq); | 
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| 70 | }; | 
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| 71 |  | 
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| 72 | void legacy_pic_pcat_compat(void); | 
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| 73 |  | 
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| 74 | extern struct legacy_pic *legacy_pic; | 
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| 75 | extern struct legacy_pic null_legacy_pic; | 
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| 76 |  | 
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| 77 | static inline bool has_legacy_pic(void) | 
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| 78 | { | 
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| 79 | return legacy_pic != &null_legacy_pic; | 
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| 80 | } | 
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| 81 |  | 
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| 82 | static inline int nr_legacy_irqs(void) | 
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| 83 | { | 
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| 84 | return legacy_pic->nr_legacy_irqs; | 
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| 85 | } | 
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| 86 |  | 
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| 87 | #endif /* _ASM_X86_I8259_H */ | 
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| 88 |  | 
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