| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 
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| 2 | #ifndef _ASM_X86_IRQ_VECTORS_H | 
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| 3 | #define _ASM_X86_IRQ_VECTORS_H | 
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| 4 |  | 
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| 5 | #include <linux/threads.h> | 
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| 6 | /* | 
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| 7 | * Linux IRQ vector layout. | 
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| 8 | * | 
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| 9 | * There are 256 IDT entries (per CPU - each entry is 8 bytes) which can | 
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| 10 | * be defined by Linux. They are used as a jump table by the CPU when a | 
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| 11 | * given vector is triggered - by a CPU-external, CPU-internal or | 
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| 12 | * software-triggered event. | 
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| 13 | * | 
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| 14 | * Linux sets the kernel code address each entry jumps to early during | 
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| 15 | * bootup, and never changes them. This is the general layout of the | 
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| 16 | * IDT entries: | 
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| 17 | * | 
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| 18 | *  Vectors   0 ...  31 : system traps and exceptions - hardcoded events | 
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| 19 | *  Vectors  32 ... 127 : device interrupts | 
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| 20 | *  Vector  128         : legacy int80 syscall interface | 
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| 21 | *  Vectors 129 ... FIRST_SYSTEM_VECTOR-1 : device interrupts | 
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| 22 | *  Vectors FIRST_SYSTEM_VECTOR ... 255   : special interrupts | 
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| 23 | * | 
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| 24 | * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table. | 
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| 25 | * | 
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| 26 | * This file enumerates the exact layout of them: | 
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| 27 | */ | 
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| 28 |  | 
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| 29 | /* This is used as an interrupt vector when programming the APIC. */ | 
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| 30 | #define NMI_VECTOR			0x02 | 
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| 31 |  | 
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| 32 | /* | 
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| 33 | * IDT vectors usable for external interrupt sources start at 0x20. | 
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| 34 | * (0x80 is the syscall vector, 0x30-0x3f are for ISA) | 
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| 35 | */ | 
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| 36 | #define FIRST_EXTERNAL_VECTOR		0x20 | 
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| 37 |  | 
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| 38 | #define IA32_SYSCALL_VECTOR		0x80 | 
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| 39 |  | 
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| 40 | /* | 
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| 41 | * Vectors 0x30-0x3f are used for ISA interrupts. | 
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| 42 | *   round up to the next 16-vector boundary | 
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| 43 | */ | 
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| 44 | #define ISA_IRQ_VECTOR(irq)		(((FIRST_EXTERNAL_VECTOR + 16) & ~15) + irq) | 
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| 45 |  | 
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| 46 | /* | 
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| 47 | * Special IRQ vectors used by the SMP architecture, 0xf0-0xff | 
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| 48 | * | 
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| 49 | *  some of the following vectors are 'rare', they are merged | 
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| 50 | *  into a single vector (CALL_FUNCTION_VECTOR) to save vector space. | 
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| 51 | *  TLB, reschedule and local APIC vectors are performance-critical. | 
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| 52 | */ | 
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| 53 |  | 
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| 54 | #define SPURIOUS_APIC_VECTOR		0xff | 
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| 55 | /* | 
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| 56 | * Sanity check | 
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| 57 | */ | 
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| 58 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) | 
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| 59 | # error SPURIOUS_APIC_VECTOR definition error | 
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| 60 | #endif | 
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| 61 |  | 
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| 62 | #define ERROR_APIC_VECTOR		0xfe | 
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| 63 | #define RESCHEDULE_VECTOR		0xfd | 
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| 64 | #define CALL_FUNCTION_VECTOR		0xfc | 
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| 65 | #define CALL_FUNCTION_SINGLE_VECTOR	0xfb | 
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| 66 | #define THERMAL_APIC_VECTOR		0xfa | 
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| 67 | #define THRESHOLD_APIC_VECTOR		0xf9 | 
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| 68 | #define REBOOT_VECTOR			0xf8 | 
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| 69 |  | 
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| 70 | /* | 
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| 71 | * Generic system vector for platform specific use | 
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| 72 | */ | 
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| 73 | #define X86_PLATFORM_IPI_VECTOR		0xf7 | 
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| 74 |  | 
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| 75 | /* | 
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| 76 | * IRQ work vector: | 
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| 77 | */ | 
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| 78 | #define IRQ_WORK_VECTOR			0xf6 | 
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| 79 |  | 
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| 80 | /* 0xf5 - unused, was UV_BAU_MESSAGE */ | 
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| 81 | #define DEFERRED_ERROR_VECTOR		0xf4 | 
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| 82 |  | 
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| 83 | /* Vector on which hypervisor callbacks will be delivered */ | 
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| 84 | #define HYPERVISOR_CALLBACK_VECTOR	0xf3 | 
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| 85 |  | 
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| 86 | /* Vector for KVM to deliver posted interrupt IPI */ | 
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| 87 | #define POSTED_INTR_VECTOR		0xf2 | 
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| 88 | #define POSTED_INTR_WAKEUP_VECTOR	0xf1 | 
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| 89 | #define POSTED_INTR_NESTED_VECTOR	0xf0 | 
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| 90 |  | 
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| 91 | #define MANAGED_IRQ_SHUTDOWN_VECTOR	0xef | 
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| 92 |  | 
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| 93 | #if IS_ENABLED(CONFIG_HYPERV) | 
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| 94 | #define HYPERV_REENLIGHTENMENT_VECTOR	0xee | 
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| 95 | #define HYPERV_STIMER0_VECTOR		0xed | 
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| 96 | #endif | 
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| 97 |  | 
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| 98 | #define LOCAL_TIMER_VECTOR		0xec | 
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| 99 |  | 
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| 100 | /* | 
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| 101 | * Posted interrupt notification vector for all device MSIs delivered to | 
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| 102 | * the host kernel. | 
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| 103 | */ | 
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| 104 | #define POSTED_MSI_NOTIFICATION_VECTOR	0xeb | 
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| 105 |  | 
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| 106 | #define NR_VECTORS			 256 | 
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| 107 |  | 
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| 108 | #ifdef CONFIG_X86_LOCAL_APIC | 
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| 109 | #define FIRST_SYSTEM_VECTOR		POSTED_MSI_NOTIFICATION_VECTOR | 
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| 110 | #else | 
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| 111 | #define FIRST_SYSTEM_VECTOR		NR_VECTORS | 
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| 112 | #endif | 
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| 113 |  | 
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| 114 | #define NR_EXTERNAL_VECTORS		(FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) | 
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| 115 | #define NR_SYSTEM_VECTORS		(NR_VECTORS - FIRST_SYSTEM_VECTOR) | 
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| 116 |  | 
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| 117 | /* | 
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| 118 | * Size the maximum number of interrupts. | 
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| 119 | * | 
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| 120 | * If the irq_desc[] array has a sparse layout, we can size things | 
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| 121 | * generously - it scales up linearly with the maximum number of CPUs, | 
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| 122 | * and the maximum number of IO-APICs, whichever is higher. | 
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| 123 | * | 
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| 124 | * In other cases we size more conservatively, to not create too large | 
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| 125 | * static arrays. | 
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| 126 | */ | 
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| 127 |  | 
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| 128 | #define NR_IRQS_LEGACY			16 | 
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| 129 |  | 
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| 130 | #define CPU_VECTOR_LIMIT		(64 * NR_CPUS) | 
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| 131 | #define IO_APIC_VECTOR_LIMIT		(32 * MAX_IO_APICS) | 
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| 132 |  | 
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| 133 | #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_PCI_MSI) | 
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| 134 | #define NR_IRQS						\ | 
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| 135 | (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ?	\ | 
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| 136 | (NR_VECTORS + CPU_VECTOR_LIMIT)  :	\ | 
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| 137 | (NR_VECTORS + IO_APIC_VECTOR_LIMIT)) | 
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| 138 | #elif defined(CONFIG_X86_IO_APIC) | 
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| 139 | #define	NR_IRQS				(NR_VECTORS + IO_APIC_VECTOR_LIMIT) | 
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| 140 | #elif defined(CONFIG_PCI_MSI) | 
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| 141 | #define NR_IRQS				(NR_VECTORS + CPU_VECTOR_LIMIT) | 
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| 142 | #else | 
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| 143 | #define NR_IRQS				NR_IRQS_LEGACY | 
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| 144 | #endif | 
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| 145 |  | 
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| 146 | #endif /* _ASM_X86_IRQ_VECTORS_H */ | 
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| 147 |  | 
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