1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef ARCH_X86_CPU_H
3#define ARCH_X86_CPU_H
4
5#include <asm/cpu.h>
6#include <asm/topology.h>
7
8#include "topology.h"
9
10/* attempt to consolidate cpu attributes */
11struct cpu_dev {
12 const char *c_vendor;
13
14 /* some have two possibilities for cpuid string */
15 const char *c_ident[2];
16
17 void (*c_early_init)(struct cpuinfo_x86 *);
18 void (*c_bsp_init)(struct cpuinfo_x86 *);
19 void (*c_init)(struct cpuinfo_x86 *);
20 void (*c_identify)(struct cpuinfo_x86 *);
21 void (*c_detect_tlb)(struct cpuinfo_x86 *);
22 int c_x86_vendor;
23#ifdef CONFIG_X86_32
24 /* Optional vendor specific routine to obtain the cache size. */
25 unsigned int (*legacy_cache_size)(struct cpuinfo_x86 *,
26 unsigned int);
27
28 /* Family/stepping-based lookup table for model names. */
29 struct legacy_cpu_model_info {
30 int family;
31 const char *model_names[16];
32 } legacy_models[5];
33#endif
34};
35
36#define cpu_dev_register(cpu_devX) \
37 static const struct cpu_dev *const __cpu_dev_##cpu_devX __used \
38 __section(".x86_cpu_dev.init") = \
39 &cpu_devX;
40
41extern const struct cpu_dev *const __x86_cpu_dev_start[],
42 *const __x86_cpu_dev_end[];
43
44#ifdef CONFIG_CPU_SUP_INTEL
45enum tsx_ctrl_states {
46 TSX_CTRL_ENABLE,
47 TSX_CTRL_DISABLE,
48 TSX_CTRL_RTM_ALWAYS_ABORT,
49 TSX_CTRL_NOT_SUPPORTED,
50};
51
52extern __ro_after_init enum tsx_ctrl_states tsx_ctrl_state;
53
54extern void __init tsx_init(void);
55void tsx_ap_init(void);
56void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c);
57#else
58static inline void tsx_init(void) { }
59static inline void tsx_ap_init(void) { }
60static inline void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) { }
61#endif /* CONFIG_CPU_SUP_INTEL */
62
63extern void init_spectral_chicken(struct cpuinfo_x86 *c);
64
65extern void get_cpu_cap(struct cpuinfo_x86 *c);
66extern void get_cpu_address_sizes(struct cpuinfo_x86 *c);
67extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c);
68extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
69extern void init_intel_cacheinfo(struct cpuinfo_x86 *c);
70extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
71extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c);
72
73extern void check_null_seg_clears_base(struct cpuinfo_x86 *c);
74
75void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id);
76void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c);
77
78#if defined(CONFIG_AMD_NB) && defined(CONFIG_SYSFS)
79struct amd_northbridge *amd_init_l3_cache(int index);
80#else
81static inline struct amd_northbridge *amd_init_l3_cache(int index)
82{
83 return NULL;
84}
85#endif
86
87unsigned int aperfmperf_get_khz(int cpu);
88void cpu_select_mitigations(void);
89
90extern void x86_spec_ctrl_setup_ap(void);
91extern void update_srbds_msr(void);
92extern void update_gds_msr(void);
93
94extern enum spectre_v2_mitigation spectre_v2_enabled;
95
96static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)
97{
98 return mode == SPECTRE_V2_EIBRS ||
99 mode == SPECTRE_V2_EIBRS_RETPOLINE ||
100 mode == SPECTRE_V2_EIBRS_LFENCE;
101}
102
103#endif /* ARCH_X86_CPU_H */
104