| 1 | // SPDX-License-Identifier: GPL-2.0 | 
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| 2 | #include <linux/io.h> | 
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| 3 | #include <linux/slab.h> | 
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| 4 | #include <linux/memblock.h> | 
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| 5 | #include <linux/cc_platform.h> | 
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| 6 | #include <linux/pgtable.h> | 
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| 7 |  | 
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| 8 | #include <asm/set_memory.h> | 
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| 9 | #include <asm/realmode.h> | 
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| 10 | #include <asm/tlbflush.h> | 
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| 11 | #include <asm/crash.h> | 
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| 12 | #include <asm/msr.h> | 
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| 13 | #include <asm/sev.h> | 
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| 14 |  | 
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| 15 | struct real_mode_header *; | 
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| 16 | u32 *trampoline_cr4_features; | 
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| 17 |  | 
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| 18 | /* Hold the pgd entry used on booting additional CPUs */ | 
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| 19 | pgd_t trampoline_pgd_entry; | 
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| 20 |  | 
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| 21 | void load_trampoline_pgtable(void) | 
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| 22 | { | 
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| 23 | #ifdef CONFIG_X86_32 | 
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| 24 | load_cr3(initial_page_table); | 
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| 25 | #else | 
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| 26 | /* | 
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| 27 | * This function is called before exiting to real-mode and that will | 
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| 28 | * fail with CR4.PCIDE still set. | 
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| 29 | */ | 
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| 30 | if (boot_cpu_has(X86_FEATURE_PCID)) | 
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| 31 | cr4_clear_bits(X86_CR4_PCIDE); | 
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| 32 |  | 
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| 33 | write_cr3(x: real_mode_header->trampoline_pgd); | 
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| 34 | #endif | 
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| 35 |  | 
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| 36 | /* | 
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| 37 | * The CR3 write above will not flush global TLB entries. | 
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| 38 | * Stale, global entries from previous page tables may still be | 
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| 39 | * present.  Flush those stale entries. | 
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| 40 | * | 
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| 41 | * This ensures that memory accessed while running with | 
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| 42 | * trampoline_pgd is *actually* mapped into trampoline_pgd. | 
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| 43 | */ | 
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| 44 | __flush_tlb_all(); | 
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| 45 | } | 
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| 46 |  | 
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| 47 | void __init reserve_real_mode(void) | 
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| 48 | { | 
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| 49 | phys_addr_t mem; | 
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| 50 | size_t size = real_mode_size_needed(); | 
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| 51 |  | 
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| 52 | if (!size) | 
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| 53 | return; | 
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| 54 |  | 
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| 55 | WARN_ON(slab_is_available()); | 
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| 56 |  | 
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| 57 | /* Has to be under 1M so we can execute real-mode AP code. */ | 
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| 58 | mem = memblock_phys_alloc_range(size, PAGE_SIZE, start: 0, end: 1<<20); | 
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| 59 | if (!mem) | 
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| 60 | pr_info( "No sub-1M memory is available for the trampoline\n"); | 
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| 61 | else | 
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| 62 | set_real_mode_mem(mem); | 
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| 63 |  | 
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| 64 | /* | 
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| 65 | * Unconditionally reserve the entire first 1M, see comment in | 
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| 66 | * setup_arch(). | 
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| 67 | */ | 
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| 68 | memblock_reserve(base: 0, SZ_1M); | 
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| 69 |  | 
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| 70 | memblock_clear_kho_scratch(base: 0, SZ_1M); | 
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| 71 | } | 
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| 72 |  | 
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| 73 | static void __init sme_sev_setup_real_mode(struct trampoline_header *th) | 
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| 74 | { | 
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| 75 | #ifdef CONFIG_AMD_MEM_ENCRYPT | 
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| 76 | if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) | 
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| 77 | th->flags |= TH_FLAGS_SME_ACTIVE; | 
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| 78 |  | 
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| 79 | if (cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) { | 
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| 80 | /* | 
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| 81 | * Skip the call to verify_cpu() in secondary_startup_64 as it | 
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| 82 | * will cause #VC exceptions when the AP can't handle them yet. | 
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| 83 | */ | 
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| 84 | th->start = (u64) secondary_startup_64_no_verify; | 
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| 85 |  | 
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| 86 | if (sev_es_setup_ap_jump_table(real_mode_header)) | 
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| 87 | panic( "Failed to get/update SEV-ES AP Jump Table"); | 
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| 88 | } | 
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| 89 | #endif | 
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| 90 | } | 
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| 91 |  | 
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| 92 | static void __init setup_real_mode(void) | 
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| 93 | { | 
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| 94 | u16 real_mode_seg; | 
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| 95 | const u32 *rel; | 
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| 96 | u32 count; | 
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| 97 | unsigned char *base; | 
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| 98 | unsigned long phys_base; | 
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| 99 | struct trampoline_header *; | 
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| 100 | size_t size = PAGE_ALIGN(real_mode_blob_end - real_mode_blob); | 
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| 101 | #ifdef CONFIG_X86_64 | 
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| 102 | u64 *trampoline_pgd; | 
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| 103 | u64 efer; | 
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| 104 | int i; | 
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| 105 | #endif | 
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| 106 |  | 
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| 107 | base = (unsigned char *)real_mode_header; | 
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| 108 |  | 
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| 109 | /* | 
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| 110 | * If SME is active, the trampoline area will need to be in | 
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| 111 | * decrypted memory in order to bring up other processors | 
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| 112 | * successfully. This is not needed for SEV. | 
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| 113 | */ | 
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| 114 | if (cc_platform_has(attr: CC_ATTR_HOST_MEM_ENCRYPT)) | 
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| 115 | set_memory_decrypted(addr: (unsigned long)base, numpages: size >> PAGE_SHIFT); | 
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| 116 |  | 
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| 117 | memcpy(to: base, from: real_mode_blob, len: size); | 
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| 118 |  | 
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| 119 | phys_base = __pa(base); | 
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| 120 | real_mode_seg = phys_base >> 4; | 
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| 121 |  | 
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| 122 | rel = (u32 *) real_mode_relocs; | 
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| 123 |  | 
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| 124 | /* 16-bit segment relocations. */ | 
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| 125 | count = *rel++; | 
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| 126 | while (count--) { | 
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| 127 | u16 *seg = (u16 *) (base + *rel++); | 
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| 128 | *seg = real_mode_seg; | 
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| 129 | } | 
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| 130 |  | 
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| 131 | /* 32-bit linear relocations. */ | 
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| 132 | count = *rel++; | 
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| 133 | while (count--) { | 
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| 134 | u32 *ptr = (u32 *) (base + *rel++); | 
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| 135 | *ptr += phys_base; | 
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| 136 | } | 
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| 137 |  | 
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| 138 | /* Must be performed *after* relocation. */ | 
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| 139 | trampoline_header = (struct trampoline_header *) | 
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| 140 | __va(real_mode_header->trampoline_header); | 
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| 141 |  | 
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| 142 | #ifdef CONFIG_X86_32 | 
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| 143 | trampoline_header->start = __pa_symbol(startup_32_smp); | 
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| 144 | trampoline_header->gdt_limit = __BOOT_DS + 7; | 
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| 145 | trampoline_header->gdt_base = __pa_symbol(boot_gdt); | 
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| 146 | #else | 
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| 147 | /* | 
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| 148 | * Some AMD processors will #GP(0) if EFER.LMA is set in WRMSR | 
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| 149 | * so we need to mask it out. | 
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| 150 | */ | 
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| 151 | rdmsrq(MSR_EFER, efer); | 
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| 152 | trampoline_header->efer = efer & ~EFER_LMA; | 
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| 153 |  | 
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| 154 | trampoline_header->start = (u64) secondary_startup_64; | 
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| 155 | trampoline_cr4_features = &trampoline_header->cr4; | 
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| 156 | *trampoline_cr4_features = mmu_cr4_features; | 
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| 157 |  | 
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| 158 | trampoline_header->flags = 0; | 
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| 159 |  | 
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| 160 | trampoline_lock = &trampoline_header->lock; | 
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| 161 | *trampoline_lock = 0; | 
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| 162 |  | 
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| 163 | trampoline_pgd = (u64 *) __va(real_mode_header->trampoline_pgd); | 
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| 164 |  | 
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| 165 | /* Map the real mode stub as virtual == physical */ | 
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| 166 | trampoline_pgd[0] = trampoline_pgd_entry.pgd; | 
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| 167 |  | 
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| 168 | /* | 
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| 169 | * Include the entirety of the kernel mapping into the trampoline | 
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| 170 | * PGD.  This way, all mappings present in the normal kernel page | 
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| 171 | * tables are usable while running on trampoline_pgd. | 
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| 172 | */ | 
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| 173 | for (i = pgd_index(__PAGE_OFFSET); i < PTRS_PER_PGD; i++) | 
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| 174 | trampoline_pgd[i] = init_top_pgt[i].pgd; | 
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| 175 | #endif | 
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| 176 |  | 
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| 177 | sme_sev_setup_real_mode(th: trampoline_header); | 
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| 178 | } | 
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| 179 |  | 
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| 180 | /* | 
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| 181 | * reserve_real_mode() gets called very early, to guarantee the | 
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| 182 | * availability of low memory. This is before the proper kernel page | 
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| 183 | * tables are set up, so we cannot set page permissions in that | 
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| 184 | * function. Also trampoline code will be executed by APs so we | 
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| 185 | * need to mark it executable at do_pre_smp_initcalls() at least, | 
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| 186 | * thus run it as a early_initcall(). | 
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| 187 | */ | 
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| 188 | static void __init set_real_mode_permissions(void) | 
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| 189 | { | 
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| 190 | unsigned char *base = (unsigned char *) real_mode_header; | 
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| 191 | size_t size = PAGE_ALIGN(real_mode_blob_end - real_mode_blob); | 
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| 192 |  | 
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| 193 | size_t ro_size = | 
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| 194 | PAGE_ALIGN(real_mode_header->ro_end) - | 
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| 195 | __pa(base); | 
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| 196 |  | 
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| 197 | size_t text_size = | 
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| 198 | PAGE_ALIGN(real_mode_header->ro_end) - | 
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| 199 | real_mode_header->text_start; | 
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| 200 |  | 
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| 201 | unsigned long text_start = | 
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| 202 | (unsigned long) __va(real_mode_header->text_start); | 
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| 203 |  | 
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| 204 | set_memory_nx(addr: (unsigned long) base, numpages: size >> PAGE_SHIFT); | 
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| 205 | set_memory_ro(addr: (unsigned long) base, numpages: ro_size >> PAGE_SHIFT); | 
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| 206 | set_memory_x(addr: (unsigned long) text_start, numpages: text_size >> PAGE_SHIFT); | 
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| 207 | } | 
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| 208 |  | 
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| 209 | void __init init_real_mode(void) | 
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| 210 | { | 
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| 211 | if (!real_mode_header) | 
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| 212 | panic(fmt: "Real mode trampoline was not allocated"); | 
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| 213 |  | 
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| 214 | setup_real_mode(); | 
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| 215 | set_real_mode_permissions(); | 
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| 216 | } | 
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| 217 |  | 
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| 218 | static int __init do_init_real_mode(void) | 
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| 219 | { | 
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| 220 | x86_platform.realmode_init(); | 
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| 221 | return 0; | 
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| 222 | } | 
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| 223 | early_initcall(do_init_real_mode); | 
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| 224 |  | 
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