| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 
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| 2 | /* | 
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| 3 | * Common Intel AGPGART and GTT definitions. | 
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| 4 | */ | 
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| 5 | #ifndef _INTEL_AGP_H | 
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| 6 | #define _INTEL_AGP_H | 
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| 7 |  | 
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| 8 | /* Intel registers */ | 
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| 9 | #define INTEL_APSIZE	0xb4 | 
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| 10 | #define INTEL_ATTBASE	0xb8 | 
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| 11 | #define INTEL_AGPCTRL	0xb0 | 
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| 12 | #define INTEL_NBXCFG	0x50 | 
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| 13 | #define INTEL_ERRSTS	0x91 | 
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| 14 |  | 
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| 15 | /* Intel i830 registers */ | 
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| 16 | #define I830_GMCH_CTRL			0x52 | 
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| 17 | #define I830_GMCH_ENABLED		0x4 | 
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| 18 | #define I830_GMCH_MEM_MASK		0x1 | 
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| 19 | #define I830_GMCH_MEM_64M		0x1 | 
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| 20 | #define I830_GMCH_MEM_128M		0 | 
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| 21 | #define I830_GMCH_GMS_MASK		0x70 | 
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| 22 | #define I830_GMCH_GMS_DISABLED		0x00 | 
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| 23 | #define I830_GMCH_GMS_LOCAL		0x10 | 
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| 24 | #define I830_GMCH_GMS_STOLEN_512	0x20 | 
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| 25 | #define I830_GMCH_GMS_STOLEN_1024	0x30 | 
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| 26 | #define I830_GMCH_GMS_STOLEN_8192	0x40 | 
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| 27 | #define I830_RDRAM_CHANNEL_TYPE		0x03010 | 
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| 28 | #define I830_RDRAM_ND(x)		(((x) & 0x20) >> 5) | 
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| 29 | #define I830_RDRAM_DDT(x)		(((x) & 0x18) >> 3) | 
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| 30 |  | 
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| 31 | /* This one is for I830MP w. an external graphic card */ | 
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| 32 | #define INTEL_I830_ERRSTS	0x92 | 
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| 33 |  | 
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| 34 | /* Intel 855GM/852GM registers */ | 
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| 35 | #define I855_GMCH_GMS_MASK		0xF0 | 
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| 36 | #define I855_GMCH_GMS_STOLEN_0M		0x0 | 
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| 37 | #define I855_GMCH_GMS_STOLEN_1M		(0x1 << 4) | 
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| 38 | #define I855_GMCH_GMS_STOLEN_4M		(0x2 << 4) | 
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| 39 | #define I855_GMCH_GMS_STOLEN_8M		(0x3 << 4) | 
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| 40 | #define I855_GMCH_GMS_STOLEN_16M	(0x4 << 4) | 
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| 41 | #define I855_GMCH_GMS_STOLEN_32M	(0x5 << 4) | 
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| 42 | #define I85X_CAPID			0x44 | 
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| 43 | #define I85X_VARIANT_MASK		0x7 | 
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| 44 | #define I85X_VARIANT_SHIFT		5 | 
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| 45 | #define I855_GME			0x0 | 
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| 46 | #define I855_GM				0x4 | 
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| 47 | #define I852_GME			0x2 | 
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| 48 | #define I852_GM				0x5 | 
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| 49 |  | 
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| 50 | /* Intel i845 registers */ | 
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| 51 | #define INTEL_I845_AGPM		0x51 | 
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| 52 | #define INTEL_I845_ERRSTS	0xc8 | 
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| 53 |  | 
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| 54 | /* Intel i860 registers */ | 
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| 55 | #define INTEL_I860_MCHCFG	0x50 | 
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| 56 | #define INTEL_I860_ERRSTS	0xc8 | 
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| 57 |  | 
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| 58 | /* Intel i810 registers */ | 
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| 59 | #define I810_GMADR_BAR		0 | 
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| 60 | #define I810_MMADR_BAR		1 | 
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| 61 | #define I810_PTE_BASE		0x10000 | 
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| 62 | #define I810_PTE_MAIN_UNCACHED	0x00000000 | 
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| 63 | #define I810_PTE_LOCAL		0x00000002 | 
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| 64 | #define I810_PTE_VALID		0x00000001 | 
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| 65 | #define I830_PTE_SYSTEM_CACHED  0x00000006 | 
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| 66 |  | 
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| 67 | #define I810_SMRAM_MISCC	0x70 | 
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| 68 | #define I810_GFX_MEM_WIN_SIZE	0x00010000 | 
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| 69 | #define I810_GFX_MEM_WIN_32M	0x00010000 | 
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| 70 | #define I810_GMS		0x000000c0 | 
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| 71 | #define I810_GMS_DISABLE	0x00000000 | 
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| 72 | #define I810_PGETBL_CTL		0x2020 | 
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| 73 | #define I810_PGETBL_ENABLED	0x00000001 | 
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| 74 | /* Note: PGETBL_CTL2 has a different offset on G33. */ | 
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| 75 | #define I965_PGETBL_CTL2	0x20c4 | 
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| 76 | #define I965_PGETBL_SIZE_MASK	0x0000000e | 
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| 77 | #define I965_PGETBL_SIZE_512KB	(0 << 1) | 
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| 78 | #define I965_PGETBL_SIZE_256KB	(1 << 1) | 
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| 79 | #define I965_PGETBL_SIZE_128KB	(2 << 1) | 
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| 80 | #define I965_PGETBL_SIZE_1MB	(3 << 1) | 
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| 81 | #define I965_PGETBL_SIZE_2MB	(4 << 1) | 
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| 82 | #define I965_PGETBL_SIZE_1_5MB	(5 << 1) | 
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| 83 | #define G33_GMCH_SIZE_MASK	(3 << 8) | 
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| 84 | #define G33_GMCH_SIZE_1M	(1 << 8) | 
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| 85 | #define G33_GMCH_SIZE_2M	(2 << 8) | 
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| 86 | #define G4x_GMCH_SIZE_MASK	(0xf << 8) | 
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| 87 | #define G4x_GMCH_SIZE_1M	(0x1 << 8) | 
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| 88 | #define G4x_GMCH_SIZE_2M	(0x3 << 8) | 
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| 89 | #define G4x_GMCH_SIZE_VT_EN	(0x8 << 8) | 
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| 90 | #define G4x_GMCH_SIZE_VT_1M	(G4x_GMCH_SIZE_1M | G4x_GMCH_SIZE_VT_EN) | 
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| 91 | #define G4x_GMCH_SIZE_VT_1_5M	((0x2 << 8) | G4x_GMCH_SIZE_VT_EN) | 
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| 92 | #define G4x_GMCH_SIZE_VT_2M	(G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN) | 
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| 93 |  | 
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| 94 | #define GFX_FLSH_CNTL		0x2170 /* 915+ */ | 
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| 95 |  | 
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| 96 | #define I810_DRAM_CTL		0x3000 | 
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| 97 | #define I810_DRAM_ROW_0		0x00000001 | 
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| 98 | #define I810_DRAM_ROW_0_SDRAM	0x00000001 | 
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| 99 |  | 
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| 100 | /* Intel 815 register */ | 
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| 101 | #define INTEL_815_APCONT	0x51 | 
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| 102 | #define INTEL_815_ATTBASE_MASK	~0x1FFFFFFF | 
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| 103 |  | 
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| 104 | /* Intel i820 registers */ | 
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| 105 | #define INTEL_I820_RDCR		0x51 | 
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| 106 | #define INTEL_I820_ERRSTS	0xc8 | 
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| 107 |  | 
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| 108 | /* Intel i840 registers */ | 
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| 109 | #define INTEL_I840_MCHCFG	0x50 | 
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| 110 | #define INTEL_I840_ERRSTS	0xc8 | 
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| 111 |  | 
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| 112 | /* Intel i850 registers */ | 
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| 113 | #define INTEL_I850_MCHCFG	0x50 | 
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| 114 | #define INTEL_I850_ERRSTS	0xc8 | 
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| 115 |  | 
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| 116 | /* intel 915G registers */ | 
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| 117 | #define I915_GMADR_BAR	2 | 
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| 118 | #define I915_MMADR_BAR	0 | 
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| 119 | #define I915_PTE_BAR	3 | 
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| 120 | #define I915_GMCH_GMS_STOLEN_48M	(0x6 << 4) | 
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| 121 | #define I915_GMCH_GMS_STOLEN_64M	(0x7 << 4) | 
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| 122 | #define G33_GMCH_GMS_STOLEN_128M	(0x8 << 4) | 
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| 123 | #define G33_GMCH_GMS_STOLEN_256M	(0x9 << 4) | 
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| 124 | #define INTEL_GMCH_GMS_STOLEN_96M	(0xa << 4) | 
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| 125 | #define INTEL_GMCH_GMS_STOLEN_160M	(0xb << 4) | 
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| 126 | #define INTEL_GMCH_GMS_STOLEN_224M	(0xc << 4) | 
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| 127 | #define INTEL_GMCH_GMS_STOLEN_352M	(0xd << 4) | 
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| 128 |  | 
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| 129 | #define I915_IFPADDR    0x60 | 
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| 130 | #define I830_HIC        0x70 | 
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| 131 |  | 
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| 132 | /* Intel 965G registers */ | 
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| 133 | #define I965_MSAC 0x62 | 
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| 134 | #define I965_IFPADDR    0x70 | 
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| 135 |  | 
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| 136 | /* Intel 7505 registers */ | 
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| 137 | #define INTEL_I7505_APSIZE	0x74 | 
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| 138 | #define INTEL_I7505_NCAPID	0x60 | 
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| 139 | #define INTEL_I7505_NISTAT	0x6c | 
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| 140 | #define INTEL_I7505_ATTBASE	0x78 | 
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| 141 | #define INTEL_I7505_ERRSTS	0x42 | 
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| 142 | #define INTEL_I7505_AGPCTRL	0x70 | 
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| 143 | #define INTEL_I7505_MCHCFG	0x50 | 
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| 144 |  | 
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| 145 | /* pci devices ids */ | 
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| 146 | #define PCI_DEVICE_ID_INTEL_E7221_HB	0x2588 | 
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| 147 | #define PCI_DEVICE_ID_INTEL_E7221_IG	0x258a | 
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| 148 | #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970 | 
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| 149 | #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972 | 
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| 150 | #define PCI_DEVICE_ID_INTEL_82G35_HB     0x2980 | 
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| 151 | #define PCI_DEVICE_ID_INTEL_82G35_IG     0x2982 | 
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| 152 | #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990 | 
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| 153 | #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992 | 
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| 154 | #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0 | 
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| 155 | #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2 | 
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| 156 | #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00 | 
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| 157 | #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02 | 
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| 158 | #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10 | 
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| 159 | #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12 | 
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| 160 | #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC | 
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| 161 | #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE | 
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| 162 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB        0xA010 | 
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| 163 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG        0xA011 | 
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| 164 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_HB         0xA000 | 
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| 165 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_IG         0xA001 | 
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| 166 | #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0 | 
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| 167 | #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2 | 
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| 168 | #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0 | 
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| 169 | #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2 | 
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| 170 | #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0 | 
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| 171 | #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2 | 
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| 172 | #define PCI_DEVICE_ID_INTEL_B43_HB          0x2E40 | 
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| 173 | #define PCI_DEVICE_ID_INTEL_B43_IG          0x2E42 | 
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| 174 | #define PCI_DEVICE_ID_INTEL_B43_1_HB        0x2E90 | 
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| 175 | #define PCI_DEVICE_ID_INTEL_B43_1_IG        0x2E92 | 
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| 176 | #define PCI_DEVICE_ID_INTEL_GM45_HB         0x2A40 | 
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| 177 | #define PCI_DEVICE_ID_INTEL_GM45_IG         0x2A42 | 
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| 178 | #define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB        0x2E00 | 
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| 179 | #define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG        0x2E02 | 
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| 180 | #define PCI_DEVICE_ID_INTEL_Q45_HB          0x2E10 | 
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| 181 | #define PCI_DEVICE_ID_INTEL_Q45_IG          0x2E12 | 
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| 182 | #define PCI_DEVICE_ID_INTEL_G45_HB          0x2E20 | 
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| 183 | #define PCI_DEVICE_ID_INTEL_G45_IG          0x2E22 | 
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| 184 | #define PCI_DEVICE_ID_INTEL_G41_HB          0x2E30 | 
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| 185 | #define PCI_DEVICE_ID_INTEL_G41_IG          0x2E32 | 
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| 186 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB	    0x0040 | 
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| 187 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB	    0x0069 | 
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| 188 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG	    0x0042 | 
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| 189 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB	    0x0044 | 
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| 190 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB	    0x0062 | 
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| 191 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB    0x006a | 
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| 192 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG	    0x0046 | 
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| 193 |  | 
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| 194 | #endif | 
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| 195 |  | 
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