1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Driver for the High Speed UART DMA
4 *
5 * Copyright (C) 2015 Intel Corporation
6 *
7 * Partially based on the bits found in drivers/tty/serial/mfd.c.
8 */
9
10#ifndef __DMA_HSU_H__
11#define __DMA_HSU_H__
12
13#include <linux/bits.h>
14#include <linux/container_of.h>
15#include <linux/io.h>
16#include <linux/types.h>
17
18#include <linux/dma/hsu.h>
19
20#include "../virt-dma.h"
21
22#define HSU_CH_SR 0x00 /* channel status */
23#define HSU_CH_CR 0x04 /* channel control */
24#define HSU_CH_DCR 0x08 /* descriptor control */
25#define HSU_CH_BSR 0x10 /* FIFO buffer size */
26#define HSU_CH_MTSR 0x14 /* minimum transfer size */
27#define HSU_CH_DxSAR(x) (0x20 + 8 * (x)) /* desc start addr */
28#define HSU_CH_DxTSR(x) (0x24 + 8 * (x)) /* desc transfer size */
29#define HSU_CH_D0SAR 0x20 /* desc 0 start addr */
30#define HSU_CH_D0TSR 0x24 /* desc 0 transfer size */
31#define HSU_CH_D1SAR 0x28
32#define HSU_CH_D1TSR 0x2c
33#define HSU_CH_D2SAR 0x30
34#define HSU_CH_D2TSR 0x34
35#define HSU_CH_D3SAR 0x38
36#define HSU_CH_D3TSR 0x3c
37
38#define HSU_DMA_CHAN_NR_DESC 4
39#define HSU_DMA_CHAN_LENGTH 0x40
40
41/* Bits in HSU_CH_SR */
42#define HSU_CH_SR_DESCTO(x) BIT(8 + (x))
43#define HSU_CH_SR_DESCTO_ANY GENMASK(11, 8)
44#define HSU_CH_SR_CHE BIT(15)
45#define HSU_CH_SR_DESCE(x) BIT(16 + (x))
46#define HSU_CH_SR_DESCE_ANY GENMASK(19, 16)
47#define HSU_CH_SR_CDESC_ANY GENMASK(31, 30)
48
49/* Bits in HSU_CH_CR */
50#define HSU_CH_CR_CHA BIT(0)
51#define HSU_CH_CR_CHD BIT(1)
52
53/* Bits in HSU_CH_DCR */
54#define HSU_CH_DCR_DESCA(x) BIT(0 + (x))
55#define HSU_CH_DCR_CHSOD(x) BIT(8 + (x))
56#define HSU_CH_DCR_CHSOTO BIT(14)
57#define HSU_CH_DCR_CHSOE BIT(15)
58#define HSU_CH_DCR_CHDI(x) BIT(16 + (x))
59#define HSU_CH_DCR_CHEI BIT(23)
60#define HSU_CH_DCR_CHTOI(x) BIT(24 + (x))
61
62/* Bits in HSU_CH_DxTSR */
63#define HSU_CH_DxTSR_MASK GENMASK(15, 0)
64#define HSU_CH_DxTSR_TSR(x) ((x) & HSU_CH_DxTSR_MASK)
65
66struct hsu_dma_sg {
67 dma_addr_t addr;
68 unsigned int len;
69};
70
71struct hsu_dma_desc {
72 struct virt_dma_desc vdesc;
73 enum dma_transfer_direction direction;
74 struct hsu_dma_sg *sg;
75 unsigned int nents;
76 size_t length;
77 unsigned int active;
78 enum dma_status status;
79};
80
81static inline struct hsu_dma_desc *to_hsu_dma_desc(struct virt_dma_desc *vdesc)
82{
83 return container_of(vdesc, struct hsu_dma_desc, vdesc);
84}
85
86struct hsu_dma_chan {
87 struct virt_dma_chan vchan;
88
89 void __iomem *reg;
90
91 /* hardware configuration */
92 enum dma_transfer_direction direction;
93 struct dma_slave_config config;
94
95 struct hsu_dma_desc *desc;
96};
97
98static inline struct hsu_dma_chan *to_hsu_dma_chan(struct dma_chan *chan)
99{
100 return container_of(chan, struct hsu_dma_chan, vchan.chan);
101}
102
103static inline u32 hsu_chan_readl(struct hsu_dma_chan *hsuc, int offset)
104{
105 return readl(addr: hsuc->reg + offset);
106}
107
108static inline void hsu_chan_writel(struct hsu_dma_chan *hsuc, int offset,
109 u32 value)
110{
111 writel(val: value, addr: hsuc->reg + offset);
112}
113
114struct hsu_dma {
115 struct dma_device dma;
116
117 /* channels */
118 struct hsu_dma_chan *chan;
119 unsigned short nr_channels;
120};
121
122static inline struct hsu_dma *to_hsu_dma(struct dma_device *ddev)
123{
124 return container_of(ddev, struct hsu_dma, dma);
125}
126
127#endif /* __DMA_HSU_H__ */
128