1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
6#ifndef __INTEL_BACKLIGHT_REGS_H__
7#define __INTEL_BACKLIGHT_REGS_H__
8
9#include "intel_display_reg_defs.h"
10
11#define _VLV_BLC_PWM_CTL2_A (VLV_DISPLAY_BASE + 0x61250)
12#define _VLV_BLC_PWM_CTL2_B (VLV_DISPLAY_BASE + 0x61350)
13#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, _VLV_BLC_PWM_CTL2_B)
14
15#define _VLV_BLC_PWM_CTL_A (VLV_DISPLAY_BASE + 0x61254)
16#define _VLV_BLC_PWM_CTL_B (VLV_DISPLAY_BASE + 0x61354)
17#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, _VLV_BLC_PWM_CTL_B)
18
19#define _VLV_BLC_HIST_CTL_A (VLV_DISPLAY_BASE + 0x61260)
20#define _VLV_BLC_HIST_CTL_B (VLV_DISPLAY_BASE + 0x61360)
21#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, _VLV_BLC_HIST_CTL_B)
22
23/* Backlight control */
24#define BLC_PWM_CTL2 _MMIO(0x61250) /* 965+ only */
25#define BLM_PWM_ENABLE (1 << 31)
26#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
27#define BLM_PIPE_SELECT (1 << 29)
28#define BLM_PIPE_SELECT_IVB (3 << 29)
29#define BLM_PIPE_A (0 << 29)
30#define BLM_PIPE_B (1 << 29)
31#define BLM_PIPE_C (2 << 29) /* ivb + */
32#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
33#define BLM_TRANSCODER_B BLM_PIPE_B
34#define BLM_TRANSCODER_C BLM_PIPE_C
35#define BLM_TRANSCODER_EDP (3 << 29)
36#define BLM_PIPE(pipe) ((pipe) << 29)
37#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
38#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
39#define BLM_PHASE_IN_ENABLE (1 << 25)
40#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
41#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
42#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
43#define BLM_PHASE_IN_COUNT_SHIFT (8)
44#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
45#define BLM_PHASE_IN_INCR_SHIFT (0)
46#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
47#define BLC_PWM_CTL _MMIO(0x61254)
48/*
49 * This is the most significant 15 bits of the number of backlight cycles in a
50 * complete cycle of the modulated backlight control.
51 *
52 * The actual value is this field multiplied by two.
53 */
54#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
55#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
56#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
57/*
58 * This is the number of cycles out of the backlight modulation cycle for which
59 * the backlight is on.
60 *
61 * This field must be no greater than the number of cycles in the complete
62 * backlight modulation cycle.
63 */
64#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
65#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
66#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
67#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
68
69#define BLC_HIST_CTL _MMIO(0x61260)
70#define BLM_HISTOGRAM_ENABLE (1 << 31)
71
72/* New registers for PCH-split platforms. Safe where new bits show up, the
73 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
74#define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
75#define BLC_PWM_CPU_CTL _MMIO(0x48254)
76
77#define HSW_BLC_PWM2_CTL _MMIO(0x48350)
78
79/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
80 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
81#define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
82#define BLM_PCH_PWM_ENABLE (1 << 31)
83#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
84#define BLM_PCH_POLARITY (1 << 29)
85#define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
86
87/* BXT backlight register definition. */
88#define _BXT_BLC_PWM_CTL1 0xC8250
89#define BXT_BLC_PWM_ENABLE (1 << 31)
90#define BXT_BLC_PWM_POLARITY (1 << 29)
91#define _BXT_BLC_PWM_FREQ1 0xC8254
92#define _BXT_BLC_PWM_DUTY1 0xC8258
93
94#define _BXT_BLC_PWM_CTL2 0xC8350
95#define _BXT_BLC_PWM_FREQ2 0xC8354
96#define _BXT_BLC_PWM_DUTY2 0xC8358
97
98#define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
99 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
100#define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
101 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
102#define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
103 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
104
105/* Utility pin */
106#define UTIL_PIN_CTL _MMIO(0x48400)
107#define UTIL_PIN_ENABLE (1 << 31)
108#define UTIL_PIN_PIPE_MASK (3 << 29)
109#define UTIL_PIN_PIPE(x) ((x) << 29)
110#define UTIL_PIN_MODE_MASK (0xf << 24)
111#define UTIL_PIN_MODE_DATA (0 << 24)
112#define UTIL_PIN_MODE_PWM (1 << 24)
113#define UTIL_PIN_MODE_VBLANK (4 << 24)
114#define UTIL_PIN_MODE_VSYNC (5 << 24)
115#define UTIL_PIN_MODE_EYE_LEVEL (8 << 24)
116#define UTIL_PIN_OUTPUT_DATA (1 << 23)
117#define UTIL_PIN_POLARITY (1 << 22)
118#define UTIL_PIN_DIRECTION_INPUT (1 << 19)
119#define UTIL_PIN_INPUT_DATA (1 << 16)
120
121#endif /* __INTEL_BACKLIGHT_REGS_H__ */
122