1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright (C) 2025 Intel Corporation
4 */
5
6#ifndef __INTEL_CMTG_REGS_H__
7#define __INTEL_CMTG_REGS_H__
8
9#include "intel_display_reg_defs.h"
10
11#define CMTG_CLK_SEL _MMIO(0x46160)
12#define CMTG_CLK_SEL_A_MASK REG_GENMASK(31, 29)
13#define CMTG_CLK_SEL_A_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
14#define CMTG_CLK_SEL_B_MASK REG_GENMASK(15, 13)
15#define CMTG_CLK_SEL_B_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
16
17#define TRANS_CMTG_CTL_A _MMIO(0x6fa88)
18#define TRANS_CMTG_CTL_B _MMIO(0x6fb88)
19#define CMTG_ENABLE REG_BIT(31)
20
21#endif /* __INTEL_CMTG_REGS_H__ */
22