1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2024 Intel Corporation
4 */
5
6#ifndef __INTEL_CRT_REGS_H__
7#define __INTEL_CRT_REGS_H__
8
9#include "intel_display_reg_defs.h"
10
11#define ADPA _MMIO(0x61100)
12#define PCH_ADPA _MMIO(0xe1100)
13#define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
14#define ADPA_DAC_ENABLE REG_BIT(31)
15#define ADPA_PIPE_SEL_MASK REG_BIT(30)
16#define ADPA_PIPE_SEL(pipe) REG_FIELD_PREP(ADPA_PIPE_SEL_MASK, (pipe))
17#define ADPA_PIPE_SEL_MASK_CPT REG_GENMASK(30, 29)
18#define ADPA_PIPE_SEL_CPT(pipe) REG_FIELD_PREP(ADPA_PIPE_SEL_MASK_CPT, (pipe))
19#define ADPA_CRT_HOTPLUG_MONITOR_MASK REG_GENMASK(25, 24)
20#define ADPA_CRT_HOTPLUG_MONITOR_NONE REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 0)
21#define ADPA_CRT_HOTPLUG_MONITOR_COLOR REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 3)
22#define ADPA_CRT_HOTPLUG_MONITOR_MONO REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 2)
23#define ADPA_CRT_HOTPLUG_ENABLE REG_BIT(23)
24#define ADPA_CRT_HOTPLUG_PERIOD_MASK REG_BIT(22)
25#define ADPA_CRT_HOTPLUG_PERIOD_64 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_PERIOD_MASK, 0)
26#define ADPA_CRT_HOTPLUG_PERIOD_128 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_PERIOD_MASK, 1)
27#define ADPA_CRT_HOTPLUG_WARMUP_MASK REG_BIT(21)
28#define ADPA_CRT_HOTPLUG_WARMUP_5MS REG_FIELD_PREP(ADPA_CRT_HOTPLUG_WARMUP_MASK, 0)
29#define ADPA_CRT_HOTPLUG_WARMUP_10MS REG_FIELD_PREP(ADPA_CRT_HOTPLUG_WARMUP_MASK, 1)
30#define ADPA_CRT_HOTPLUG_SAMPLE_MASK REG_BIT(20)
31#define ADPA_CRT_HOTPLUG_SAMPLE_2S REG_FIELD_PREP(ADPA_CRT_HOTPLUG_SAMPLE_MASK, 0)
32#define ADPA_CRT_HOTPLUG_SAMPLE_4S REG_FIELD_PREP(ADPA_CRT_HOTPLUG_SAMPLE_MASK, 1)
33#define ADPA_CRT_HOTPLUG_VOLTAGE_MASK REG_GENMASK(19, 18)
34#define ADPA_CRT_HOTPLUG_VOLTAGE_40 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 0)
35#define ADPA_CRT_HOTPLUG_VOLTAGE_50 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 1)
36#define ADPA_CRT_HOTPLUG_VOLTAGE_60 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 2)
37#define ADPA_CRT_HOTPLUG_VOLTAGE_70 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 3)
38#define ADPA_CRT_HOTPLUG_VOLREF_MASK REG_BIT(17)
39#define ADPA_CRT_HOTPLUG_VOLREF_325MV REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLREF_MASK, 0)
40#define ADPA_CRT_HOTPLUG_VOLREF_475MV REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLREF_MASK, 1)
41#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER REG_BIT(16)
42#define ADPA_USE_VGA_HVPOLARITY REG_BIT(15)
43#define ADPA_HSYNC_CNTL_DISABLE REG_BIT(11)
44#define ADPA_VSYNC_CNTL_DISABLE REG_BIT(10)
45#define ADPA_VSYNC_ACTIVE_HIGH REG_BIT(4)
46#define ADPA_HSYNC_ACTIVE_HIGH REG_BIT(3)
47
48#define _VGA_MSR_WRITE _MMIO(0x3c2)
49
50#endif /* __INTEL_CRT_REGS_H__ */
51