1/*
2 * Copyright © 2006-2019 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef _INTEL_DISPLAY_H_
26#define _INTEL_DISPLAY_H_
27
28#include <drm/drm_util.h>
29
30#include "i915_reg_defs.h"
31#include "intel_display_limits.h"
32
33struct drm_atomic_state;
34struct drm_device;
35struct drm_display_mode;
36struct drm_encoder;
37struct drm_modeset_acquire_ctx;
38struct intel_atomic_state;
39struct intel_crtc;
40struct intel_crtc_state;
41struct intel_digital_port;
42struct intel_display;
43struct intel_encoder;
44struct intel_link_m_n;
45struct intel_plane;
46struct intel_plane_state;
47struct intel_power_domain_mask;
48
49#define pipe_name(p) ((p) + 'A')
50
51static inline const char *transcoder_name(enum transcoder transcoder)
52{
53 switch (transcoder) {
54 case TRANSCODER_A:
55 return "A";
56 case TRANSCODER_B:
57 return "B";
58 case TRANSCODER_C:
59 return "C";
60 case TRANSCODER_D:
61 return "D";
62 case TRANSCODER_EDP:
63 return "EDP";
64 case TRANSCODER_DSI_A:
65 return "DSI A";
66 case TRANSCODER_DSI_C:
67 return "DSI C";
68 default:
69 return "<invalid>";
70 }
71}
72
73static inline bool transcoder_is_dsi(enum transcoder transcoder)
74{
75 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
76}
77
78#define plane_name(p) ((p) + 'A')
79
80#define for_each_plane_id_on_crtc(__crtc, __p) \
81 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
82 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
83
84#define for_each_dbuf_slice(__dev_priv, __slice) \
85 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
86 for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
87
88#define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
89 for_each_dbuf_slice((__dev_priv), (__slice)) \
90 for_each_if((__mask) & BIT(__slice))
91
92#define port_name(p) ((p) + 'A')
93
94/*
95 * Ports identifier referenced from other drivers.
96 * Expected to remain stable over time
97 */
98static inline const char *port_identifier(enum port port)
99{
100 switch (port) {
101 case PORT_A:
102 return "Port A";
103 case PORT_B:
104 return "Port B";
105 case PORT_C:
106 return "Port C";
107 case PORT_D:
108 return "Port D";
109 case PORT_E:
110 return "Port E";
111 case PORT_F:
112 return "Port F";
113 case PORT_G:
114 return "Port G";
115 case PORT_H:
116 return "Port H";
117 case PORT_I:
118 return "Port I";
119 default:
120 return "<invalid>";
121 }
122}
123
124enum tc_port {
125 TC_PORT_NONE = -1,
126
127 TC_PORT_1 = 0,
128 TC_PORT_2,
129 TC_PORT_3,
130 TC_PORT_4,
131 TC_PORT_5,
132 TC_PORT_6,
133
134 I915_MAX_TC_PORTS
135};
136
137enum aux_ch {
138 AUX_CH_NONE = -1,
139
140 AUX_CH_A,
141 AUX_CH_B,
142 AUX_CH_C,
143 AUX_CH_D,
144 AUX_CH_E, /* ICL+ */
145 AUX_CH_F,
146 AUX_CH_G,
147 AUX_CH_H,
148 AUX_CH_I,
149
150 /* tgl+ */
151 AUX_CH_USBC1 = AUX_CH_D,
152 AUX_CH_USBC2,
153 AUX_CH_USBC3,
154 AUX_CH_USBC4,
155 AUX_CH_USBC5,
156 AUX_CH_USBC6,
157
158 /* XE_LPD repositions D/E offsets and bitfields */
159 AUX_CH_D_XELPD = AUX_CH_USBC5,
160 AUX_CH_E_XELPD,
161};
162
163enum phy {
164 PHY_NONE = -1,
165
166 PHY_A = 0,
167 PHY_B,
168 PHY_C,
169 PHY_D,
170 PHY_E,
171 PHY_F,
172 PHY_G,
173 PHY_H,
174 PHY_I,
175
176 I915_MAX_PHYS
177};
178
179#define phy_name(a) ((a) + 'A')
180
181enum phy_fia {
182 FIA1,
183 FIA2,
184 FIA3,
185};
186
187#define for_each_hpd_pin(__pin) \
188 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
189
190#define for_each_pipe(__dev_priv, __p) \
191 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
192 for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
193
194#define for_each_pipe_masked(__dev_priv, __p, __mask) \
195 for_each_pipe(__dev_priv, __p) \
196 for_each_if((__mask) & BIT(__p))
197
198#define for_each_cpu_transcoder(__dev_priv, __t) \
199 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
200 for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
201
202#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
203 for_each_cpu_transcoder(__dev_priv, __t) \
204 for_each_if ((__mask) & BIT(__t))
205
206#define for_each_sprite(__dev_priv, __p, __s) \
207 for ((__s) = 0; \
208 (__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
209 (__s)++)
210
211#define for_each_port(__port) \
212 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
213
214#define for_each_port_masked(__port, __ports_mask) \
215 for_each_port(__port) \
216 for_each_if((__ports_mask) & BIT(__port))
217
218#define for_each_phy_masked(__phy, __phys_mask) \
219 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
220 for_each_if((__phys_mask) & BIT(__phy))
221
222#define for_each_intel_plane(dev, intel_plane) \
223 list_for_each_entry(intel_plane, \
224 &(dev)->mode_config.plane_list, \
225 base.head)
226
227#define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
228 list_for_each_entry(intel_plane, \
229 &(dev)->mode_config.plane_list, \
230 base.head) \
231 for_each_if((plane_mask) & \
232 drm_plane_mask(&intel_plane->base))
233
234#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
235 list_for_each_entry(intel_plane, \
236 &(dev)->mode_config.plane_list, \
237 base.head) \
238 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
239
240#define for_each_intel_crtc(dev, intel_crtc) \
241 list_for_each_entry(intel_crtc, \
242 &(dev)->mode_config.crtc_list, \
243 base.head)
244
245#define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \
246 list_for_each_entry(intel_crtc, \
247 &(dev)->mode_config.crtc_list, \
248 base.head) \
249 for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
250
251#define for_each_intel_crtc_in_pipe_mask_reverse(dev, intel_crtc, pipe_mask) \
252 list_for_each_entry_reverse((intel_crtc), \
253 &(dev)->mode_config.crtc_list, \
254 base.head) \
255 for_each_if((pipe_mask) & BIT((intel_crtc)->pipe))
256
257#define for_each_intel_encoder(dev, intel_encoder) \
258 list_for_each_entry(intel_encoder, \
259 &(dev)->mode_config.encoder_list, \
260 base.head)
261
262#define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \
263 list_for_each_entry(intel_encoder, \
264 &(dev)->mode_config.encoder_list, \
265 base.head) \
266 for_each_if((encoder_mask) & \
267 drm_encoder_mask(&intel_encoder->base))
268
269#define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \
270 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
271 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
272 intel_encoder_can_psr(intel_encoder))
273
274#define for_each_intel_dp(dev, intel_encoder) \
275 for_each_intel_encoder(dev, intel_encoder) \
276 for_each_if(intel_encoder_is_dp(intel_encoder))
277
278#define for_each_intel_encoder_with_psr(dev, intel_encoder) \
279 for_each_intel_encoder((dev), (intel_encoder)) \
280 for_each_if(intel_encoder_can_psr(intel_encoder))
281
282#define for_each_intel_connector_iter(intel_connector, iter) \
283 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
284
285#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
286 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
287 for_each_if((intel_encoder)->base.crtc == (__crtc))
288
289#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
290 for ((__i) = 0; \
291 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
292 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
293 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
294 (__i)++) \
295 for_each_if(plane)
296
297#define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \
298 for ((__i) = 0; \
299 (__i) < (__state)->base.dev->mode_config.num_crtc && \
300 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
301 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \
302 (__i)++) \
303 for_each_if(crtc)
304
305#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
306 for ((__i) = 0; \
307 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
308 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
309 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
310 (__i)++) \
311 for_each_if(plane)
312
313#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
314 for ((__i) = 0; \
315 (__i) < (__state)->base.dev->mode_config.num_crtc && \
316 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
317 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
318 (__i)++) \
319 for_each_if(crtc)
320
321#define for_each_new_intel_crtc_in_state_reverse(__state, crtc, new_crtc_state, __i) \
322 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
323 (__i) >= 0 && \
324 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
325 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
326 (__i)--) \
327 for_each_if(crtc)
328
329#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
330 for ((__i) = 0; \
331 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
332 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
333 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
334 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
335 (__i)++) \
336 for_each_if(plane)
337
338#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
339 for ((__i) = 0; \
340 (__i) < (__state)->base.dev->mode_config.num_crtc && \
341 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
342 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
343 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
344 (__i)++) \
345 for_each_if(crtc)
346
347#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
348 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
349 (__i) >= 0 && \
350 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
351 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
352 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
353 (__i)--) \
354 for_each_if(crtc)
355
356#define intel_atomic_crtc_state_for_each_plane_state( \
357 plane, plane_state, \
358 crtc_state) \
359 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
360 ((crtc_state)->uapi.plane_mask)) \
361 for_each_if ((plane_state = \
362 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
363
364#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
365 for ((__i) = 0; \
366 (__i) < (__state)->base.num_connector; \
367 (__i)++) \
368 for_each_if ((__state)->base.connectors[__i].ptr && \
369 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
370 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
371
372#define for_each_crtc_in_masks(display, crtc, first_pipes, second_pipes, i) \
373 for ((i) = 0; \
374 (i) < (I915_MAX_PIPES * 2) && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \
375 (i)++) \
376 for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i))
377
378#define for_each_crtc_in_masks_reverse(display, crtc, first_pipes, second_pipes, i) \
379 for ((i) = (I915_MAX_PIPES * 2 - 1); \
380 (i) >= 0 && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \
381 (i)--) \
382 for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i))
383
384#define for_each_pipe_crtc_modeset_disable(display, crtc, crtc_state, i) \
385 for_each_crtc_in_masks(display, crtc, \
386 _intel_modeset_primary_pipes(crtc_state), \
387 _intel_modeset_secondary_pipes(crtc_state), \
388 i)
389
390#define for_each_pipe_crtc_modeset_enable(display, crtc, crtc_state, i) \
391 for_each_crtc_in_masks_reverse(display, crtc, \
392 _intel_modeset_primary_pipes(crtc_state), \
393 _intel_modeset_secondary_pipes(crtc_state), \
394 i)
395
396int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
397u8 intel_calc_active_pipes(struct intel_atomic_state *state,
398 u8 active_pipes);
399void intel_link_compute_m_n(u16 bpp, int nlanes,
400 int pixel_clock, int link_clock,
401 int bw_overhead,
402 struct intel_link_m_n *m_n);
403u32 intel_plane_fb_max_stride(struct drm_device *drm,
404 u32 pixel_format, u64 modifier);
405enum drm_mode_status
406intel_mode_valid_max_plane_size(struct intel_display *display,
407 const struct drm_display_mode *mode,
408 int num_joined_pipes);
409enum drm_mode_status
410intel_cpu_transcoder_mode_valid(struct intel_display *display,
411 const struct drm_display_mode *mode);
412enum phy intel_port_to_phy(struct intel_display *display, enum port port);
413bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
414bool is_trans_port_sync_master(const struct intel_crtc_state *state);
415u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state);
416bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state);
417bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state);
418bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state);
419bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state);
420bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state);
421bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state);
422bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state);
423u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state);
424u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state);
425u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state);
426struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state);
427bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
428bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
429 const struct intel_crtc_state *pipe_config,
430 bool fastset);
431
432void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
433void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
434void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
435void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
436void i830_enable_pipe(struct intel_display *display, enum pipe pipe);
437void i830_disable_pipe(struct intel_display *display, enum pipe pipe);
438int vlv_get_hpll_vco(struct drm_device *drm);
439int vlv_get_cck_clock(struct drm_device *drm,
440 const char *name, u32 reg, int ref_freq);
441int vlv_get_cck_clock_hpll(struct drm_device *drm,
442 const char *name, u32 reg);
443bool intel_has_pending_fb_unpin(struct intel_display *display);
444void intel_encoder_destroy(struct drm_encoder *encoder);
445struct drm_display_mode *
446intel_encoder_current_mode(struct intel_encoder *encoder);
447void intel_encoder_get_config(struct intel_encoder *encoder,
448 struct intel_crtc_state *crtc_state);
449bool intel_phy_is_combo(struct intel_display *display, enum phy phy);
450bool intel_phy_is_tc(struct intel_display *display, enum phy phy);
451bool intel_phy_is_snps(struct intel_display *display, enum phy phy);
452enum tc_port intel_port_to_tc(struct intel_display *display, enum port port);
453
454enum phy intel_encoder_to_phy(struct intel_encoder *encoder);
455bool intel_encoder_is_combo(struct intel_encoder *encoder);
456bool intel_encoder_is_snps(struct intel_encoder *encoder);
457bool intel_encoder_is_tc(struct intel_encoder *encoder);
458enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder);
459
460int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
461
462bool intel_fuzzy_clock_check(int clock1, int clock2);
463
464void intel_zero_m_n(struct intel_link_m_n *m_n);
465void intel_set_m_n(struct intel_display *display,
466 const struct intel_link_m_n *m_n,
467 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
468 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
469void intel_get_m_n(struct intel_display *display,
470 struct intel_link_m_n *m_n,
471 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
472 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
473bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
474 enum transcoder transcoder);
475void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
476 enum transcoder cpu_transcoder,
477 const struct intel_link_m_n *m_n);
478void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
479 enum transcoder cpu_transcoder,
480 const struct intel_link_m_n *m_n);
481void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
482 enum transcoder cpu_transcoder,
483 struct intel_link_m_n *m_n);
484void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
485 enum transcoder cpu_transcoder,
486 struct intel_link_m_n *m_n);
487int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
488int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
489enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
490enum intel_display_power_domain
491intel_aux_power_domain(struct intel_digital_port *dig_port);
492void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
493 struct intel_crtc_state *crtc_state);
494int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc);
495unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
496
497struct intel_encoder *
498intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
499 const struct intel_crtc_state *crtc_state);
500void intel_plane_disable_noatomic(struct intel_crtc *crtc,
501 struct intel_plane *plane);
502void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
503 struct intel_plane_state *plane_state,
504 bool visible);
505void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
506
507bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
508 struct intel_crtc *crtc);
509
510int intel_display_min_pipe_bpp(void);
511int intel_display_max_pipe_bpp(struct intel_display *display);
512
513/* modesetting */
514int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
515 const char *reason, u8 pipe_mask);
516int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
517 const char *reason);
518int intel_modeset_commit_pipes(struct intel_display *display,
519 u8 pipe_mask,
520 struct drm_modeset_acquire_ctx *ctx);
521void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
522 struct intel_power_domain_mask *old_domains);
523void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
524 struct intel_power_domain_mask *domains);
525
526/* interface for intel_display_driver.c */
527void intel_init_display_hooks(struct intel_display *display);
528void intel_setup_outputs(struct intel_display *display);
529int intel_initial_commit(struct intel_display *display);
530void intel_panel_sanitize_ssc(struct intel_display *display);
531void intel_update_czclk(struct intel_display *display);
532enum drm_mode_status intel_mode_valid(struct drm_device *dev,
533 const struct drm_display_mode *mode);
534int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
535 bool nonblock);
536
537/* modesetting asserts */
538void assert_transcoder(struct intel_display *display,
539 enum transcoder cpu_transcoder, bool state);
540#define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)
541#define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)
542
543bool assert_port_valid(struct intel_display *display, enum port port);
544
545/*
546 * Use INTEL_DISPLAY_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw
547 * state sanity checks to check for unexpected conditions which may not
548 * necessarily be a user visible problem. This will either drm_WARN() or
549 * drm_err() depending on the verbose_state_checks module param, to enable
550 * distros and users to tailor their preferred amount of i915 abrt spam.
551 */
552#define INTEL_DISPLAY_STATE_WARN(__display, condition, format...) ({ \
553 int __ret_warn_on = !!(condition); \
554 if (unlikely(__ret_warn_on)) \
555 if (!drm_WARN((__display)->drm, (__display)->params.verbose_state_checks, format)) \
556 drm_err((__display)->drm, format); \
557 unlikely(__ret_warn_on); \
558})
559
560bool intel_scanout_needs_vtd_wa(struct intel_display *display);
561int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
562
563#endif
564