1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
6#ifndef __INTEL_SNPS_PHY_REGS__
7#define __INTEL_SNPS_PHY_REGS__
8
9#include "intel_display_reg_defs.h"
10
11#define _SNPS_PHY_A_BASE 0x168000
12#define _SNPS_PHY_B_BASE 0x169000
13#define _SNPS_PHY(phy) _PHY(phy, \
14 _SNPS_PHY_A_BASE, \
15 _SNPS_PHY_B_BASE)
16#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
17 _SNPS_PHY_A_BASE + (reg))
18#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
19#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
20 (reg) + (ln) * 0x10))
21
22#define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000)
23#define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
24#define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
25#define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
26#define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
27
28#define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)
29#define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
30#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
31#define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
32#define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
33#define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
34#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
35#define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
36#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
37#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
38#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
39#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
40
41#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
42#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
43#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
44#define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
45
46#define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C)
47#define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
48#define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0)
49
50#define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014)
51#define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
52#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30)
53#define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10)
54
55#define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018)
56#define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11)
57
58#define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C)
59#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
60#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15)
61#define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12)
62#define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0)
63
64#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)
65#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
66
67#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200)
68#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
69
70#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)
71#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
72#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
73#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
74
75#endif /* __INTEL_SNPS_PHY_REGS__ */
76