1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2019 Intel Corporation
4 */
5
6#ifndef __INTEL_TC_H__
7#define __INTEL_TC_H__
8
9#include <linux/types.h>
10
11struct intel_crtc_state;
12struct intel_digital_port;
13struct intel_encoder;
14
15/*
16 * The following enum values must stay fixed, as they match the corresponding
17 * pin assignment fields in the PORT_TX_DFLEXPA1 and TCSS_DDI_STATUS registers.
18 */
19enum intel_tc_pin_assignment { /* Lanes (a) Signal/ Cable Notes */
20 /* DP USB Rate (b) type */
21 INTEL_TC_PIN_ASSIGNMENT_NONE = 0, /* 4 - - - (c) */
22 INTEL_TC_PIN_ASSIGNMENT_A, /* 2/4 0 GEN2 TC->TC (d,e) */
23 INTEL_TC_PIN_ASSIGNMENT_B, /* 1/2 1 GEN2 TC->TC (d,f,g) */
24 INTEL_TC_PIN_ASSIGNMENT_C, /* 4 0 DP2 TC->TC (h) */
25 INTEL_TC_PIN_ASSIGNMENT_D, /* 2 1 DP2 TC->TC (h,g) */
26 INTEL_TC_PIN_ASSIGNMENT_E, /* 4 0 DP2 TC->DP */
27 INTEL_TC_PIN_ASSIGNMENT_F, /* 2 1 GEN1/DP1 TC->DP (d,g,i) */
28 /*
29 * (a) - DP unidirectional lanes, each lane using 1 differential signal
30 * pair.
31 * - USB SuperSpeed bidirectional lane, using 2 differential (TX and
32 * RX) signal pairs.
33 * - USB 2.0 (HighSpeed) unidirectional lane, using 1 differential
34 * signal pair. Not indicated, this lane is always present on pin
35 * assignments A-D and never present on pin assignments E/F.
36 * (b) - GEN1: USB 3.1 GEN1 bit rate (5 Gbps) and signaling. This
37 * is used for transferring only a USB stream.
38 * - GEN2: USB 3.1 GEN2 bit rate (10 Gbps) and signaling. This
39 * allows transferring an HBR3 (8.1 Gbps) DP stream.
40 * - DP1: Display Port signaling defined by the DP v1.3 Standard,
41 * with a maximum bit rate of HBR3.
42 * - DP2: Display Port signaling defined by the DP v2.1 Standard,
43 * with a maximum bit rate defined by the DP Alt Mode
44 * v2.1a Standard depending on the cable type as follows:
45 * - Passive (Full-Featured) USB 3.2 GEN1
46 * TC->TC cables (CC3G1-X) : UHBR10
47 * - Passive (Full-Featured) USB 3.2/4 GEN2 and
48 * Thunderbolt Alt Mode GEN2
49 * TC->TC cables (CC3G2-X) all : UHBR10
50 * DP54 logo : UHBR13.5
51 * - Passive (Full-Featured) USB4 GEN3+ and
52 * Thunderbolt Alt Mode GEN3+
53 * TC->TC cables (CC4G3-X) all : UHBR13.5
54 * DP80 logo : UHBR20
55 * - Active Re-Timed or
56 * Active Linear Re-driven (LRD)
57 * USB3.2 GEN1/2 and USB4 GEN2+
58 * TC->TC cables all : HBR3
59 * with DP_BR CTS : UHBR10
60 * DP54 logo : UHBR13.5
61 * DP80 logo : UHBR20
62 * - Passive/Active Re-Timed or
63 * Active Linear Re-driven (LRD)
64 * TC->DP cables with DP_BR CTS/DP8K logo : HBR3
65 * with DP_BR CTS : UHBR10
66 * DP54 logo : UHBR13.5
67 * DP80 logo : UHBR20
68 * (c) Used in TBT-alt/legacy modes and on LNL+ after the sink
69 * disconnected in DP-alt mode.
70 * (d) Only defined by the DP Alt Standard v1.0a, deprecated by v1.0b,
71 * only supported on ICL.
72 * (e) GEN2 passive 1 m cable: 4 DP lanes, GEN2 active cable: 2 DP lanes.
73 * (f) GEN2 passive 1 m cable: 2 DP lanes, GEN2 active cable: 1 DP lane.
74 * (g) These pin assignments are also referred to as (USB/DP)
75 * multifunction or Multifunction Display Port (MFD) modes.
76 * (h) Also used where one end of the cable is a captive connector,
77 * attached to a DP->HDMI/DVI/VGA converter.
78 * (i) The DP end of the cable is a captive connector attached to a
79 * (DP/USB) multifunction dock as defined by the DockPort v1.0a
80 * specification.
81 */
82};
83
84bool intel_tc_port_in_tbt_alt_mode(struct intel_digital_port *dig_port);
85bool intel_tc_port_in_dp_alt_mode(struct intel_digital_port *dig_port);
86bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port);
87bool intel_tc_port_handles_hpd_glitches(struct intel_digital_port *dig_port);
88
89bool intel_tc_port_connected(struct intel_encoder *encoder);
90
91enum intel_tc_pin_assignment
92intel_tc_port_get_pin_assignment(struct intel_digital_port *dig_port);
93int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port);
94void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
95 int required_lanes);
96
97void intel_tc_port_init_mode(struct intel_digital_port *dig_port);
98void intel_tc_port_sanitize_mode(struct intel_digital_port *dig_port,
99 const struct intel_crtc_state *crtc_state);
100void intel_tc_port_lock(struct intel_digital_port *dig_port);
101void intel_tc_port_unlock(struct intel_digital_port *dig_port);
102void intel_tc_port_suspend(struct intel_digital_port *dig_port);
103void intel_tc_port_get_link(struct intel_digital_port *dig_port,
104 int required_lanes);
105void intel_tc_port_put_link(struct intel_digital_port *dig_port);
106bool intel_tc_port_ref_held(struct intel_digital_port *dig_port);
107bool intel_tc_port_link_needs_reset(struct intel_digital_port *dig_port);
108bool intel_tc_port_link_reset(struct intel_digital_port *dig_port);
109void intel_tc_port_link_cancel_reset_work(struct intel_digital_port *dig_port);
110
111int intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy);
112void intel_tc_port_cleanup(struct intel_digital_port *dig_port);
113
114bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port);
115
116#endif /* __INTEL_TC_H__ */
117