1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2024 Intel Corporation
4 */
5
6#ifndef __SKL_UNIVERSAL_PLANE_REGS_H__
7#define __SKL_UNIVERSAL_PLANE_REGS_H__
8
9#include "intel_display_reg_defs.h"
10
11#define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
12 _PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), (reg_2_a), (reg_2_b)))
13#define _SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
14 (_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)) + (dw) * 4)
15#define _MMIO_SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
16 _MMIO(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))
17#define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
18 _MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))
19
20#define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \
21 _PICK_EVEN_2RANGES((plane), PLANE_5, \
22 _PIPE((pipe), (reg_1_a), (reg_1_b)), \
23 _PIPE((pipe), (reg_2_a), (reg_2_b)), \
24 _PIPE((pipe), (reg_5_a), (reg_5_b)), \
25 _PIPE((pipe), (reg_6_a), (reg_6_b)))
26#define _MMIO_SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \
27 _MMIO(_SEL_FETCH((pipe), (plane), \
28 (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b), \
29 (reg_5_a), (reg_5_b), (reg_6_a), (reg_6_b)))
30
31#define _PLANE_CTL_1_A 0x70180
32#define _PLANE_CTL_2_A 0x70280
33#define _PLANE_CTL_1_B 0x71180
34#define _PLANE_CTL_2_B 0x71280
35#define PLANE_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
36 _PLANE_CTL_1_A, _PLANE_CTL_1_B, \
37 _PLANE_CTL_2_A, _PLANE_CTL_2_B)
38#define PLANE_CTL_ENABLE REG_BIT(31)
39#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
40#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
41#define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
42#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
43/*
44 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
45 * expanded to include bit 23 as well. However, the shift-24 based values
46 * correctly map to the same formats in ICL, as long as bit 23 is set to 0
47 */
48#define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
49#define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */
50#define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
51#define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
52#define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
53#define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
54#define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
55#define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
56#define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
57#define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
58#define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
59#define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)
60#define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)
61#define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)
62#define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3)
63#define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5)
64#define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
65#define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
66#define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
67#define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
68#define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21)
69#define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)
70#define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2)
71#define PLANE_CTL_ORDER_RGBX REG_BIT(20)
72#define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
73#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
74#define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16)
75#define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)
76#define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)
77#define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)
78#define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)
79#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
80#define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
81#define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
82#define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
83#define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10)
84#define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)
85#define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)
86#define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)
87#define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
88#define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
89#define PLANE_CTL_ASYNC_FLIP REG_BIT(9)
90#define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8)
91#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
92#define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
93#define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)
94#define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2)
95#define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3)
96#define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0)
97#define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)
98#define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
99#define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
100#define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
101
102#define _PLANE_STRIDE_1_A 0x70188
103#define _PLANE_STRIDE_2_A 0x70288
104#define _PLANE_STRIDE_1_B 0x71188
105#define _PLANE_STRIDE_2_B 0x71288
106#define PLANE_STRIDE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
107 _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B, \
108 _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
109#define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
110#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
111
112#define _PLANE_POS_1_A 0x7018c
113#define _PLANE_POS_2_A 0x7028c
114#define _PLANE_POS_1_B 0x7118c
115#define _PLANE_POS_2_B 0x7128c
116#define PLANE_POS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
117 _PLANE_POS_1_A, _PLANE_POS_1_B, \
118 _PLANE_POS_2_A, _PLANE_POS_2_B)
119#define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
120#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
121#define PLANE_POS_X_MASK REG_GENMASK(15, 0)
122#define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
123
124#define _PLANE_SIZE_1_A 0x70190
125#define _PLANE_SIZE_2_A 0x70290
126#define _PLANE_SIZE_1_B 0x71190
127#define _PLANE_SIZE_2_B 0x71290
128#define PLANE_SIZE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
129 _PLANE_SIZE_1_A, _PLANE_SIZE_1_B, \
130 _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
131#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
132#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
133#define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
134#define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
135
136#define _PLANE_KEYVAL_1_A 0x70194
137#define _PLANE_KEYVAL_2_A 0x70294
138#define _PLANE_KEYVAL_1_B 0x71194
139#define _PLANE_KEYVAL_2_B 0x71294
140#define PLANE_KEYVAL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane),\
141 _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B, \
142 _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
143
144#define _PLANE_KEYMSK_1_A 0x70198
145#define _PLANE_KEYMSK_2_A 0x70298
146#define _PLANE_KEYMSK_1_B 0x71198
147#define _PLANE_KEYMSK_2_B 0x71298
148#define PLANE_KEYMSK(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
149 _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B, \
150 _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
151#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
152
153#define _PLANE_SURF_1_A 0x7019c
154#define _PLANE_SURF_2_A 0x7029c
155#define _PLANE_SURF_1_B 0x7119c
156#define _PLANE_SURF_2_B 0x7129c
157#define PLANE_SURF(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
158 _PLANE_SURF_1_A, _PLANE_SURF_1_B, \
159 _PLANE_SURF_2_A, _PLANE_SURF_2_B)
160#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
161#define PLANE_SURF_DECRYPT REG_BIT(2)
162#define PLANE_SURF_ASYNC_UPDATE REG_BIT(0)
163
164#define _PLANE_KEYMAX_1_A 0x701a0
165#define _PLANE_KEYMAX_2_A 0x702a0
166#define _PLANE_KEYMAX_1_B 0x711a0
167#define _PLANE_KEYMAX_2_B 0x712a0
168#define PLANE_KEYMAX(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
169 _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B, \
170 _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
171#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
172#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))
173
174#define _PLANE_OFFSET_1_A 0x701a4
175#define _PLANE_OFFSET_2_A 0x702a4
176#define _PLANE_OFFSET_1_B 0x711a4
177#define _PLANE_OFFSET_2_B 0x712a4
178#define PLANE_OFFSET(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
179 _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B, \
180 _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
181#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
182#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
183#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
184#define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
185
186#define _PLANE_SURFLIVE_1_A 0x701ac
187#define _PLANE_SURFLIVE_2_A 0x702ac
188#define _PLANE_SURFLIVE_1_B 0x711ac
189#define _PLANE_SURFLIVE_2_B 0x712ac
190#define PLANE_SURFLIVE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
191 _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B, \
192 _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
193
194#define _PLANE_CC_VAL_1_A 0x701b4
195#define _PLANE_CC_VAL_2_A 0x702b4
196#define _PLANE_CC_VAL_1_B 0x711b4
197#define _PLANE_CC_VAL_2_B 0x712b4
198#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_SKL_PLANE_DW((pipe), (plane), (dw), \
199 _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B, \
200 _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
201
202#define _PLANE_AUX_DIST_1_A 0x701c0
203#define _PLANE_AUX_DIST_2_A 0x702c0
204#define _PLANE_AUX_DIST_1_B 0x711c0
205#define _PLANE_AUX_DIST_2_B 0x712c0
206#define PLANE_AUX_DIST(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
207 _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B, \
208 _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
209#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
210#define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
211#define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
212
213#define _PLANE_AUX_OFFSET_1_A 0x701c4
214#define _PLANE_AUX_OFFSET_2_A 0x702c4
215#define _PLANE_AUX_OFFSET_1_B 0x711c4
216#define _PLANE_AUX_OFFSET_2_B 0x712c4
217#define PLANE_AUX_OFFSET(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
218 _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B, \
219 _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
220
221#define _PLANE_CUS_CTL_1_A 0x701c8
222#define _PLANE_CUS_CTL_2_A 0x702c8
223#define _PLANE_CUS_CTL_1_B 0x711c8
224#define _PLANE_CUS_CTL_2_B 0x712c8
225#define PLANE_CUS_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
226 _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B, \
227 _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
228#define PLANE_CUS_ENABLE REG_BIT(31)
229#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
230#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
231#define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
232#define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
233#define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
234#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
235#define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
236#define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
237#define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
238#define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
239#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
240#define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
241#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
242#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
243#define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
244
245#define _PLANE_COLOR_CTL_1_A 0x701cc /* GLK+ */
246#define _PLANE_COLOR_CTL_2_A 0x702cc
247#define _PLANE_COLOR_CTL_1_B 0x711cc
248#define _PLANE_COLOR_CTL_2_B 0x712cc
249#define PLANE_COLOR_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
250 _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B, \
251 _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
252#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
253#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
254#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
255#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
256#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
257#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
258#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
259#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
260#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2)
261#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3)
262#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4)
263#define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13)
264#define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4)
265#define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
266#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
267#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
268
269#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701e0
270#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702e0
271#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711e0
272#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712e0
273#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
274 _PLANE_INPUT_CSC_RY_GY_1_A, _PLANE_INPUT_CSC_RY_GY_1_B, \
275 _PLANE_INPUT_CSC_RY_GY_2_A, _PLANE_INPUT_CSC_RY_GY_2_B)
276
277#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701f8
278#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702f8
279#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711f8
280#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712f8
281#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
282 _PLANE_INPUT_CSC_PREOFF_HI_1_A, _PLANE_INPUT_CSC_PREOFF_HI_1_B, \
283 _PLANE_INPUT_CSC_PREOFF_HI_2_A, _PLANE_INPUT_CSC_PREOFF_HI_2_B)
284
285#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
286#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
287#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
288#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
289#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
290 _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B, \
291 _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
292
293#define _PLANE_CSC_RY_GY_1_A 0x70210
294#define _PLANE_CSC_RY_GY_2_A 0x70310
295#define _PLANE_CSC_RY_GY_1_B 0x71210
296#define _PLANE_CSC_RY_GY_2_B 0x71310
297#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
298 _PLANE_CSC_RY_GY_1_A, _PLANE_CSC_RY_GY_1_B, \
299 _PLANE_CSC_RY_GY_2_A, _PLANE_CSC_RY_GY_2_B)
300
301#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
302#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
303#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
304#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
305#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
306 _PLANE_CSC_PREOFF_HI_1_A, _PLANE_CSC_PREOFF_HI_1_B, \
307 _PLANE_CSC_PREOFF_HI_2_A, _PLANE_CSC_PREOFF_HI_2_B)
308
309#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
310#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
311#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
312#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
313#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
314 _PLANE_CSC_POSTOFF_HI_1_A, _PLANE_CSC_POSTOFF_HI_1_B, \
315 _PLANE_CSC_POSTOFF_HI_2_A, _PLANE_CSC_POSTOFF_HI_2_B)
316#define _PLANE_WM_1_A_0 0x70240
317#define _PLANE_WM_1_B_0 0x71240
318#define _PLANE_WM_2_A_0 0x70340
319#define _PLANE_WM_2_B_0 0x71340
320#define PLANE_WM(pipe, plane, level) _MMIO_SKL_PLANE_DW((pipe), (plane), (level), \
321 _PLANE_WM_1_A_0, _PLANE_WM_1_B_0, \
322 _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
323#define PLANE_WM_EN REG_BIT(31)
324#define PLANE_WM_IGNORE_LINES REG_BIT(30)
325#define PLANE_WM_AUTO_MIN_ALLOC_EN REG_BIT(29)
326#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
327#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
328
329#define _PLANE_WM_SAGV_1_A 0x70258
330#define _PLANE_WM_SAGV_1_B 0x71258
331#define _PLANE_WM_SAGV_2_A 0x70358
332#define _PLANE_WM_SAGV_2_B 0x71358
333#define PLANE_WM_SAGV(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
334 _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B, \
335 _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
336
337#define _PLANE_WM_SAGV_TRANS_1_A 0x7025c
338#define _PLANE_WM_SAGV_TRANS_1_B 0x7125c
339#define _PLANE_WM_SAGV_TRANS_2_A 0x7035c
340#define _PLANE_WM_SAGV_TRANS_2_B 0x7135c
341#define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
342 _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B, \
343 _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
344
345#define _PLANE_WM_TRANS_1_A 0x70268
346#define _PLANE_WM_TRANS_1_B 0x71268
347#define _PLANE_WM_TRANS_2_A 0x70368
348#define _PLANE_WM_TRANS_2_B 0x71368
349#define PLANE_WM_TRANS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
350 _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B, \
351 _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
352
353#define _PLANE_CHICKEN_1_A 0x7026c /* tgl+ */
354#define _PLANE_CHICKEN_2_A 0x7036c
355#define _PLANE_CHICKEN_1_B 0x7126c
356#define _PLANE_CHICKEN_2_B 0x7136c
357#define PLANE_CHICKEN(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
358 _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B, \
359 _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
360#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
361
362#define _PLANE_NV12_BUF_CFG_1_A 0x70278
363#define _PLANE_NV12_BUF_CFG_2_A 0x70378
364#define _PLANE_NV12_BUF_CFG_1_B 0x71278
365#define _PLANE_NV12_BUF_CFG_2_B 0x71378
366#define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
367 _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B, \
368 _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
369
370#define _PLANE_BUF_CFG_1_A 0x7027c
371#define _PLANE_BUF_CFG_2_A 0x7037c
372#define _PLANE_BUF_CFG_1_B 0x7127c
373#define _PLANE_BUF_CFG_2_B 0x7137c
374#define PLANE_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
375 _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B, \
376 _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
377
378/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
379#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
380#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
381#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
382#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
383
384#define _PLANE_MIN_BUF_CFG_1_A 0x70274
385#define _PLANE_MIN_BUF_CFG_2_A 0x70374
386#define _PLANE_MIN_BUF_CFG_1_B 0x71274
387#define _PLANE_MIN_BUF_CFG_2_B 0x71374
388#define PLANE_MIN_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
389 _PLANE_MIN_BUF_CFG_1_A, _PLANE_MIN_BUF_CFG_1_B, \
390 _PLANE_MIN_BUF_CFG_2_A, _PLANE_MIN_BUF_CFG_2_B)
391#define PLANE_AUTO_MIN_DBUF_EN REG_BIT(31)
392#define PLANE_MIN_DBUF_BLOCKS_MASK REG_GENMASK(27, 16)
393#define PLANE_MIN_DBUF_BLOCKS(val) REG_FIELD_PREP(PLANE_MIN_DBUF_BLOCKS_MASK, (val))
394#define PLANE_INTERIM_DBUF_BLOCKS_MASK REG_GENMASK(11, 0)
395#define PLANE_INTERIM_DBUF_BLOCKS(val) REG_FIELD_PREP(PLANE_INTERIM_DBUF_BLOCKS_MASK, (val))
396
397/* tgl+ */
398#define _SEL_FETCH_PLANE_CTL_1_A 0x70890
399#define _SEL_FETCH_PLANE_CTL_2_A 0x708b0
400#define _SEL_FETCH_PLANE_CTL_5_A 0x70920
401#define _SEL_FETCH_PLANE_CTL_6_A 0x70940
402#define _SEL_FETCH_PLANE_CTL_1_B 0x71890
403#define _SEL_FETCH_PLANE_CTL_2_B 0x718b0
404#define _SEL_FETCH_PLANE_CTL_5_B 0x71920
405#define _SEL_FETCH_PLANE_CTL_6_B 0x71940
406#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\
407 _SEL_FETCH_PLANE_CTL_1_A, _SEL_FETCH_PLANE_CTL_1_B, \
408 _SEL_FETCH_PLANE_CTL_2_A, _SEL_FETCH_PLANE_CTL_2_B, \
409 _SEL_FETCH_PLANE_CTL_5_A, _SEL_FETCH_PLANE_CTL_5_B, \
410 _SEL_FETCH_PLANE_CTL_6_A, _SEL_FETCH_PLANE_CTL_6_B)
411#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31)
412
413/* tgl+ */
414#define _SEL_FETCH_PLANE_POS_1_A 0x70894
415#define _SEL_FETCH_PLANE_POS_2_A 0x708b4
416#define _SEL_FETCH_PLANE_POS_5_A 0x70924
417#define _SEL_FETCH_PLANE_POS_6_A 0x70944
418#define _SEL_FETCH_PLANE_POS_1_B 0x71894
419#define _SEL_FETCH_PLANE_POS_2_B 0x718b4
420#define _SEL_FETCH_PLANE_POS_5_B 0x71924
421#define _SEL_FETCH_PLANE_POS_6_B 0x71944
422#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\
423 _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \
424 _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \
425 _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \
426 _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B)
427
428/* tgl+ */
429#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898
430#define _SEL_FETCH_PLANE_SIZE_2_A 0x708b8
431#define _SEL_FETCH_PLANE_SIZE_5_A 0x70928
432#define _SEL_FETCH_PLANE_SIZE_6_A 0x70948
433#define _SEL_FETCH_PLANE_SIZE_1_B 0x71898
434#define _SEL_FETCH_PLANE_SIZE_2_B 0x718b8
435#define _SEL_FETCH_PLANE_SIZE_5_B 0x71928
436#define _SEL_FETCH_PLANE_SIZE_6_B 0x71948
437#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\
438 _SEL_FETCH_PLANE_SIZE_1_A, _SEL_FETCH_PLANE_SIZE_1_B, \
439 _SEL_FETCH_PLANE_SIZE_2_A, _SEL_FETCH_PLANE_SIZE_2_B, \
440 _SEL_FETCH_PLANE_SIZE_5_A, _SEL_FETCH_PLANE_SIZE_5_B, \
441 _SEL_FETCH_PLANE_SIZE_6_A, _SEL_FETCH_PLANE_SIZE_6_B)
442
443/* tgl+ */
444#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089c
445#define _SEL_FETCH_PLANE_OFFSET_2_A 0x708bc
446#define _SEL_FETCH_PLANE_OFFSET_5_A 0x7092c
447#define _SEL_FETCH_PLANE_OFFSET_6_A 0x7094c
448#define _SEL_FETCH_PLANE_OFFSET_1_B 0x7189c
449#define _SEL_FETCH_PLANE_OFFSET_2_B 0x718bc
450#define _SEL_FETCH_PLANE_OFFSET_5_B 0x7192c
451#define _SEL_FETCH_PLANE_OFFSET_6_B 0x7194c
452#define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\
453 _SEL_FETCH_PLANE_OFFSET_1_A, _SEL_FETCH_PLANE_OFFSET_1_B, \
454 _SEL_FETCH_PLANE_OFFSET_2_A, _SEL_FETCH_PLANE_OFFSET_2_B, \
455 _SEL_FETCH_PLANE_OFFSET_5_A, _SEL_FETCH_PLANE_OFFSET_5_B, \
456 _SEL_FETCH_PLANE_OFFSET_6_A, _SEL_FETCH_PLANE_OFFSET_6_B)
457
458#endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
459