| 1 | // SPDX-License-Identifier: MIT | 
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| 2 | /* | 
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| 3 | * Copyright © 2019 Intel Corporation | 
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| 4 | */ | 
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| 5 |  | 
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| 6 | #include "i915_drv.h" | 
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| 7 | #include "i915_vma.h" | 
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| 8 | #include "intel_context.h" | 
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| 9 | #include "intel_engine_pm.h" | 
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| 10 | #include "intel_gpu_commands.h" | 
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| 11 | #include "intel_lrc.h" | 
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| 12 | #include "intel_lrc_reg.h" | 
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| 13 | #include "intel_ring.h" | 
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| 14 | #include "intel_sseu.h" | 
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| 15 |  | 
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| 16 | static int gen8_emit_rpcs_config(struct i915_request *rq, | 
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| 17 | const struct intel_context *ce, | 
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| 18 | const struct intel_sseu sseu) | 
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| 19 | { | 
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| 20 | u64 offset; | 
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| 21 | u32 *cs; | 
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| 22 |  | 
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| 23 | cs = intel_ring_begin(rq, num_dwords: 4); | 
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| 24 | if (IS_ERR(ptr: cs)) | 
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| 25 | return PTR_ERR(ptr: cs); | 
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| 26 |  | 
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| 27 | offset = i915_ggtt_offset(vma: ce->state) + | 
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| 28 | LRC_STATE_OFFSET + CTX_R_PWR_CLK_STATE * 4; | 
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| 29 |  | 
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| 30 | *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; | 
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| 31 | *cs++ = lower_32_bits(offset); | 
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| 32 | *cs++ = upper_32_bits(offset); | 
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| 33 | *cs++ = intel_sseu_make_rpcs(gt: rq->engine->gt, req_sseu: &sseu); | 
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| 34 |  | 
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| 35 | intel_ring_advance(rq, cs); | 
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| 36 |  | 
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| 37 | return 0; | 
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| 38 | } | 
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| 39 |  | 
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| 40 | static int | 
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| 41 | gen8_modify_rpcs(struct intel_context *ce, const struct intel_sseu sseu) | 
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| 42 | { | 
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| 43 | struct i915_request *rq; | 
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| 44 | int ret; | 
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| 45 |  | 
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| 46 | lockdep_assert_held(&ce->pin_mutex); | 
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| 47 |  | 
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| 48 | /* | 
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| 49 | * If the context is not idle, we have to submit an ordered request to | 
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| 50 | * modify its context image via the kernel context (writing to our own | 
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| 51 | * image, or into the registers directory, does not stick). Pristine | 
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| 52 | * and idle contexts will be configured on pinning. | 
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| 53 | */ | 
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| 54 | if (!intel_context_pin_if_active(ce)) | 
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| 55 | return 0; | 
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| 56 |  | 
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| 57 | rq = intel_engine_create_kernel_request(engine: ce->engine); | 
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| 58 | if (IS_ERR(ptr: rq)) { | 
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| 59 | ret = PTR_ERR(ptr: rq); | 
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| 60 | goto out_unpin; | 
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| 61 | } | 
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| 62 |  | 
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| 63 | /* Serialise with the remote context */ | 
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| 64 | ret = intel_context_prepare_remote_request(ce, rq); | 
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| 65 | if (ret == 0) | 
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| 66 | ret = gen8_emit_rpcs_config(rq, ce, sseu); | 
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| 67 |  | 
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| 68 | i915_request_add(rq); | 
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| 69 | out_unpin: | 
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| 70 | intel_context_unpin(ce); | 
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| 71 | return ret; | 
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| 72 | } | 
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| 73 |  | 
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| 74 | int | 
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| 75 | intel_context_reconfigure_sseu(struct intel_context *ce, | 
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| 76 | const struct intel_sseu sseu) | 
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| 77 | { | 
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| 78 | int ret; | 
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| 79 |  | 
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| 80 | GEM_BUG_ON(GRAPHICS_VER(ce->engine->i915) < 8); | 
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| 81 |  | 
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| 82 | ret = intel_context_lock_pinned(ce); | 
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| 83 | if (ret) | 
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| 84 | return ret; | 
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| 85 |  | 
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| 86 | /* Nothing to do if unmodified. */ | 
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| 87 | if (!memcmp(&ce->sseu, &sseu, sizeof(sseu))) | 
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| 88 | goto unlock; | 
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| 89 |  | 
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| 90 | ret = gen8_modify_rpcs(ce, sseu); | 
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| 91 | if (!ret) | 
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| 92 | ce->sseu = sseu; | 
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| 93 |  | 
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| 94 | unlock: | 
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| 95 | intel_context_unlock_pinned(ce); | 
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| 96 | return ret; | 
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| 97 | } | 
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| 98 |  | 
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