1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2021 Intel Corporation
4 */
5
6#ifndef _ABI_GUC_KLVS_ABI_H
7#define _ABI_GUC_KLVS_ABI_H
8
9#include <linux/types.h>
10
11/**
12 * DOC: GuC KLV
13 *
14 * +---+-------+--------------------------------------------------------------+
15 * | | Bits | Description |
16 * +===+=======+==============================================================+
17 * | 0 | 31:16 | **KEY** - KLV key identifier |
18 * | | | - `GuC Self Config KLVs`_ |
19 * | | | |
20 * | +-------+--------------------------------------------------------------+
21 * | | 15:0 | **LEN** - length of VALUE (in 32bit dwords) |
22 * +---+-------+--------------------------------------------------------------+
23 * | 1 | 31:0 | **VALUE** - actual value of the KLV (format depends on KEY) |
24 * +---+-------+ |
25 * |...| | |
26 * +---+-------+ |
27 * | n | 31:0 | |
28 * +---+-------+--------------------------------------------------------------+
29 */
30
31#define GUC_KLV_LEN_MIN 1u
32#define GUC_KLV_0_KEY (0xffffu << 16)
33#define GUC_KLV_0_LEN (0xffffu << 0)
34#define GUC_KLV_n_VALUE (0xffffffffu << 0)
35
36/**
37 * DOC: GuC Self Config KLVs
38 *
39 * `GuC KLV`_ keys available for use with HOST2GUC_SELF_CFG_.
40 *
41 * _`GUC_KLV_SELF_CFG_H2G_CTB_ADDR` : 0x0902
42 * Refers to 64 bit Global Gfx address of H2G `CT Buffer`_.
43 * Should be above WOPCM address but below APIC base address for native mode.
44 *
45 * _`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR` : 0x0903
46 * Refers to 64 bit Global Gfx address of H2G `CTB Descriptor`_.
47 * Should be above WOPCM address but below APIC base address for native mode.
48 *
49 * _`GUC_KLV_SELF_CFG_H2G_CTB_SIZE` : 0x0904
50 * Refers to size of H2G `CT Buffer`_ in bytes.
51 * Should be a multiple of 4K.
52 *
53 * _`GUC_KLV_SELF_CFG_G2H_CTB_ADDR` : 0x0905
54 * Refers to 64 bit Global Gfx address of G2H `CT Buffer`_.
55 * Should be above WOPCM address but below APIC base address for native mode.
56 *
57 * _`GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR` : 0x0906
58 * Refers to 64 bit Global Gfx address of G2H `CTB Descriptor`_.
59 * Should be above WOPCM address but below APIC base address for native mode.
60 *
61 * _`GUC_KLV_SELF_CFG_G2H_CTB_SIZE` : 0x0907
62 * Refers to size of G2H `CT Buffer`_ in bytes.
63 * Should be a multiple of 4K.
64 */
65
66#define GUC_KLV_SELF_CFG_H2G_CTB_ADDR_KEY 0x0902
67#define GUC_KLV_SELF_CFG_H2G_CTB_ADDR_LEN 2u
68
69#define GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR_KEY 0x0903
70#define GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR_LEN 2u
71
72#define GUC_KLV_SELF_CFG_H2G_CTB_SIZE_KEY 0x0904
73#define GUC_KLV_SELF_CFG_H2G_CTB_SIZE_LEN 1u
74
75#define GUC_KLV_SELF_CFG_G2H_CTB_ADDR_KEY 0x0905
76#define GUC_KLV_SELF_CFG_G2H_CTB_ADDR_LEN 2u
77
78#define GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR_KEY 0x0906
79#define GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR_LEN 2u
80
81#define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_KEY 0x0907
82#define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_LEN 1u
83
84/*
85 * Global scheduling policy update keys.
86 */
87enum {
88 GUC_SCHEDULING_POLICIES_KLV_ID_RENDER_COMPUTE_YIELD = 0x1001,
89};
90
91/*
92 * Per context scheduling policy update keys.
93 */
94enum {
95 GUC_CONTEXT_POLICIES_KLV_ID_EXECUTION_QUANTUM = 0x2001,
96 GUC_CONTEXT_POLICIES_KLV_ID_PREEMPTION_TIMEOUT = 0x2002,
97 GUC_CONTEXT_POLICIES_KLV_ID_SCHEDULING_PRIORITY = 0x2003,
98 GUC_CONTEXT_POLICIES_KLV_ID_PREEMPT_TO_IDLE_ON_QUANTUM_EXPIRY = 0x2004,
99 GUC_CONTEXT_POLICIES_KLV_ID_SLPM_GT_FREQUENCY = 0x2005,
100
101 GUC_CONTEXT_POLICIES_KLV_NUM_IDS = 5,
102};
103
104/*
105 * Workaround keys:
106 */
107enum {
108 GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE = 0x9001,
109 GUC_WORKAROUND_KLV_BLOCK_INTERRUPTS_WHEN_MGSR_BLOCKED = 0x9002,
110 GUC_WORKAROUND_KLV_AVOID_GFX_CLEAR_WHILE_ACTIVE = 0x9006,
111};
112
113#endif /* _ABI_GUC_KLVS_ABI_H */
114