1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2014-2019 Intel Corporation
4 *
5 * Authors:
6 * Vinit Azad <vinit.azad@intel.com>
7 * Ben Widawsky <ben@bwidawsk.net>
8 * Dave Gordon <david.s.gordon@intel.com>
9 * Alex Dai <yu.dai@intel.com>
10 */
11
12#include "gt/intel_gt.h"
13#include "gt/intel_gt_mcr.h"
14#include "gt/intel_gt_regs.h"
15#include "gt/intel_rps.h"
16
17#include "i915_drv.h"
18#include "i915_wait_util.h"
19#include "intel_guc_fw.h"
20#include "intel_guc_print.h"
21
22static void guc_prepare_xfer(struct intel_gt *gt)
23{
24 struct intel_uncore *uncore = gt->uncore;
25
26 u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC |
27 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
28 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
29 GUC_ENABLE_MIA_CLOCK_GATING;
30
31 if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 55))
32 shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES |
33 GUC_ENABLE_MIA_CACHING;
34
35 /* Must program this register before loading the ucode with DMA */
36 intel_uncore_write(uncore, GUC_SHIM_CONTROL, val: shim_flags);
37
38 if (IS_GEN9_LP(uncore->i915))
39 intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
40 else
41 intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
42
43 if (GRAPHICS_VER(uncore->i915) == 9) {
44 /* DOP Clock Gating Enable for GuC clocks */
45 intel_uncore_rmw(uncore, GEN7_MISCCPCTL, clear: 0,
46 GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
47
48 /* allows for 5us (in 10ns units) before GT can go to RC6 */
49 intel_uncore_write(uncore, GUC_ARAT_C6DIS, val: 0x1FF);
50 }
51
52 /*
53 * Starting from IP 12.50 we need to enable the mirroring of GuC
54 * internal state to debug registers. This is always enabled on previous
55 * IPs.
56 */
57 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50))
58 intel_uncore_rmw(uncore, GUC_SHIM_CONTROL2, clear: 0, GUC_ENABLE_DEBUG_REG);
59}
60
61static int guc_xfer_rsa_mmio(struct intel_uc_fw *guc_fw,
62 struct intel_uncore *uncore)
63{
64 u32 rsa[UOS_RSA_SCRATCH_COUNT];
65 size_t copied;
66 int i;
67
68 copied = intel_uc_fw_copy_rsa(uc_fw: guc_fw, dst: rsa, max_len: sizeof(rsa));
69 if (copied < sizeof(rsa))
70 return -ENOMEM;
71
72 for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
73 intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), val: rsa[i]);
74
75 return 0;
76}
77
78static int guc_xfer_rsa_vma(struct intel_uc_fw *guc_fw,
79 struct intel_uncore *uncore)
80{
81 struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
82
83 intel_uncore_write(uncore, UOS_RSA_SCRATCH(0),
84 val: intel_guc_ggtt_offset(guc, vma: guc_fw->rsa_data));
85
86 return 0;
87}
88
89/* Copy RSA signature from the fw image to HW for verification */
90static int guc_xfer_rsa(struct intel_uc_fw *guc_fw,
91 struct intel_uncore *uncore)
92{
93 if (guc_fw->rsa_data)
94 return guc_xfer_rsa_vma(guc_fw, uncore);
95 else
96 return guc_xfer_rsa_mmio(guc_fw, uncore);
97}
98
99/*
100 * Read the GuC status register (GUC_STATUS) and store it in the
101 * specified location; then return a boolean indicating whether
102 * the value matches either completion or a known failure code.
103 *
104 * This is used for polling the GuC status in a wait_for()
105 * loop below.
106 */
107static inline bool guc_load_done(struct intel_uncore *uncore, u32 *status, bool *success)
108{
109 u32 val = intel_uncore_read(uncore, GUC_STATUS);
110 u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, val);
111 u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, val);
112
113 *status = val;
114 switch (uk_val) {
115 case INTEL_GUC_LOAD_STATUS_READY:
116 *success = true;
117 return true;
118
119 case INTEL_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH:
120 case INTEL_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH:
121 case INTEL_GUC_LOAD_STATUS_ERROR_DEVID_INVALID_GUCTYPE:
122 case INTEL_GUC_LOAD_STATUS_HWCONFIG_ERROR:
123 case INTEL_GUC_LOAD_STATUS_DPC_ERROR:
124 case INTEL_GUC_LOAD_STATUS_EXCEPTION:
125 case INTEL_GUC_LOAD_STATUS_INIT_DATA_INVALID:
126 case INTEL_GUC_LOAD_STATUS_MPU_DATA_INVALID:
127 case INTEL_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID:
128 case INTEL_GUC_LOAD_STATUS_KLV_WORKAROUND_INIT_ERROR:
129 *success = false;
130 return true;
131 }
132
133 switch (br_val) {
134 case INTEL_BOOTROM_STATUS_NO_KEY_FOUND:
135 case INTEL_BOOTROM_STATUS_RSA_FAILED:
136 case INTEL_BOOTROM_STATUS_PAVPC_FAILED:
137 case INTEL_BOOTROM_STATUS_WOPCM_FAILED:
138 case INTEL_BOOTROM_STATUS_LOADLOC_FAILED:
139 case INTEL_BOOTROM_STATUS_JUMP_FAILED:
140 case INTEL_BOOTROM_STATUS_RC6CTXCONFIG_FAILED:
141 case INTEL_BOOTROM_STATUS_MPUMAP_INCORRECT:
142 case INTEL_BOOTROM_STATUS_EXCEPTION:
143 case INTEL_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE:
144 *success = false;
145 return true;
146 }
147
148 return false;
149}
150
151/*
152 * Use a longer timeout for debug builds so that problems can be detected
153 * and analysed. But a shorter timeout for releases so that user's don't
154 * wait forever to find out there is a problem. Note that the only reason
155 * an end user should hit the timeout is in case of extreme thermal throttling.
156 * And a system that is that hot during boot is probably dead anyway!
157 */
158#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
159#define GUC_LOAD_RETRY_LIMIT 20
160#else
161#define GUC_LOAD_RETRY_LIMIT 3
162#endif
163
164static int guc_wait_ucode(struct intel_guc *guc)
165{
166 struct intel_gt *gt = guc_to_gt(guc);
167 struct intel_uncore *uncore = gt->uncore;
168 ktime_t before, after, delta;
169 bool success;
170 u32 status;
171 int ret, count;
172 u64 delta_ms;
173 u32 before_freq;
174
175 /*
176 * Wait for the GuC to start up.
177 *
178 * Measurements indicate this should take no more than 20ms
179 * (assuming the GT clock is at maximum frequency). So, a
180 * timeout here indicates that the GuC has failed and is unusable.
181 * (Higher levels of the driver may decide to reset the GuC and
182 * attempt the ucode load again if this happens.)
183 *
184 * FIXME: There is a known (but exceedingly unlikely) race condition
185 * where the asynchronous frequency management code could reduce
186 * the GT clock while a GuC reload is in progress (during a full
187 * GT reset). A fix is in progress but there are complex locking
188 * issues to be resolved. In the meantime bump the timeout to
189 * 200ms. Even at slowest clock, this should be sufficient. And
190 * in the working case, a larger timeout makes no difference.
191 *
192 * IFWI updates have also been seen to cause sporadic failures due to
193 * the requested frequency not being granted and thus the firmware
194 * load is attempted at minimum frequency. That can lead to load times
195 * in the seconds range. However, there is a limit on how long an
196 * individual wait_for() can wait. So wrap it in a loop.
197 */
198 before_freq = intel_rps_read_actual_frequency(rps: &gt->rps);
199 before = ktime_get();
200 for (count = 0; count < GUC_LOAD_RETRY_LIMIT; count++) {
201 ret = wait_for(guc_load_done(uncore, &status, &success), 1000);
202 if (!ret || !success)
203 break;
204
205 guc_dbg(guc, "load still in progress, count = %d, freq = %dMHz, status = 0x%08X [0x%02X/%02X]\n",
206 count, intel_rps_read_actual_frequency(&gt->rps), status,
207 REG_FIELD_GET(GS_BOOTROM_MASK, status),
208 REG_FIELD_GET(GS_UKERNEL_MASK, status));
209 }
210 after = ktime_get();
211 delta = ktime_sub(after, before);
212 delta_ms = ktime_to_ms(kt: delta);
213 if (ret || !success) {
214 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status);
215 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status);
216
217 guc_info(guc, "load failed: status = 0x%08X, time = %lldms, freq = %dMHz, ret = %d\n",
218 status, delta_ms, intel_rps_read_actual_frequency(&gt->rps), ret);
219 guc_info(guc, "load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n",
220 REG_FIELD_GET(GS_MIA_IN_RESET, status),
221 bootrom, ukernel,
222 REG_FIELD_GET(GS_MIA_MASK, status),
223 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
224
225 switch (bootrom) {
226 case INTEL_BOOTROM_STATUS_NO_KEY_FOUND:
227 guc_info(guc, "invalid key requested, header = 0x%08X\n",
228 intel_uncore_read(uncore, GUC_HEADER_INFO));
229 ret = -ENOEXEC;
230 break;
231
232 case INTEL_BOOTROM_STATUS_RSA_FAILED:
233 guc_info(guc, "firmware signature verification failed\n");
234 ret = -ENOEXEC;
235 break;
236
237 case INTEL_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE:
238 guc_info(guc, "firmware production part check failure\n");
239 ret = -ENOEXEC;
240 break;
241 }
242
243 switch (ukernel) {
244 case INTEL_GUC_LOAD_STATUS_EXCEPTION:
245 guc_info(guc, "firmware exception. EIP: %#x\n",
246 intel_uncore_read(uncore, SOFT_SCRATCH(13)));
247 ret = -ENXIO;
248 break;
249
250 case INTEL_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID:
251 guc_info(guc, "illegal register in save/restore workaround list\n");
252 ret = -EPERM;
253 break;
254
255 case INTEL_GUC_LOAD_STATUS_KLV_WORKAROUND_INIT_ERROR:
256 guc_info(guc, "invalid w/a KLV entry\n");
257 ret = -EINVAL;
258 break;
259
260 case INTEL_GUC_LOAD_STATUS_HWCONFIG_START:
261 guc_info(guc, "still extracting hwconfig table.\n");
262 ret = -ETIMEDOUT;
263 break;
264 }
265
266 /* Uncommon/unexpected error, see earlier status code print for details */
267 if (ret == 0)
268 ret = -ENXIO;
269 } else if (delta_ms > 200) {
270 guc_warn(guc, "excessive init time: %lldms! [status = 0x%08X, count = %d, ret = %d]\n",
271 delta_ms, status, count, ret);
272 guc_warn(guc, "excessive init time: [freq = %dMHz -> %dMHz vs %dMHz, perf_limit_reasons = 0x%08X]\n",
273 before_freq, intel_rps_read_actual_frequency(&gt->rps),
274 intel_rps_get_requested_frequency(&gt->rps),
275 intel_uncore_read(uncore, intel_gt_perf_limit_reasons_reg(gt)));
276 } else {
277 guc_dbg(guc, "init took %lldms, freq = %dMHz -> %dMHz vs %dMHz, status = 0x%08X, count = %d, ret = %d\n",
278 delta_ms, before_freq, intel_rps_read_actual_frequency(&gt->rps),
279 intel_rps_get_requested_frequency(&gt->rps), status, count, ret);
280 }
281
282 return ret;
283}
284
285/**
286 * intel_guc_fw_upload() - load GuC uCode to device
287 * @guc: intel_guc structure
288 *
289 * Called from intel_uc_init_hw() during driver load, resume from sleep and
290 * after a GPU reset.
291 *
292 * The firmware image should have already been fetched into memory, so only
293 * check that fetch succeeded, and then transfer the image to the h/w.
294 *
295 * Return: non-zero code on error
296 */
297int intel_guc_fw_upload(struct intel_guc *guc)
298{
299 struct intel_gt *gt = guc_to_gt(guc);
300 struct intel_uncore *uncore = gt->uncore;
301 int ret;
302
303 guc_prepare_xfer(gt);
304
305 /*
306 * Note that GuC needs the CSS header plus uKernel code to be copied
307 * by the DMA engine in one operation, whereas the RSA signature is
308 * loaded separately, either by copying it to the UOS_RSA_SCRATCH
309 * register (if key size <= 256) or through a ggtt-pinned vma (if key
310 * size > 256). The RSA size and therefore the way we provide it to the
311 * HW is fixed for each platform and hard-coded in the bootrom.
312 */
313 ret = guc_xfer_rsa(guc_fw: &guc->fw, uncore);
314 if (ret)
315 goto out;
316
317 /*
318 * Current uCode expects the code to be loaded at 8k; locations below
319 * this are used for the stack.
320 */
321 ret = intel_uc_fw_upload(uc_fw: &guc->fw, offset: 0x2000, UOS_MOVE);
322 if (ret)
323 goto out;
324
325 ret = guc_wait_ucode(guc);
326 if (ret)
327 goto out;
328
329 intel_uc_fw_change_status(uc_fw: &guc->fw, status: INTEL_UC_FIRMWARE_RUNNING);
330 return 0;
331
332out:
333 intel_uc_fw_change_status(uc_fw: &guc->fw, status: INTEL_UC_FIRMWARE_LOAD_FAIL);
334 return ret;
335}
336