1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
6#ifndef __INTEL_MCHBAR_REGS__
7#define __INTEL_MCHBAR_REGS__
8
9#include "i915_reg_defs.h"
10
11/*
12 * MCHBAR mirror.
13 *
14 * This mirrors the MCHBAR MMIO space whose location is determined by
15 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
16 * every way. It is not accessible from the CP register read instructions.
17 *
18 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
19 * just read.
20 */
21
22#define MCHBAR_MIRROR_BASE 0x10000
23#define MCHBAR_MIRROR_BASE_SNB 0x140000
24
25#define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
26#define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
27#define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
28#define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
29#define G4X_STOLEN_RESERVED_ENABLE (1 << 0)
30
31/* Pineview MCH register contains DDR3 setting */
32#define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
33#define CSHRDDR3CTL_DDR3 (1 << 2)
34
35/* 915-945 and GM965 MCH register controlling DRAM channel access */
36#define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
37#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
38#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
39#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
40#define DCC_ADDRESSING_MODE_MASK (3 << 0)
41#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
42#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
43#define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
44#define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
45
46/* 965 MCH register controlling DRAM channel configuration */
47#define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206)
48#define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606)
49
50/* Clocking configuration register */
51#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
52#define CLKCFG_FSB_400 (0 << 0) /* hrawclk 100 */
53#define CLKCFG_FSB_400_ALT (5 << 0) /* hrawclk 100 */
54#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
55#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
56#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
57#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
58#define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */
59#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
60#define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */
61#define CLKCFG_FSB_1600_ALT (6 << 0) /* hrawclk 400 */
62#define CLKCFG_FSB_MASK (7 << 0)
63#define CLKCFG_MEM_533 (1 << 4)
64#define CLKCFG_MEM_667 (2 << 4)
65#define CLKCFG_MEM_800 (3 << 4)
66#define CLKCFG_MEM_MASK (7 << 4)
67
68#define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
69#define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
70
71#define TSC1 _MMIO(MCHBAR_MIRROR_BASE + 0x1001)
72#define TSE (1 << 0)
73#define TR1 _MMIO(MCHBAR_MIRROR_BASE + 0x1006)
74#define TSFS _MMIO(MCHBAR_MIRROR_BASE + 0x1020)
75#define TSFS_SLOPE_MASK 0x0000ff00
76#define TSFS_SLOPE_SHIFT 8
77#define TSFS_INTR_MASK 0x000000ff
78
79/* Memory latency timer register */
80#define MLTR_ILK _MMIO(MCHBAR_MIRROR_BASE + 0x1222)
81/* the unit of memory self-refresh latency time is 0.5us */
82#define MLTR_WM2_MASK REG_GENMASK(13, 8)
83#define MLTR_WM1_MASK REG_GENMASK(5, 0)
84
85#define CSIPLL0 _MMIO(MCHBAR_MIRROR_BASE + 0x2c10)
86#define DDRMPLL1 _MMIO(MCHBAR_MIRROR_BASE + 0x2c20)
87
88#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
89#define ILK_GRDOM_FULL (0 << 1)
90#define ILK_GRDOM_RENDER (1 << 1)
91#define ILK_GRDOM_MEDIA (3 << 1)
92#define ILK_GRDOM_MASK (3 << 1)
93#define ILK_GRDOM_RESET_ENABLE (1 << 0)
94
95#define BXT_D_CR_DRP0_DUNIT8 0x1000
96#define BXT_D_CR_DRP0_DUNIT9 0x1200
97#define BXT_D_CR_DRP0_DUNIT_START 8
98#define BXT_D_CR_DRP0_DUNIT_END 11
99#define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \
100 _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
101 BXT_D_CR_DRP0_DUNIT9))
102#define BXT_DRAM_RANK_MASK 0x3
103#define BXT_DRAM_RANK_SINGLE 0x1
104#define BXT_DRAM_RANK_DUAL 0x3
105#define BXT_DRAM_WIDTH_MASK (0x3 << 4)
106#define BXT_DRAM_WIDTH_SHIFT 4
107#define BXT_DRAM_WIDTH_X8 (0x0 << 4)
108#define BXT_DRAM_WIDTH_X16 (0x1 << 4)
109#define BXT_DRAM_WIDTH_X32 (0x2 << 4)
110#define BXT_DRAM_WIDTH_X64 (0x3 << 4)
111#define BXT_DRAM_SIZE_MASK (0x7 << 6)
112#define BXT_DRAM_SIZE_SHIFT 6
113#define BXT_DRAM_SIZE_4GBIT (0x0 << 6)
114#define BXT_DRAM_SIZE_6GBIT (0x1 << 6)
115#define BXT_DRAM_SIZE_8GBIT (0x2 << 6)
116#define BXT_DRAM_SIZE_12GBIT (0x3 << 6)
117#define BXT_DRAM_SIZE_16GBIT (0x4 << 6)
118#define BXT_DRAM_TYPE_MASK (0x7 << 22)
119#define BXT_DRAM_TYPE_SHIFT 22
120#define BXT_DRAM_TYPE_DDR3 (0x0 << 22)
121#define BXT_DRAM_TYPE_LPDDR3 (0x1 << 22)
122#define BXT_DRAM_TYPE_LPDDR4 (0x2 << 22)
123#define BXT_DRAM_TYPE_DDR4 (0x4 << 22)
124
125#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
126#define DG1_DRAM_T_RDPRE_MASK REG_GENMASK(16, 11)
127#define DG1_DRAM_T_RP_MASK REG_GENMASK(6, 0)
128#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)
129#define DG1_DRAM_T_RCD_MASK REG_GENMASK(15, 9)
130#define DG1_DRAM_T_RAS_MASK REG_GENMASK(8, 1)
131
132#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
133#define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0)
134#define SKL_DRAM_DDR_TYPE_DDR4 (0 << 0)
135#define SKL_DRAM_DDR_TYPE_DDR3 (1 << 0)
136#define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
137#define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
138
139/* snb MCH registers for reading the DRAM channel configuration */
140#define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
141#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
142#define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
143#define MAD_DIMM_ECC_MASK (0x3 << 24)
144#define MAD_DIMM_ECC_OFF (0x0 << 24)
145#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
146#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
147#define MAD_DIMM_ECC_ON (0x3 << 24)
148#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
149#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
150#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
151#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
152#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
153#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
154#define MAD_DIMM_A_SELECT (0x1 << 16)
155/* DIMM sizes are in multiples of 256mb. */
156#define MAD_DIMM_B_SIZE_SHIFT 8
157#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
158#define MAD_DIMM_A_SIZE_SHIFT 0
159#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
160
161#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
162#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
163#define SKL_DRAM_S_SHIFT 16
164#define SKL_DRAM_SIZE_MASK 0x3F
165#define SKL_DRAM_WIDTH_MASK (0x3 << 8)
166#define SKL_DRAM_WIDTH_SHIFT 8
167#define SKL_DRAM_WIDTH_X8 (0x0 << 8)
168#define SKL_DRAM_WIDTH_X16 (0x1 << 8)
169#define SKL_DRAM_WIDTH_X32 (0x2 << 8)
170#define SKL_DRAM_RANK_MASK (0x1 << 10)
171#define SKL_DRAM_RANK_SHIFT 10
172#define SKL_DRAM_RANK_1 (0x0 << 10)
173#define SKL_DRAM_RANK_2 (0x1 << 10)
174#define SKL_DRAM_RANK_MASK (0x1 << 10)
175#define ICL_DRAM_SIZE_MASK 0x7F
176#define ICL_DRAM_WIDTH_MASK (0x3 << 7)
177#define ICL_DRAM_WIDTH_SHIFT 7
178#define ICL_DRAM_WIDTH_X8 (0x0 << 7)
179#define ICL_DRAM_WIDTH_X16 (0x1 << 7)
180#define ICL_DRAM_WIDTH_X32 (0x2 << 7)
181#define ICL_DRAM_RANK_MASK (0x3 << 9)
182#define ICL_DRAM_RANK_SHIFT 9
183#define ICL_DRAM_RANK_1 (0x0 << 9)
184#define ICL_DRAM_RANK_2 (0x1 << 9)
185#define ICL_DRAM_RANK_3 (0x2 << 9)
186#define ICL_DRAM_RANK_4 (0x3 << 9)
187
188#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
189#define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)
190#define DG1_QCLK_REFERENCE REG_BIT(10)
191
192/*
193 * *_PACKAGE_POWER_SKU - SKU power and timing parameters.
194 */
195#define PCU_PACKAGE_POWER_SKU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5930)
196#define PKG_PKG_TDP GENMASK_ULL(14, 0)
197#define PKG_MIN_PWR GENMASK_ULL(30, 16)
198#define PKG_MAX_PWR GENMASK_ULL(46, 32)
199#define PKG_MAX_WIN GENMASK_ULL(54, 48)
200#define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
201#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
202
203#define PCU_PACKAGE_POWER_SKU_UNIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5938)
204#define PKG_PWR_UNIT REG_GENMASK(3, 0)
205#define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
206#define PKG_TIME_UNIT REG_GENMASK(19, 16)
207#define PCU_PACKAGE_ENERGY_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x593c)
208
209#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
210
211#define PCU_PACKAGE_TEMPERATURE _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5978)
212#define TEMP_MASK REG_GENMASK(7, 0)
213
214#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
215#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
216#define RP0_CAP_MASK REG_GENMASK(7, 0)
217#define RP1_CAP_MASK REG_GENMASK(15, 8)
218#define RPN_CAP_MASK REG_GENMASK(23, 16)
219
220#define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
221#define RPE_MASK REG_GENMASK(15, 8)
222#define PCU_PACKAGE_RAPL_LIMIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
223#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
224#define PKG_PWR_LIM_1_EN REG_BIT(15)
225#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17)
226#define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22)
227#define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17)
228
229/* snb MCH registers for priority tuning */
230#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
231#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
232#define SSKPD_WM4_MASK_HSW REG_GENMASK64(40, 32)
233#define SSKPD_WM3_MASK_HSW REG_GENMASK64(28, 20)
234#define SSKPD_WM2_MASK_HSW REG_GENMASK64(19, 12)
235#define SSKPD_WM1_MASK_HSW REG_GENMASK64(11, 4)
236#define SSKPD_OLD_WM0_MASK_HSW REG_GENMASK64(3, 0)
237#define SSKPD_WM3_MASK_SNB REG_GENMASK(29, 24)
238#define SSKPD_WM2_MASK_SNB REG_GENMASK(21, 16)
239#define SSKPD_WM1_MASK_SNB REG_GENMASK(13, 8)
240#define SSKPD_WM0_MASK_SNB REG_GENMASK(5, 0)
241
242/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
243#define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
244#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
245#define DG1_GEAR_TYPE REG_BIT(16)
246
247/*
248 * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
249 * since on HSW we can't write to it using intel_uncore_write.
250 */
251#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5f0c)
252#define D_COMP_RCOMP_IN_PROGRESS (1 << 9)
253#define D_COMP_COMP_FORCE (1 << 8)
254#define D_COMP_COMP_DISABLE (1 << 0)
255
256#define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
257
258#endif /* __INTEL_MCHBAR_REGS */
259