| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 
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| 2 | /* Copyright(c) 1999 - 2018 Intel Corporation. */ | 
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| 3 |  | 
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| 4 | #ifndef _E1000E_82571_H_ | 
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| 5 | #define _E1000E_82571_H_ | 
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| 6 |  | 
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| 7 | #define ID_LED_RESERVED_F746	0xF746 | 
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| 8 | #define ID_LED_DEFAULT_82573	((ID_LED_DEF1_DEF2 << 12) | \ | 
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| 9 | (ID_LED_OFF1_ON2  <<  8) | \ | 
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| 10 | (ID_LED_DEF1_DEF2 <<  4) | \ | 
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| 11 | (ID_LED_DEF1_DEF2)) | 
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| 12 |  | 
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| 13 | #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX	0x08000000 | 
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| 14 | #define AN_RETRY_COUNT		5	/* Autoneg Retry Count value */ | 
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| 15 |  | 
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| 16 | /* Intr Throttling - RW */ | 
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| 17 | #define E1000_EITR_82574(_n)	(0x000E8 + (0x4 * (_n))) | 
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| 18 |  | 
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| 19 | #define E1000_EIAC_82574	0x000DC	/* Ext. Interrupt Auto Clear - RW */ | 
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| 20 | #define E1000_EIAC_MASK_82574	0x01F00000 | 
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| 21 |  | 
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| 22 | #define E1000_IVAR_INT_ALLOC_VALID	0x8 | 
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| 23 |  | 
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| 24 | /* Manageability Operation Mode mask */ | 
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| 25 | #define E1000_NVM_INIT_CTRL2_MNGM	0x6000 | 
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| 26 |  | 
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| 27 | #define E1000_BASE1000T_STATUS		10 | 
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| 28 | #define E1000_IDLE_ERROR_COUNT_MASK	0xFF | 
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| 29 | #define E1000_RECEIVE_ERROR_COUNTER	21 | 
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| 30 | #define E1000_RECEIVE_ERROR_MAX		0xFFFF | 
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| 31 | bool e1000_check_phy_82574(struct e1000_hw *hw); | 
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| 32 | bool e1000e_get_laa_state_82571(struct e1000_hw *hw); | 
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| 33 | void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state); | 
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| 34 |  | 
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| 35 | #endif | 
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| 36 |  | 
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