1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef DRIVERS_PCI_H
3#define DRIVERS_PCI_H
4
5#include <linux/align.h>
6#include <linux/bitfield.h>
7#include <linux/pci.h>
8
9struct pcie_tlp_log;
10
11/* Number of possible devfns: 0.0 to 1f.7 inclusive */
12#define MAX_NR_DEVFNS 256
13#define PCI_MAX_NR_DEVS 32
14
15#define MAX_NR_LANES 16
16
17#define PCI_FIND_CAP_TTL 48
18
19#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
20
21#define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000
22
23/*
24 * Power stable to PERST# inactive.
25 *
26 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express
27 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol
28 * "T_PVPERL".
29 */
30#define PCIE_T_PVPERL_MS 100
31
32/*
33 * REFCLK stable before PERST# inactive.
34 *
35 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express
36 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol
37 * "T_PERST-CLK".
38 */
39#define PCIE_T_PERST_CLK_US 100
40
41/*
42 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
43 * Recommends 1ms to 10ms timeout to check L2 ready.
44 */
45#define PCIE_PME_TO_L2_TIMEOUT_US 10000
46
47/*
48 * PCIe r6.0, sec 6.6.1 <Conventional Reset>
49 *
50 * - "With a Downstream Port that does not support Link speeds greater
51 * than 5.0 GT/s, software must wait a minimum of 100 ms following exit
52 * from a Conventional Reset before sending a Configuration Request to
53 * the device immediately below that Port."
54 *
55 * - "With a Downstream Port that supports Link speeds greater than
56 * 5.0 GT/s, software must wait a minimum of 100 ms after Link training
57 * completes before sending a Configuration Request to the device
58 * immediately below that Port."
59 */
60#define PCIE_RESET_CONFIG_WAIT_MS 100
61
62/* Parameters for the waiting for link up routine */
63#define PCIE_LINK_WAIT_MAX_RETRIES 10
64#define PCIE_LINK_WAIT_SLEEP_MS 90
65
66/* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */
67#define PCIE_MSG_TYPE_R_RC 0
68#define PCIE_MSG_TYPE_R_ADDR 1
69#define PCIE_MSG_TYPE_R_ID 2
70#define PCIE_MSG_TYPE_R_BC 3
71#define PCIE_MSG_TYPE_R_LOCAL 4
72#define PCIE_MSG_TYPE_R_GATHER 5
73
74/* Power Management Messages; PCIe r6.0, sec 2.2.8.2 */
75#define PCIE_MSG_CODE_PME_TURN_OFF 0x19
76
77/* INTx Mechanism Messages; PCIe r6.0, sec 2.2.8.1 */
78#define PCIE_MSG_CODE_ASSERT_INTA 0x20
79#define PCIE_MSG_CODE_ASSERT_INTB 0x21
80#define PCIE_MSG_CODE_ASSERT_INTC 0x22
81#define PCIE_MSG_CODE_ASSERT_INTD 0x23
82#define PCIE_MSG_CODE_DEASSERT_INTA 0x24
83#define PCIE_MSG_CODE_DEASSERT_INTB 0x25
84#define PCIE_MSG_CODE_DEASSERT_INTC 0x26
85#define PCIE_MSG_CODE_DEASSERT_INTD 0x27
86
87#define PCI_BUS_BRIDGE_IO_WINDOW 0
88#define PCI_BUS_BRIDGE_MEM_WINDOW 1
89#define PCI_BUS_BRIDGE_PREF_MEM_WINDOW 2
90
91extern const unsigned char pcie_link_speed[];
92extern bool pci_early_dump;
93
94extern struct mutex pci_rescan_remove_lock;
95
96bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
97bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
98bool pcie_cap_has_rtctl(const struct pci_dev *dev);
99
100/* Standard Capability finder */
101/**
102 * PCI_FIND_NEXT_CAP - Find a PCI standard capability
103 * @read_cfg: Function pointer for reading PCI config space
104 * @start: Starting position to begin search
105 * @cap: Capability ID to find
106 * @args: Arguments to pass to read_cfg function
107 *
108 * Search the capability list in PCI config space to find @cap.
109 * Implements TTL (time-to-live) protection against infinite loops.
110 *
111 * Return: Position of the capability if found, 0 otherwise.
112 */
113#define PCI_FIND_NEXT_CAP(read_cfg, start, cap, args...) \
114({ \
115 int __ttl = PCI_FIND_CAP_TTL; \
116 u8 __id, __found_pos = 0; \
117 u8 __pos = (start); \
118 u16 __ent; \
119 \
120 read_cfg##_byte(args, __pos, &__pos); \
121 \
122 while (__ttl--) { \
123 if (__pos < PCI_STD_HEADER_SIZEOF) \
124 break; \
125 \
126 __pos = ALIGN_DOWN(__pos, 4); \
127 read_cfg##_word(args, __pos, &__ent); \
128 \
129 __id = FIELD_GET(PCI_CAP_ID_MASK, __ent); \
130 if (__id == 0xff) \
131 break; \
132 \
133 if (__id == (cap)) { \
134 __found_pos = __pos; \
135 break; \
136 } \
137 \
138 __pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, __ent); \
139 } \
140 __found_pos; \
141})
142
143/* Extended Capability finder */
144/**
145 * PCI_FIND_NEXT_EXT_CAP - Find a PCI extended capability
146 * @read_cfg: Function pointer for reading PCI config space
147 * @start: Starting position to begin search (0 for initial search)
148 * @cap: Extended capability ID to find
149 * @args: Arguments to pass to read_cfg function
150 *
151 * Search the extended capability list in PCI config space to find @cap.
152 * Implements TTL protection against infinite loops using a calculated
153 * maximum search count.
154 *
155 * Return: Position of the capability if found, 0 otherwise.
156 */
157#define PCI_FIND_NEXT_EXT_CAP(read_cfg, start, cap, args...) \
158({ \
159 u16 __pos = (start) ?: PCI_CFG_SPACE_SIZE; \
160 u16 __found_pos = 0; \
161 int __ttl, __ret; \
162 u32 __header; \
163 \
164 __ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; \
165 while (__ttl-- > 0 && __pos >= PCI_CFG_SPACE_SIZE) { \
166 __ret = read_cfg##_dword(args, __pos, &__header); \
167 if (__ret != PCIBIOS_SUCCESSFUL) \
168 break; \
169 \
170 if (__header == 0) \
171 break; \
172 \
173 if (PCI_EXT_CAP_ID(__header) == (cap) && __pos != start) {\
174 __found_pos = __pos; \
175 break; \
176 } \
177 \
178 __pos = PCI_EXT_CAP_NEXT(__header); \
179 } \
180 __found_pos; \
181})
182
183/* Functions internal to the PCI core code */
184
185#ifdef CONFIG_DMI
186extern const struct attribute_group pci_dev_smbios_attr_group;
187#endif
188
189enum pci_mmap_api {
190 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
191 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
192};
193int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
194 enum pci_mmap_api mmap_api);
195
196bool pci_reset_supported(struct pci_dev *dev);
197void pci_init_reset_methods(struct pci_dev *dev);
198int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
199int pci_bus_error_reset(struct pci_dev *dev);
200int __pci_reset_bus(struct pci_bus *bus);
201
202struct pci_cap_saved_data {
203 u16 cap_nr;
204 bool cap_extended;
205 unsigned int size;
206 u32 data[];
207};
208
209struct pci_cap_saved_state {
210 struct hlist_node next;
211 struct pci_cap_saved_data cap;
212};
213
214void pci_allocate_cap_save_buffers(struct pci_dev *dev);
215void pci_free_cap_save_buffers(struct pci_dev *dev);
216int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
217int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
218 u16 cap, unsigned int size);
219struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
220struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
221 u16 cap);
222
223#define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
224#define PCI_PM_D3HOT_WAIT 10 /* msec */
225#define PCI_PM_D3COLD_WAIT 100 /* msec */
226
227void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
228void pci_refresh_power_state(struct pci_dev *dev);
229int pci_power_up(struct pci_dev *dev);
230void pci_disable_enabled_device(struct pci_dev *dev);
231int pci_finish_runtime_suspend(struct pci_dev *dev);
232void pcie_clear_device_status(struct pci_dev *dev);
233void pcie_clear_root_pme_status(struct pci_dev *dev);
234bool pci_check_pme_status(struct pci_dev *dev);
235void pci_pme_wakeup_bus(struct pci_bus *bus);
236void pci_pme_restore(struct pci_dev *dev);
237bool pci_dev_need_resume(struct pci_dev *dev);
238void pci_dev_adjust_pme(struct pci_dev *dev);
239void pci_dev_complete_resume(struct pci_dev *pci_dev);
240void pci_config_pm_runtime_get(struct pci_dev *dev);
241void pci_config_pm_runtime_put(struct pci_dev *dev);
242void pci_pm_power_up_and_verify_state(struct pci_dev *pci_dev);
243void pci_pm_init(struct pci_dev *dev);
244void pci_ea_init(struct pci_dev *dev);
245void pci_msi_init(struct pci_dev *dev);
246void pci_msix_init(struct pci_dev *dev);
247bool pci_bridge_d3_possible(struct pci_dev *dev);
248void pci_bridge_d3_update(struct pci_dev *dev);
249int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);
250
251static inline bool pci_bus_rrs_vendor_id(u32 l)
252{
253 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG;
254}
255
256static inline void pci_wakeup_event(struct pci_dev *dev)
257{
258 /* Wait 100 ms before the system can be put into a sleep state. */
259 pm_wakeup_event(dev: &dev->dev, msec: 100);
260}
261
262/**
263 * pci_bar_index_is_valid - Check whether a BAR index is within valid range
264 * @bar: BAR index
265 *
266 * Protects against overflowing &struct pci_dev.resource array.
267 *
268 * Return: true for valid index, false otherwise.
269 */
270static inline bool pci_bar_index_is_valid(int bar)
271{
272 if (bar >= 0 && bar < PCI_NUM_RESOURCES)
273 return true;
274
275 return false;
276}
277
278static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
279{
280 return !!(pci_dev->subordinate);
281}
282
283static inline bool pci_power_manageable(struct pci_dev *pci_dev)
284{
285 /*
286 * Currently we allow normal PCI devices and PCI bridges transition
287 * into D3 if their bridge_d3 is set.
288 */
289 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
290}
291
292static inline bool pcie_downstream_port(const struct pci_dev *dev)
293{
294 int type = pci_pcie_type(dev);
295
296 return type == PCI_EXP_TYPE_ROOT_PORT ||
297 type == PCI_EXP_TYPE_DOWNSTREAM ||
298 type == PCI_EXP_TYPE_PCIE_BRIDGE;
299}
300
301void pci_vpd_init(struct pci_dev *dev);
302extern const struct attribute_group pci_dev_vpd_attr_group;
303
304/* PCI Virtual Channel */
305int pci_save_vc_state(struct pci_dev *dev);
306void pci_restore_vc_state(struct pci_dev *dev);
307void pci_allocate_vc_save_buffers(struct pci_dev *dev);
308
309/* PCI /proc functions */
310#ifdef CONFIG_PROC_FS
311int pci_proc_attach_device(struct pci_dev *dev);
312int pci_proc_detach_device(struct pci_dev *dev);
313int pci_proc_detach_bus(struct pci_bus *bus);
314#else
315static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
316static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
317static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
318#endif
319
320/* Functions for PCI Hotplug drivers to use */
321int pci_hp_add_bridge(struct pci_dev *dev);
322bool pci_hp_spurious_link_change(struct pci_dev *pdev);
323
324#if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY)
325void pci_create_legacy_files(struct pci_bus *bus);
326void pci_remove_legacy_files(struct pci_bus *bus);
327#else
328static inline void pci_create_legacy_files(struct pci_bus *bus) { }
329static inline void pci_remove_legacy_files(struct pci_bus *bus) { }
330#endif
331
332/* Lock for read/write access to pci device and bus lists */
333extern struct rw_semaphore pci_bus_sem;
334extern struct mutex pci_slot_mutex;
335
336extern raw_spinlock_t pci_lock;
337
338extern unsigned int pci_pm_d3hot_delay;
339
340#ifdef CONFIG_PCI_MSI
341void pci_no_msi(void);
342#else
343static inline void pci_no_msi(void) { }
344#endif
345
346void pci_realloc_get_opt(char *);
347
348static inline int pci_no_d1d2(struct pci_dev *dev)
349{
350 unsigned int parent_dstates = 0;
351
352 if (dev->bus->self)
353 parent_dstates = dev->bus->self->no_d1d2;
354 return (dev->no_d1d2 || parent_dstates);
355
356}
357
358#ifdef CONFIG_SYSFS
359int pci_create_sysfs_dev_files(struct pci_dev *pdev);
360void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
361extern const struct attribute_group *pci_dev_groups[];
362extern const struct attribute_group *pci_dev_attr_groups[];
363extern const struct attribute_group *pcibus_groups[];
364extern const struct attribute_group *pci_bus_groups[];
365extern const struct attribute_group pci_doe_sysfs_group;
366#else
367static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; }
368static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { }
369#define pci_dev_groups NULL
370#define pci_dev_attr_groups NULL
371#define pcibus_groups NULL
372#define pci_bus_groups NULL
373#endif
374
375extern unsigned long pci_hotplug_io_size;
376extern unsigned long pci_hotplug_mmio_size;
377extern unsigned long pci_hotplug_mmio_pref_size;
378extern unsigned long pci_hotplug_bus_size;
379extern unsigned long pci_cardbus_io_size;
380extern unsigned long pci_cardbus_mem_size;
381
382/**
383 * pci_match_one_device - Tell if a PCI device structure has a matching
384 * PCI device id structure
385 * @id: single PCI device id structure to match
386 * @dev: the PCI device structure to match against
387 *
388 * Returns the matching pci_device_id structure or %NULL if there is no match.
389 */
390static inline const struct pci_device_id *
391pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
392{
393 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
394 (id->device == PCI_ANY_ID || id->device == dev->device) &&
395 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
396 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
397 !((id->class ^ dev->class) & id->class_mask))
398 return id;
399 return NULL;
400}
401
402/* PCI slot sysfs helper code */
403#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
404
405extern struct kset *pci_slots_kset;
406
407struct pci_slot_attribute {
408 struct attribute attr;
409 ssize_t (*show)(struct pci_slot *, char *);
410 ssize_t (*store)(struct pci_slot *, const char *, size_t);
411};
412#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
413
414enum pci_bar_type {
415 pci_bar_unknown, /* Standard PCI BAR probe */
416 pci_bar_io, /* An I/O port BAR */
417 pci_bar_mem32, /* A 32-bit memory BAR */
418 pci_bar_mem64, /* A 64-bit memory BAR */
419};
420
421struct device *pci_get_host_bridge_device(struct pci_dev *dev);
422void pci_put_host_bridge_device(struct device *dev);
423
424unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
425int pbus_reassign_bridge_resources(struct pci_bus *bus, struct resource *res);
426int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
427
428int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
429bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
430 int rrs_timeout);
431bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
432 int rrs_timeout);
433int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int rrs_timeout);
434
435int pci_setup_device(struct pci_dev *dev);
436void __pci_size_stdbars(struct pci_dev *dev, int count,
437 unsigned int pos, u32 *sizes);
438int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
439 struct resource *res, unsigned int reg, u32 *sizes);
440void pci_configure_ari(struct pci_dev *dev);
441void __pci_bus_size_bridges(struct pci_bus *bus,
442 struct list_head *realloc_head);
443void __pci_bus_assign_resources(const struct pci_bus *bus,
444 struct list_head *realloc_head,
445 struct list_head *fail_head);
446bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
447void pci_walk_bus_locked(struct pci_bus *top,
448 int (*cb)(struct pci_dev *, void *),
449 void *userdata);
450
451const char *pci_resource_name(struct pci_dev *dev, unsigned int i);
452bool pci_resource_is_optional(const struct pci_dev *dev, int resno);
453
454/**
455 * pci_resource_num - Reverse lookup resource number from device resources
456 * @dev: PCI device
457 * @res: Resource to lookup index for (MUST be a @dev's resource)
458 *
459 * Perform reverse lookup to determine the resource number for @res within
460 * @dev resource array. NOTE: The caller is responsible for ensuring @res is
461 * among @dev's resources!
462 *
463 * Returns: resource number.
464 */
465static inline int pci_resource_num(const struct pci_dev *dev,
466 const struct resource *res)
467{
468 int resno = res - &dev->resource[0];
469
470 /* Passing a resource that is not among dev's resources? */
471 WARN_ON_ONCE(resno >= PCI_NUM_RESOURCES);
472
473 return resno;
474}
475
476struct resource *pbus_select_window(struct pci_bus *bus,
477 const struct resource *res);
478void pci_reassigndev_resource_alignment(struct pci_dev *dev);
479void pci_disable_bridge_window(struct pci_dev *dev);
480struct pci_bus *pci_bus_get(struct pci_bus *bus);
481void pci_bus_put(struct pci_bus *bus);
482
483#define PCIE_LNKCAP_SLS2SPEED(lnkcap) \
484({ \
485 u32 lnkcap_sls = (lnkcap) & PCI_EXP_LNKCAP_SLS; \
486 \
487 (lnkcap_sls == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
488 lnkcap_sls == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
489 lnkcap_sls == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
490 lnkcap_sls == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
491 lnkcap_sls == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
492 lnkcap_sls == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
493 PCI_SPEED_UNKNOWN); \
494})
495
496/* PCIe link information from Link Capabilities 2 */
497#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
498 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
499 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
500 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
501 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
502 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
503 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
504 PCI_SPEED_UNKNOWN)
505
506#define PCIE_LNKCTL2_TLS2SPEED(lnkctl2) \
507({ \
508 u16 lnkctl2_tls = (lnkctl2) & PCI_EXP_LNKCTL2_TLS; \
509 \
510 (lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \
511 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \
512 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \
513 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \
514 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \
515 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \
516 PCI_SPEED_UNKNOWN); \
517})
518
519/* PCIe speed to Mb/s reduced by encoding overhead */
520#define PCIE_SPEED2MBS_ENC(speed) \
521 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \
522 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
523 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
524 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
525 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
526 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
527 0)
528
529static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)
530{
531 switch (speed) {
532 case PCIE_SPEED_2_5GT:
533 return 2500;
534 case PCIE_SPEED_5_0GT:
535 return 5000;
536 case PCIE_SPEED_8_0GT:
537 return 8000;
538 case PCIE_SPEED_16_0GT:
539 return 16000;
540 case PCIE_SPEED_32_0GT:
541 return 32000;
542 case PCIE_SPEED_64_0GT:
543 return 64000;
544 default:
545 break;
546 }
547
548 return -EINVAL;
549}
550
551u8 pcie_get_supported_speeds(struct pci_dev *dev);
552const char *pci_speed_string(enum pci_bus_speed speed);
553void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
554void pcie_report_downtraining(struct pci_dev *dev);
555
556static inline void __pcie_update_link_speed(struct pci_bus *bus, u16 linksta, u16 linksta2)
557{
558 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
559 bus->flit_mode = (linksta2 & PCI_EXP_LNKSTA2_FLIT) ? 1 : 0;
560}
561void pcie_update_link_speed(struct pci_bus *bus);
562
563/* Single Root I/O Virtualization */
564struct pci_sriov {
565 int pos; /* Capability position */
566 int nres; /* Number of resources */
567 u32 cap; /* SR-IOV Capabilities */
568 u16 ctrl; /* SR-IOV Control */
569 u16 total_VFs; /* Total VFs associated with the PF */
570 u16 initial_VFs; /* Initial VFs associated with the PF */
571 u16 num_VFs; /* Number of VFs available */
572 u16 offset; /* First VF Routing ID offset */
573 u16 stride; /* Following VF stride */
574 u16 vf_device; /* VF device ID */
575 u32 pgsz; /* Page size for BAR alignment */
576 u8 link; /* Function Dependency Link */
577 u8 max_VF_buses; /* Max buses consumed by VFs */
578 u16 driver_max_VFs; /* Max num VFs driver supports */
579 struct pci_dev *dev; /* Lowest numbered PF */
580 struct pci_dev *self; /* This PF */
581 u32 class; /* VF device */
582 u8 hdr_type; /* VF header type */
583 u16 subsystem_vendor; /* VF subsystem vendor */
584 u16 subsystem_device; /* VF subsystem device */
585 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
586 u16 vf_rebar_cap; /* VF Resizable BAR capability offset */
587 bool drivers_autoprobe; /* Auto probing of VFs by driver */
588};
589
590#ifdef CONFIG_PCI_DOE
591void pci_doe_init(struct pci_dev *pdev);
592void pci_doe_destroy(struct pci_dev *pdev);
593void pci_doe_disconnected(struct pci_dev *pdev);
594#else
595static inline void pci_doe_init(struct pci_dev *pdev) { }
596static inline void pci_doe_destroy(struct pci_dev *pdev) { }
597static inline void pci_doe_disconnected(struct pci_dev *pdev) { }
598#endif
599
600#ifdef CONFIG_PCI_NPEM
601void pci_npem_create(struct pci_dev *dev);
602void pci_npem_remove(struct pci_dev *dev);
603#else
604static inline void pci_npem_create(struct pci_dev *dev) { }
605static inline void pci_npem_remove(struct pci_dev *dev) { }
606#endif
607
608#if defined(CONFIG_PCI_DOE) && defined(CONFIG_SYSFS)
609void pci_doe_sysfs_init(struct pci_dev *pci_dev);
610void pci_doe_sysfs_teardown(struct pci_dev *pdev);
611#else
612static inline void pci_doe_sysfs_init(struct pci_dev *pdev) { }
613static inline void pci_doe_sysfs_teardown(struct pci_dev *pdev) { }
614#endif
615
616/**
617 * pci_dev_set_io_state - Set the new error state if possible.
618 *
619 * @dev: PCI device to set new error_state
620 * @new: the state we want dev to be in
621 *
622 * If the device is experiencing perm_failure, it has to remain in that state.
623 * Any other transition is allowed.
624 *
625 * Returns true if state has been changed to the requested state.
626 */
627static inline bool pci_dev_set_io_state(struct pci_dev *dev,
628 pci_channel_state_t new)
629{
630 pci_channel_state_t old;
631
632 switch (new) {
633 case pci_channel_io_perm_failure:
634 xchg(&dev->error_state, pci_channel_io_perm_failure);
635 return true;
636 case pci_channel_io_frozen:
637 old = cmpxchg(&dev->error_state, pci_channel_io_normal,
638 pci_channel_io_frozen);
639 return old != pci_channel_io_perm_failure;
640 case pci_channel_io_normal:
641 old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
642 pci_channel_io_normal);
643 return old != pci_channel_io_perm_failure;
644 default:
645 return false;
646 }
647}
648
649static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
650{
651 pci_dev_set_io_state(dev, new: pci_channel_io_perm_failure);
652 pci_doe_disconnected(pdev: dev);
653
654 return 0;
655}
656
657/* pci_dev priv_flags */
658#define PCI_DEV_ADDED 0
659#define PCI_DPC_RECOVERED 1
660#define PCI_DPC_RECOVERING 2
661#define PCI_DEV_REMOVED 3
662#define PCI_LINK_CHANGED 4
663#define PCI_LINK_CHANGING 5
664#define PCI_LINK_LBMS_SEEN 6
665#define PCI_DEV_ALLOW_BINDING 7
666
667static inline void pci_dev_assign_added(struct pci_dev *dev)
668{
669 smp_mb__before_atomic();
670 set_bit(PCI_DEV_ADDED, addr: &dev->priv_flags);
671 smp_mb__after_atomic();
672}
673
674static inline bool pci_dev_test_and_clear_added(struct pci_dev *dev)
675{
676 return test_and_clear_bit(PCI_DEV_ADDED, addr: &dev->priv_flags);
677}
678
679static inline bool pci_dev_is_added(const struct pci_dev *dev)
680{
681 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
682}
683
684static inline bool pci_dev_test_and_set_removed(struct pci_dev *dev)
685{
686 return test_and_set_bit(PCI_DEV_REMOVED, addr: &dev->priv_flags);
687}
688
689static inline void pci_dev_allow_binding(struct pci_dev *dev)
690{
691 set_bit(PCI_DEV_ALLOW_BINDING, addr: &dev->priv_flags);
692}
693
694static inline bool pci_dev_binding_disallowed(struct pci_dev *dev)
695{
696 return !test_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags);
697}
698
699#ifdef CONFIG_PCIEAER
700#include <linux/aer.h>
701
702#define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
703
704struct aer_err_info {
705 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
706 int ratelimit_print[AER_MAX_MULTI_ERR_DEVICES];
707 int error_dev_num;
708 const char *level; /* printk level */
709
710 unsigned int id:16;
711
712 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
713 unsigned int root_ratelimit_print:1; /* 0=skip, 1=print */
714 unsigned int __pad1:4;
715 unsigned int multi_error_valid:1;
716
717 unsigned int first_error:5;
718 unsigned int __pad2:2;
719 unsigned int tlp_header_valid:1;
720
721 unsigned int status; /* COR/UNCOR Error Status */
722 unsigned int mask; /* COR/UNCOR Error Mask */
723 struct pcie_tlp_log tlp; /* TLP Header */
724};
725
726int aer_get_device_error_info(struct aer_err_info *info, int i);
727void aer_print_error(struct aer_err_info *info, int i);
728
729int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2,
730 unsigned int tlp_len, bool flit,
731 struct pcie_tlp_log *log);
732unsigned int aer_tlp_log_len(struct pci_dev *dev, u32 aercc);
733void pcie_print_tlp_log(const struct pci_dev *dev,
734 const struct pcie_tlp_log *log, const char *level,
735 const char *pfx);
736#endif /* CONFIG_PCIEAER */
737
738#ifdef CONFIG_PCIEPORTBUS
739/* Cached RCEC Endpoint Association */
740struct rcec_ea {
741 u8 nextbusn;
742 u8 lastbusn;
743 u32 bitmap;
744};
745#endif
746
747#ifdef CONFIG_PCIE_DPC
748void pci_save_dpc_state(struct pci_dev *dev);
749void pci_restore_dpc_state(struct pci_dev *dev);
750void pci_dpc_init(struct pci_dev *pdev);
751void dpc_process_error(struct pci_dev *pdev);
752pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
753bool pci_dpc_recovered(struct pci_dev *pdev);
754unsigned int dpc_tlp_log_len(struct pci_dev *dev);
755#else
756static inline void pci_save_dpc_state(struct pci_dev *dev) { }
757static inline void pci_restore_dpc_state(struct pci_dev *dev) { }
758static inline void pci_dpc_init(struct pci_dev *pdev) { }
759static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
760#endif
761
762#ifdef CONFIG_PCIEPORTBUS
763void pci_rcec_init(struct pci_dev *dev);
764void pci_rcec_exit(struct pci_dev *dev);
765void pcie_link_rcec(struct pci_dev *rcec);
766void pcie_walk_rcec(struct pci_dev *rcec,
767 int (*cb)(struct pci_dev *, void *),
768 void *userdata);
769#else
770static inline void pci_rcec_init(struct pci_dev *dev) { }
771static inline void pci_rcec_exit(struct pci_dev *dev) { }
772static inline void pcie_link_rcec(struct pci_dev *rcec) { }
773static inline void pcie_walk_rcec(struct pci_dev *rcec,
774 int (*cb)(struct pci_dev *, void *),
775 void *userdata) { }
776#endif
777
778#ifdef CONFIG_PCI_ATS
779/* Address Translation Service */
780void pci_ats_init(struct pci_dev *dev);
781void pci_restore_ats_state(struct pci_dev *dev);
782#else
783static inline void pci_ats_init(struct pci_dev *d) { }
784static inline void pci_restore_ats_state(struct pci_dev *dev) { }
785#endif /* CONFIG_PCI_ATS */
786
787#ifdef CONFIG_PCI_PRI
788void pci_pri_init(struct pci_dev *dev);
789void pci_restore_pri_state(struct pci_dev *pdev);
790#else
791static inline void pci_pri_init(struct pci_dev *dev) { }
792static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
793#endif
794
795#ifdef CONFIG_PCI_PASID
796void pci_pasid_init(struct pci_dev *dev);
797void pci_restore_pasid_state(struct pci_dev *pdev);
798#else
799static inline void pci_pasid_init(struct pci_dev *dev) { }
800static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
801#endif
802
803#ifdef CONFIG_PCI_IOV
804int pci_iov_init(struct pci_dev *dev);
805void pci_iov_release(struct pci_dev *dev);
806void pci_iov_remove(struct pci_dev *dev);
807void pci_iov_update_resource(struct pci_dev *dev, int resno);
808resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
809void pci_restore_iov_state(struct pci_dev *dev);
810int pci_iov_bus_range(struct pci_bus *bus);
811void pci_iov_resource_set_size(struct pci_dev *dev, int resno,
812 resource_size_t size);
813bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev);
814static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev)
815{
816 if (!dev->is_physfn)
817 return 0;
818
819 return dev->sriov->vf_rebar_cap;
820}
821static inline bool pci_resource_is_iov(int resno)
822{
823 return resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END;
824}
825static inline int pci_resource_num_from_vf_bar(int resno)
826{
827 return resno + PCI_IOV_RESOURCES;
828}
829static inline int pci_resource_num_to_vf_bar(int resno)
830{
831 return resno - PCI_IOV_RESOURCES;
832}
833extern const struct attribute_group sriov_pf_dev_attr_group;
834extern const struct attribute_group sriov_vf_dev_attr_group;
835#else
836static inline int pci_iov_init(struct pci_dev *dev)
837{
838 return -ENODEV;
839}
840static inline void pci_iov_release(struct pci_dev *dev) { }
841static inline void pci_iov_remove(struct pci_dev *dev) { }
842static inline void pci_iov_update_resource(struct pci_dev *dev, int resno) { }
843static inline resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev,
844 int resno)
845{
846 return 0;
847}
848static inline void pci_restore_iov_state(struct pci_dev *dev) { }
849static inline int pci_iov_bus_range(struct pci_bus *bus)
850{
851 return 0;
852}
853static inline void pci_iov_resource_set_size(struct pci_dev *dev, int resno,
854 resource_size_t size) { }
855static inline bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev)
856{
857 return false;
858}
859static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev)
860{
861 return 0;
862}
863static inline bool pci_resource_is_iov(int resno)
864{
865 return false;
866}
867static inline int pci_resource_num_from_vf_bar(int resno)
868{
869 WARN_ON_ONCE(1);
870 return -ENODEV;
871}
872static inline int pci_resource_num_to_vf_bar(int resno)
873{
874 WARN_ON_ONCE(1);
875 return -ENODEV;
876}
877#endif /* CONFIG_PCI_IOV */
878
879#ifdef CONFIG_PCIE_TPH
880void pci_restore_tph_state(struct pci_dev *dev);
881void pci_save_tph_state(struct pci_dev *dev);
882void pci_no_tph(void);
883void pci_tph_init(struct pci_dev *dev);
884#else
885static inline void pci_restore_tph_state(struct pci_dev *dev) { }
886static inline void pci_save_tph_state(struct pci_dev *dev) { }
887static inline void pci_no_tph(void) { }
888static inline void pci_tph_init(struct pci_dev *dev) { }
889#endif
890
891#ifdef CONFIG_PCIE_PTM
892void pci_ptm_init(struct pci_dev *dev);
893void pci_save_ptm_state(struct pci_dev *dev);
894void pci_restore_ptm_state(struct pci_dev *dev);
895void pci_suspend_ptm(struct pci_dev *dev);
896void pci_resume_ptm(struct pci_dev *dev);
897#else
898static inline void pci_ptm_init(struct pci_dev *dev) { }
899static inline void pci_save_ptm_state(struct pci_dev *dev) { }
900static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
901static inline void pci_suspend_ptm(struct pci_dev *dev) { }
902static inline void pci_resume_ptm(struct pci_dev *dev) { }
903#endif
904
905unsigned long pci_cardbus_resource_alignment(struct resource *);
906
907static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
908 struct resource *res)
909{
910 int resno = pci_resource_num(dev, res);
911
912 if (pci_resource_is_iov(resno))
913 return pci_sriov_resource_alignment(dev, resno);
914 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
915 return pci_cardbus_resource_alignment(res);
916 return resource_alignment(res);
917}
918
919void pci_acs_init(struct pci_dev *dev);
920#ifdef CONFIG_PCI_QUIRKS
921int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
922int pci_dev_specific_enable_acs(struct pci_dev *dev);
923int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
924int pcie_failed_link_retrain(struct pci_dev *dev);
925#else
926static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
927 u16 acs_flags)
928{
929 return -ENOTTY;
930}
931static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
932{
933 return -ENOTTY;
934}
935static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
936{
937 return -ENOTTY;
938}
939static inline int pcie_failed_link_retrain(struct pci_dev *dev)
940{
941 return -ENOTTY;
942}
943#endif
944
945/* PCI error reporting and recovery */
946pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
947 pci_channel_state_t state,
948 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
949
950bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
951int pcie_retrain_link(struct pci_dev *pdev, bool use_lt);
952
953/* ASPM-related functionality we need even without CONFIG_PCIEASPM */
954void pci_save_ltr_state(struct pci_dev *dev);
955void pci_restore_ltr_state(struct pci_dev *dev);
956void pci_configure_aspm_l1ss(struct pci_dev *dev);
957void pci_save_aspm_l1ss_state(struct pci_dev *dev);
958void pci_restore_aspm_l1ss_state(struct pci_dev *dev);
959
960#ifdef CONFIG_PCIEASPM
961void pcie_aspm_init_link_state(struct pci_dev *pdev);
962void pcie_aspm_exit_link_state(struct pci_dev *pdev);
963void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked);
964void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
965void pci_configure_ltr(struct pci_dev *pdev);
966void pci_bridge_reconfigure_ltr(struct pci_dev *pdev);
967#else
968static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
969static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
970static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { }
971static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
972static inline void pci_configure_ltr(struct pci_dev *pdev) { }
973static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { }
974#endif
975
976#ifdef CONFIG_PCIE_ECRC
977void pcie_set_ecrc_checking(struct pci_dev *dev);
978void pcie_ecrc_get_policy(char *str);
979#else
980static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
981static inline void pcie_ecrc_get_policy(char *str) { }
982#endif
983
984#ifdef CONFIG_PCIEPORTBUS
985void pcie_reset_lbms(struct pci_dev *port);
986#else
987static inline void pcie_reset_lbms(struct pci_dev *port) {}
988#endif
989
990struct pci_dev_reset_methods {
991 u16 vendor;
992 u16 device;
993 int (*reset)(struct pci_dev *dev, bool probe);
994};
995
996struct pci_reset_fn_method {
997 int (*reset_fn)(struct pci_dev *pdev, bool probe);
998 char *name;
999};
1000extern const struct pci_reset_fn_method pci_reset_fn_methods[];
1001
1002#ifdef CONFIG_PCI_QUIRKS
1003int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
1004#else
1005static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
1006{
1007 return -ENOTTY;
1008}
1009#endif
1010
1011#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
1012int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
1013 struct resource *res);
1014#else
1015static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
1016 u16 segment, struct resource *res)
1017{
1018 return -ENODEV;
1019}
1020#endif
1021
1022void pci_rebar_init(struct pci_dev *pdev);
1023int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
1024int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
1025static inline u64 pci_rebar_size_to_bytes(int size)
1026{
1027 return 1ULL << (size + 20);
1028}
1029
1030struct device_node;
1031
1032#define PCI_EQ_RESV 0xff
1033
1034enum equalization_preset_type {
1035 EQ_PRESET_TYPE_8GTS,
1036 EQ_PRESET_TYPE_16GTS,
1037 EQ_PRESET_TYPE_32GTS,
1038 EQ_PRESET_TYPE_64GTS,
1039 EQ_PRESET_TYPE_MAX
1040};
1041
1042struct pci_eq_presets {
1043 u16 eq_presets_8gts[MAX_NR_LANES];
1044 u8 eq_presets_Ngts[EQ_PRESET_TYPE_MAX - 1][MAX_NR_LANES];
1045};
1046
1047#ifdef CONFIG_OF
1048int of_get_pci_domain_nr(struct device_node *node);
1049int of_pci_get_max_link_speed(struct device_node *node);
1050u32 of_pci_get_slot_power_limit(struct device_node *node,
1051 u8 *slot_power_limit_value,
1052 u8 *slot_power_limit_scale);
1053bool of_pci_preserve_config(struct device_node *node);
1054int pci_set_of_node(struct pci_dev *dev);
1055void pci_release_of_node(struct pci_dev *dev);
1056void pci_set_bus_of_node(struct pci_bus *bus);
1057void pci_release_bus_of_node(struct pci_bus *bus);
1058
1059int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
1060bool of_pci_supply_present(struct device_node *np);
1061int of_pci_get_equalization_presets(struct device *dev,
1062 struct pci_eq_presets *presets,
1063 int num_lanes);
1064#else
1065static inline int
1066of_get_pci_domain_nr(struct device_node *node)
1067{
1068 return -1;
1069}
1070
1071static inline int
1072of_pci_get_max_link_speed(struct device_node *node)
1073{
1074 return -EINVAL;
1075}
1076
1077static inline u32
1078of_pci_get_slot_power_limit(struct device_node *node,
1079 u8 *slot_power_limit_value,
1080 u8 *slot_power_limit_scale)
1081{
1082 if (slot_power_limit_value)
1083 *slot_power_limit_value = 0;
1084 if (slot_power_limit_scale)
1085 *slot_power_limit_scale = 0;
1086 return 0;
1087}
1088
1089static inline bool of_pci_preserve_config(struct device_node *node)
1090{
1091 return false;
1092}
1093
1094static inline int pci_set_of_node(struct pci_dev *dev) { return 0; }
1095static inline void pci_release_of_node(struct pci_dev *dev) { }
1096static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1097static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1098
1099static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
1100{
1101 return 0;
1102}
1103
1104static inline bool of_pci_supply_present(struct device_node *np)
1105{
1106 return false;
1107}
1108
1109static inline int of_pci_get_equalization_presets(struct device *dev,
1110 struct pci_eq_presets *presets,
1111 int num_lanes)
1112{
1113 presets->eq_presets_8gts[0] = PCI_EQ_RESV;
1114 for (int i = 0; i < EQ_PRESET_TYPE_MAX - 1; i++)
1115 presets->eq_presets_Ngts[i][0] = PCI_EQ_RESV;
1116
1117 return 0;
1118}
1119#endif /* CONFIG_OF */
1120
1121struct of_changeset;
1122
1123#ifdef CONFIG_PCI_DYNAMIC_OF_NODES
1124void of_pci_make_dev_node(struct pci_dev *pdev);
1125void of_pci_remove_node(struct pci_dev *pdev);
1126int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs,
1127 struct device_node *np);
1128void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge);
1129void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge);
1130int of_pci_add_host_bridge_properties(struct pci_host_bridge *bridge,
1131 struct of_changeset *ocs,
1132 struct device_node *np);
1133#else
1134static inline void of_pci_make_dev_node(struct pci_dev *pdev) { }
1135static inline void of_pci_remove_node(struct pci_dev *pdev) { }
1136static inline void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge) { }
1137static inline void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge) { }
1138#endif
1139
1140#ifdef CONFIG_PCIEAER
1141void pci_no_aer(void);
1142void pci_aer_init(struct pci_dev *dev);
1143void pci_aer_exit(struct pci_dev *dev);
1144extern const struct attribute_group aer_stats_attr_group;
1145extern const struct attribute_group aer_attr_group;
1146void pci_aer_clear_fatal_status(struct pci_dev *dev);
1147int pci_aer_clear_status(struct pci_dev *dev);
1148int pci_aer_raw_clear_status(struct pci_dev *dev);
1149void pci_save_aer_state(struct pci_dev *dev);
1150void pci_restore_aer_state(struct pci_dev *dev);
1151#else
1152static inline void pci_no_aer(void) { }
1153static inline void pci_aer_init(struct pci_dev *d) { }
1154static inline void pci_aer_exit(struct pci_dev *d) { }
1155static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
1156static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
1157static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
1158static inline void pci_save_aer_state(struct pci_dev *dev) { }
1159static inline void pci_restore_aer_state(struct pci_dev *dev) { }
1160#endif
1161
1162#ifdef CONFIG_ACPI
1163bool pci_acpi_preserve_config(struct pci_host_bridge *bridge);
1164int pci_acpi_program_hp_params(struct pci_dev *dev);
1165extern const struct attribute_group pci_dev_acpi_attr_group;
1166void pci_set_acpi_fwnode(struct pci_dev *dev);
1167int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
1168bool acpi_pci_power_manageable(struct pci_dev *dev);
1169bool acpi_pci_bridge_d3(struct pci_dev *dev);
1170int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1171pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
1172void acpi_pci_refresh_power_state(struct pci_dev *dev);
1173int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
1174bool acpi_pci_need_resume(struct pci_dev *dev);
1175pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
1176#else
1177static inline bool pci_acpi_preserve_config(struct pci_host_bridge *bridge)
1178{
1179 return false;
1180}
1181static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
1182{
1183 return -ENOTTY;
1184}
1185static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { }
1186static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
1187{
1188 return -ENODEV;
1189}
1190static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
1191{
1192 return false;
1193}
1194static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
1195{
1196 return false;
1197}
1198static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1199{
1200 return -ENODEV;
1201}
1202static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
1203{
1204 return PCI_UNKNOWN;
1205}
1206static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { }
1207static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
1208{
1209 return -ENODEV;
1210}
1211static inline bool acpi_pci_need_resume(struct pci_dev *dev)
1212{
1213 return false;
1214}
1215static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
1216{
1217 return PCI_POWER_ERROR;
1218}
1219#endif
1220
1221#ifdef CONFIG_PCIEASPM
1222extern const struct attribute_group aspm_ctrl_attr_group;
1223#endif
1224
1225#ifdef CONFIG_X86_INTEL_MID
1226bool pci_use_mid_pm(void);
1227int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
1228pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
1229#else
1230static inline bool pci_use_mid_pm(void)
1231{
1232 return false;
1233}
1234static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
1235{
1236 return -ENODEV;
1237}
1238static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
1239{
1240 return PCI_UNKNOWN;
1241}
1242#endif
1243
1244#ifdef CONFIG_PCI_MSI
1245int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag);
1246#else
1247static inline int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag)
1248{
1249 return -ENODEV;
1250}
1251#endif
1252
1253/*
1254 * Config Address for PCI Configuration Mechanism #1
1255 *
1256 * See PCI Local Bus Specification, Revision 3.0,
1257 * Section 3.2.2.3.2, Figure 3-2, p. 50.
1258 */
1259
1260#define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
1261#define PCI_CONF1_DEV_SHIFT 11 /* Device number */
1262#define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
1263
1264#define PCI_CONF1_BUS_MASK 0xff
1265#define PCI_CONF1_DEV_MASK 0x1f
1266#define PCI_CONF1_FUNC_MASK 0x7
1267#define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
1268
1269#define PCI_CONF1_ENABLE BIT(31)
1270#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
1271#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
1272#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
1273#define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
1274
1275#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
1276 (PCI_CONF1_ENABLE | \
1277 PCI_CONF1_BUS(bus) | \
1278 PCI_CONF1_DEV(dev) | \
1279 PCI_CONF1_FUNC(func) | \
1280 PCI_CONF1_REG(reg))
1281
1282/*
1283 * Extension of PCI Config Address for accessing extended PCIe registers
1284 *
1285 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
1286 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
1287 * are used for specifying additional 4 high bits of PCI Express register.
1288 */
1289
1290#define PCI_CONF1_EXT_REG_SHIFT 16
1291#define PCI_CONF1_EXT_REG_MASK 0xf00
1292#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
1293
1294#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
1295 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
1296 PCI_CONF1_EXT_REG(reg))
1297
1298#endif /* DRIVERS_PCI_H */
1299