| 1 | /* | 
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| 2 | * topic.h 1.8 1999/08/28 04:01:47 | 
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| 3 | * | 
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| 4 | * The contents of this file are subject to the Mozilla Public License | 
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| 5 | * Version 1.1 (the "License"); you may not use this file except in | 
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| 6 | * compliance with the License. You may obtain a copy of the License | 
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| 7 | * at http://www.mozilla.org/MPL/ | 
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| 8 | * | 
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| 9 | * Software distributed under the License is distributed on an "AS IS" | 
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| 10 | * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See | 
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| 11 | * the License for the specific language governing rights and | 
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| 12 | * limitations under the License. | 
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| 13 | * | 
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| 14 | * The initial developer of the original code is David A. Hinds | 
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| 15 | * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds | 
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| 16 | * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved. | 
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| 17 | * | 
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| 18 | * Alternatively, the contents of this file may be used under the | 
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| 19 | * terms of the GNU General Public License version 2 (the "GPL"), in which | 
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| 20 | * case the provisions of the GPL are applicable instead of the | 
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| 21 | * above.  If you wish to allow the use of your version of this file | 
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| 22 | * only under the terms of the GPL and not to allow others to use | 
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| 23 | * your version of this file under the MPL, indicate your decision by | 
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| 24 | * deleting the provisions above and replace them with the notice and | 
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| 25 | * other provisions required by the GPL.  If you do not delete the | 
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| 26 | * provisions above, a recipient may use your version of this file | 
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| 27 | * under either the MPL or the GPL. | 
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| 28 | * topic.h $Release$ 1999/08/28 04:01:47 | 
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| 29 | */ | 
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| 30 |  | 
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| 31 | #ifndef _LINUX_TOPIC_H | 
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| 32 | #define _LINUX_TOPIC_H | 
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| 33 |  | 
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| 34 | /* Register definitions for Toshiba ToPIC95/97/100 controllers */ | 
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| 35 |  | 
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| 36 | #define TOPIC_SOCKET_CONTROL		0x0090	/* 32 bit */ | 
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| 37 | #define  TOPIC_SCR_IRQSEL		0x00000001 | 
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| 38 |  | 
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| 39 | #define TOPIC_SLOT_CONTROL		0x00a0	/* 8 bit */ | 
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| 40 | #define  TOPIC_SLOT_SLOTON		0x80 | 
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| 41 | #define  TOPIC_SLOT_SLOTEN		0x40 | 
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| 42 | #define  TOPIC_SLOT_ID_LOCK		0x20 | 
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| 43 | #define  TOPIC_SLOT_ID_WP		0x10 | 
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| 44 | #define  TOPIC_SLOT_PORT_MASK		0x0c | 
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| 45 | #define  TOPIC_SLOT_PORT_SHIFT		2 | 
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| 46 | #define  TOPIC_SLOT_OFS_MASK		0x03 | 
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| 47 |  | 
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| 48 | #define TOPIC_CARD_CONTROL		0x00a1	/* 8 bit */ | 
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| 49 | #define  TOPIC_CCR_INTB			0x20 | 
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| 50 | #define  TOPIC_CCR_INTA			0x10 | 
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| 51 | #define  TOPIC_CCR_CLOCK		0x0c | 
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| 52 | #define  TOPIC_CCR_PCICLK		0x0c | 
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| 53 | #define  TOPIC_CCR_PCICLK_2		0x08 | 
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| 54 | #define  TOPIC_CCR_CCLK			0x04 | 
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| 55 |  | 
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| 56 | #define TOPIC97_INT_CONTROL		0x00a1	/* 8 bit */ | 
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| 57 | #define  TOPIC97_ICR_INTB		0x20 | 
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| 58 | #define  TOPIC97_ICR_INTA		0x10 | 
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| 59 | #define  TOPIC97_ICR_STSIRQNP		0x04 | 
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| 60 | #define  TOPIC97_ICR_IRQNP		0x02 | 
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| 61 | #define  TOPIC97_ICR_IRQSEL		0x01 | 
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| 62 |  | 
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| 63 | #define TOPIC_CARD_DETECT		0x00a3	/* 8 bit */ | 
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| 64 | #define  TOPIC_CDR_MODE_PC32		0x80 | 
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| 65 | #define  TOPIC_CDR_VS1			0x04 | 
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| 66 | #define  TOPIC_CDR_VS2			0x02 | 
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| 67 | #define  TOPIC_CDR_SW_DETECT		0x01 | 
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| 68 |  | 
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| 69 | #define TOPIC_REGISTER_CONTROL		0x00a4	/* 32 bit */ | 
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| 70 | #define  TOPIC_RCR_RESUME_RESET		0x80000000 | 
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| 71 | #define  TOPIC_RCR_REMOVE_RESET		0x40000000 | 
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| 72 | #define  TOPIC97_RCR_CLKRUN_ENA		0x20000000 | 
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| 73 | #define  TOPIC97_RCR_TESTMODE		0x10000000 | 
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| 74 | #define  TOPIC97_RCR_IOPLUP		0x08000000 | 
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| 75 | #define  TOPIC_RCR_BUFOFF_PWROFF	0x02000000 | 
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| 76 | #define  TOPIC_RCR_BUFOFF_SIGOFF	0x01000000 | 
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| 77 | #define  TOPIC97_RCR_CB_DEV_MASK	0x0000f800 | 
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| 78 | #define  TOPIC97_RCR_CB_DEV_SHIFT	11 | 
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| 79 | #define  TOPIC97_RCR_RI_DISABLE		0x00000004 | 
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| 80 | #define  TOPIC97_RCR_CAUDIO_OFF		0x00000002 | 
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| 81 | #define  TOPIC_RCR_CAUDIO_INVERT	0x00000001 | 
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| 82 |  | 
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| 83 | #define TOPIC97_MISC1			0x00ad  /* 8bit */ | 
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| 84 | #define  TOPIC97_MISC1_CLOCKRUN_ENABLE	0x80 | 
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| 85 | #define  TOPIC97_MISC1_CLOCKRUN_MODE	0x40 | 
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| 86 | #define  TOPIC97_MISC1_DETECT_REQ_ENA	0x10 | 
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| 87 | #define  TOPIC97_MISC1_SCK_CLEAR_DIS	0x04 | 
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| 88 | #define  TOPIC97_MISC1_R2_LOW_ENABLE	0x10 | 
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| 89 |  | 
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| 90 | #define TOPIC97_MISC2			0x00ae  /* 8 bit */ | 
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| 91 | #define  TOPIC97_MISC2_SPWRCLK_MASK	0x70 | 
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| 92 | #define  TOPIC97_MISC2_SPWRMOD		0x08 | 
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| 93 | #define  TOPIC97_MISC2_SPWR_ENABLE	0x04 | 
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| 94 | #define  TOPIC97_MISC2_ZV_MODE		0x02 | 
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| 95 | #define  TOPIC97_MISC2_ZV_ENABLE	0x01 | 
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| 96 |  | 
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| 97 | #define TOPIC97_ZOOM_VIDEO_CONTROL	0x009c  /* 8 bit */ | 
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| 98 | #define  TOPIC97_ZV_CONTROL_ENABLE	0x01 | 
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| 99 |  | 
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| 100 | #define TOPIC97_AUDIO_VIDEO_SWITCH	0x003c  /* 8 bit */ | 
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| 101 | #define  TOPIC97_AVS_AUDIO_CONTROL	0x02 | 
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| 102 | #define  TOPIC97_AVS_VIDEO_CONTROL	0x01 | 
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| 103 |  | 
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| 104 | #define TOPIC_EXCA_IF_CONTROL		0x3e	/* 8 bit */ | 
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| 105 | #define TOPIC_EXCA_IFC_33V_ENA		0x01 | 
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| 106 |  | 
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| 107 | #define TOPIC_PCI_CFG_PPBCN		0x3e	/* 16-bit */ | 
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| 108 | #define TOPIC_PCI_CFG_PPBCN_WBEN	0x0400 | 
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| 109 |  | 
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| 110 | static void topic97_zoom_video(struct pcmcia_socket *sock, int onoff) | 
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| 111 | { | 
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| 112 | struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket); | 
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| 113 | u8 reg_zv, reg; | 
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| 114 |  | 
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| 115 | reg_zv = config_readb(socket, TOPIC97_ZOOM_VIDEO_CONTROL); | 
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| 116 | if (onoff) { | 
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| 117 | reg_zv |= TOPIC97_ZV_CONTROL_ENABLE; | 
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| 118 | config_writeb(socket, TOPIC97_ZOOM_VIDEO_CONTROL, val: reg_zv); | 
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| 119 |  | 
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| 120 | reg = config_readb(socket, TOPIC97_AUDIO_VIDEO_SWITCH); | 
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| 121 | reg |= TOPIC97_AVS_AUDIO_CONTROL | TOPIC97_AVS_VIDEO_CONTROL; | 
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| 122 | config_writeb(socket, TOPIC97_AUDIO_VIDEO_SWITCH, val: reg); | 
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| 123 | } else { | 
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| 124 | reg_zv &= ~TOPIC97_ZV_CONTROL_ENABLE; | 
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| 125 | config_writeb(socket, TOPIC97_ZOOM_VIDEO_CONTROL, val: reg_zv); | 
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| 126 |  | 
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| 127 | reg = config_readb(socket, TOPIC97_AUDIO_VIDEO_SWITCH); | 
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| 128 | reg &= ~(TOPIC97_AVS_AUDIO_CONTROL | TOPIC97_AVS_VIDEO_CONTROL); | 
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| 129 | config_writeb(socket, TOPIC97_AUDIO_VIDEO_SWITCH, val: reg); | 
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| 130 | } | 
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| 131 | } | 
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| 132 |  | 
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| 133 | static int topic97_override(struct yenta_socket *socket) | 
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| 134 | { | 
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| 135 | /* ToPIC97/100 support ZV */ | 
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| 136 | socket->socket.zoom_video = topic97_zoom_video; | 
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| 137 | return 0; | 
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| 138 | } | 
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| 139 |  | 
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| 140 |  | 
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| 141 | static int topic95_override(struct yenta_socket *socket) | 
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| 142 | { | 
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| 143 | u8 fctrl; | 
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| 144 | u16 ppbcn; | 
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| 145 |  | 
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| 146 | /* enable 3.3V support for 16bit cards */ | 
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| 147 | fctrl = exca_readb(socket, TOPIC_EXCA_IF_CONTROL); | 
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| 148 | exca_writeb(socket, TOPIC_EXCA_IF_CONTROL, val: fctrl | TOPIC_EXCA_IFC_33V_ENA); | 
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| 149 |  | 
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| 150 | /* tell yenta to use exca registers to power 16bit cards */ | 
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| 151 | socket->flags |= YENTA_16BIT_POWER_EXCA | YENTA_16BIT_POWER_DF; | 
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| 152 |  | 
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| 153 | /* Disable write buffers to prevent lockups under load with numerous | 
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| 154 | Cardbus cards, observed on Tecra 500CDT and reported elsewhere on the | 
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| 155 | net.  This is not a power-on default according to the datasheet | 
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| 156 | but some BIOSes seem to set it. */ | 
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| 157 | if (pci_read_config_word(dev: socket->dev, TOPIC_PCI_CFG_PPBCN, val: &ppbcn) == 0 | 
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| 158 | && socket->dev->revision <= 7 | 
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| 159 | && (ppbcn & TOPIC_PCI_CFG_PPBCN_WBEN)) { | 
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| 160 | ppbcn &= ~TOPIC_PCI_CFG_PPBCN_WBEN; | 
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| 161 | pci_write_config_word(dev: socket->dev, TOPIC_PCI_CFG_PPBCN, val: ppbcn); | 
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| 162 | dev_info(&socket->dev->dev, "Disabled ToPIC95 Cardbus write buffers.\n"); | 
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| 163 | } | 
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| 164 |  | 
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| 165 | return 0; | 
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| 166 | } | 
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| 167 |  | 
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| 168 | #endif /* _LINUX_TOPIC_H */ | 
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| 169 |  | 
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