1/* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
2/*
3 * include/linux/serial_reg.h
4 *
5 * Copyright (C) 1992, 1994 by Theodore Ts'o.
6 *
7 * Redistribution of this file is permitted under the terms of the GNU
8 * Public License (GPL)
9 *
10 * These are the UART port assignments, expressed as offsets from the base
11 * register. These assignments should hold for any serial port based on
12 * a 8250, 16450, or 16550(A).
13 */
14
15#ifndef _LINUX_SERIAL_REG_H
16#define _LINUX_SERIAL_REG_H
17
18/*
19 * DLAB=0
20 */
21#define UART_RX 0 /* In: Receive buffer */
22#define UART_TX 0 /* Out: Transmit buffer */
23
24#define UART_IER 1 /* Out: Interrupt Enable Register */
25#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
26#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
27#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
28#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
29/*
30 * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1
31 */
32#define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
33
34#define UART_IIR 2 /* In: Interrupt ID Register */
35#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
36#define UART_IIR_ID 0x0e /* Mask for the interrupt ID */
37#define UART_IIR_MSI 0x00 /* Modem status interrupt */
38#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
39#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
40#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
41
42#define UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */
43
44#define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */
45#define UART_IIR_XOFF 0x10 /* OMAP XOFF/Special Character */
46#define UART_IIR_CTS_RTS_DSR 0x20 /* OMAP CTS/RTS/DSR Change */
47#define UART_IIR_64BYTE_FIFO 0x20 /* 16750 64 bytes FIFO */
48#define UART_IIR_FIFO_ENABLED 0xc0 /* FIFOs enabled / port type identification */
49#define UART_IIR_FIFO_ENABLED_8250 0x00 /* 8250: no FIFO */
50#define UART_IIR_FIFO_ENABLED_16550 0x80 /* 16550: (broken/unusable) FIFO */
51#define UART_IIR_FIFO_ENABLED_16550A 0xc0 /* 16550A: FIFO enabled */
52#define UART_IIR_FIFO_ENABLED_16750 0xe0 /* 16750: 64 bytes FIFO enabled */
53
54#define UART_FCR 2 /* Out: FIFO Control Register */
55#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
56#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
57#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
58#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
59/*
60 * Note: The FIFO trigger levels are chip specific:
61 * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
62 * PC16550D: 1 4 8 14 xx xx xx xx
63 * TI16C550A: 1 4 8 14 xx xx xx xx
64 * TI16C550C: 1 4 8 14 xx xx xx xx
65 * ST16C550: 1 4 8 14 xx xx xx xx
66 * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2
67 * NS16C552: 1 4 8 14 xx xx xx xx
68 * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654
69 * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750
70 * TI16C752: 8 16 56 60 8 16 32 56
71 * OX16C950: 16 32 112 120 16 32 64 112 PORT_16C950
72 * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA
73 */
74#define UART_FCR_R_TRIG_00 0x00
75#define UART_FCR_R_TRIG_01 0x40
76#define UART_FCR_R_TRIG_10 0x80
77#define UART_FCR_R_TRIG_11 0xc0
78#define UART_FCR_T_TRIG_00 0x00
79#define UART_FCR_T_TRIG_01 0x10
80#define UART_FCR_T_TRIG_10 0x20
81#define UART_FCR_T_TRIG_11 0x30
82
83#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
84#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
85#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
86#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
87#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
88/* 16650 definitions */
89#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
90#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
91#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
92#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
93#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
94#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
95#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
96#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
97#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750 and
98 some Freescale UARTs) */
99
100#define UART_FCR_R_TRIG_SHIFT 6
101#define UART_FCR_R_TRIG_BITS(x) \
102 (((x) & UART_FCR_TRIGGER_MASK) >> UART_FCR_R_TRIG_SHIFT)
103#define UART_FCR_R_TRIG_MAX_STATE 4
104
105#define UART_LCR 3 /* Out: Line Control Register */
106/*
107 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
108 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
109 */
110#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
111#define UART_LCR_SBC 0x40 /* Set break control */
112#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
113#define UART_LCR_EPAR 0x10 /* Even parity select */
114#define UART_LCR_PARITY 0x08 /* Parity Enable */
115#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */
116#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
117#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
118#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
119#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
120
121/*
122 * Access to some registers depends on register access / configuration
123 * mode.
124 */
125#define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */
126#define UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */
127
128#define UART_MCR 4 /* Out: Modem Control Register */
129#define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
130#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
131#define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
132#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
133#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
134#define UART_MCR_OUT2 0x08 /* Out2 complement */
135#define UART_MCR_OUT1 0x04 /* Out1 complement */
136#define UART_MCR_RTS 0x02 /* RTS complement */
137#define UART_MCR_DTR 0x01 /* DTR complement */
138
139#define UART_LSR 5 /* In: Line Status Register */
140#define UART_LSR_FIFOE 0x80 /* Fifo error */
141#define UART_LSR_TEMT 0x40 /* Transmitter empty */
142#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
143#define UART_LSR_BI 0x10 /* Break interrupt indicator */
144#define UART_LSR_FE 0x08 /* Frame error indicator */
145#define UART_LSR_PE 0x04 /* Parity error indicator */
146#define UART_LSR_OE 0x02 /* Overrun error indicator */
147#define UART_LSR_DR 0x01 /* Receiver data ready */
148#define UART_LSR_BRK_ERROR_BITS (UART_LSR_BI|UART_LSR_FE|UART_LSR_PE|UART_LSR_OE)
149
150#define UART_MSR 6 /* In: Modem Status Register */
151#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
152#define UART_MSR_RI 0x40 /* Ring Indicator */
153#define UART_MSR_DSR 0x20 /* Data Set Ready */
154#define UART_MSR_CTS 0x10 /* Clear to Send */
155#define UART_MSR_DDCD 0x08 /* Delta DCD */
156#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
157#define UART_MSR_DDSR 0x02 /* Delta DSR */
158#define UART_MSR_DCTS 0x01 /* Delta CTS */
159#define UART_MSR_ANY_DELTA (UART_MSR_DDCD|UART_MSR_TERI|UART_MSR_DDSR|UART_MSR_DCTS)
160
161#define UART_SCR 7 /* I/O: Scratch Register */
162
163/*
164 * DLAB=1
165 */
166#define UART_DLL 0 /* Out: Divisor Latch Low */
167#define UART_DLM 1 /* Out: Divisor Latch High */
168#define UART_DIV_MAX 0xFFFF /* Max divisor value */
169
170/*
171 * LCR=0xBF (or DLAB=1 for 16C660)
172 */
173#define UART_EFR 2 /* I/O: Extended Features Register */
174#define UART_XR_EFR 9 /* I/O: Extended Features Register (XR17D15x) */
175#define UART_EFR_CTS 0x80 /* CTS flow control */
176#define UART_EFR_RTS 0x40 /* RTS flow control */
177#define UART_EFR_SCD 0x20 /* Special character detect */
178#define UART_EFR_ECB 0x10 /* Enhanced control bit */
179/*
180 * the low four bits control software flow control
181 */
182
183/*
184 * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654
185 */
186#define UART_XON1 4 /* I/O: Xon character 1 */
187#define UART_XON2 5 /* I/O: Xon character 2 */
188#define UART_XOFF1 6 /* I/O: Xoff character 1 */
189#define UART_XOFF2 7 /* I/O: Xoff character 2 */
190
191/*
192 * EFR[4]=1 MCR[6]=1, TI16C752
193 */
194#define UART_TI752_TCR 6 /* I/O: transmission control register */
195#define UART_TI752_TLR 7 /* I/O: trigger level register */
196
197/*
198 * LCR=0xBF, XR16C85x
199 */
200#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
201 * In: Fifo count
202 * Out: Fifo custom trigger levels */
203/*
204 * These are the definitions for the Programmable Trigger Register
205 */
206#define UART_TRG_1 0x01
207#define UART_TRG_4 0x04
208#define UART_TRG_8 0x08
209#define UART_TRG_16 0x10
210#define UART_TRG_32 0x20
211#define UART_TRG_64 0x40
212#define UART_TRG_96 0x60
213#define UART_TRG_120 0x78
214#define UART_TRG_128 0x80
215
216#define UART_FCTR 1 /* Feature Control Register */
217#define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */
218#define UART_FCTR_RTS_4DELAY 0x01
219#define UART_FCTR_RTS_6DELAY 0x02
220#define UART_FCTR_RTS_8DELAY 0x03
221#define UART_FCTR_IRDA 0x04 /* IrDa data encode select */
222#define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
223#define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
224#define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
225#define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
226#define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */
227#define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */
228#define UART_FCTR_RX 0x00 /* Programmable trigger mode select */
229#define UART_FCTR_TX 0x80 /* Programmable trigger mode select */
230
231/*
232 * LCR=0xBF, FCTR[6]=1
233 */
234#define UART_EMSR 7 /* Extended Mode Select Register */
235#define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */
236#define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */
237
238/*
239 * The Intel XScale on-chip UARTs define these bits
240 */
241#define UART_IER_DMAE 0x80 /* DMA Requests Enable */
242#define UART_IER_UUE 0x40 /* UART Unit Enable */
243#define UART_IER_NRZE 0x20 /* NRZ coding Enable */
244#define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */
245
246#define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */
247
248#define UART_FCR_PXAR1 0x00 /* receive FIFO threshold = 1 */
249#define UART_FCR_PXAR8 0x40 /* receive FIFO threshold = 8 */
250#define UART_FCR_PXAR16 0x80 /* receive FIFO threshold = 16 */
251#define UART_FCR_PXAR32 0xc0 /* receive FIFO threshold = 32 */
252
253/*
254 * These register definitions are for the 16C950
255 */
256#define UART_ASR 0x01 /* Additional Status Register */
257#define UART_RFL 0x03 /* Receiver FIFO level */
258#define UART_TFL 0x04 /* Transmitter FIFO level */
259#define UART_ICR 0x05 /* Index Control Register */
260
261/* The 16950 ICR registers */
262#define UART_ACR 0x00 /* Additional Control Register */
263#define UART_CPR 0x01 /* Clock Prescalar Register */
264#define UART_TCR 0x02 /* Times Clock Register */
265#define UART_CKS 0x03 /* Clock Select Register */
266#define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */
267#define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */
268#define UART_FCL 0x06 /* Flow Control Level Lower */
269#define UART_FCH 0x07 /* Flow Control Level Higher */
270#define UART_ID1 0x08 /* ID #1 */
271#define UART_ID2 0x09 /* ID #2 */
272#define UART_ID3 0x0A /* ID #3 */
273#define UART_REV 0x0B /* Revision */
274#define UART_CSR 0x0C /* Channel Software Reset */
275#define UART_NMR 0x0D /* Nine-bit Mode Register */
276#define UART_CTR 0xFF
277
278/*
279 * The 16C950 Additional Control Register
280 */
281#define UART_ACR_RXDIS 0x01 /* Receiver disable */
282#define UART_ACR_TXDIS 0x02 /* Transmitter disable */
283#define UART_ACR_DSRFC 0x04 /* DSR Flow Control */
284#define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */
285#define UART_ACR_ICRRD 0x40 /* ICR Read enable */
286#define UART_ACR_ASREN 0x80 /* Additional status enable */
287
288
289
290/*
291 * These definitions are for the RSA-DV II/S card, from
292 *
293 * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
294 */
295
296#define UART_RSA_BASE (-8)
297
298#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */
299
300#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
301#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
302#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
303#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
304
305#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
306
307#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
308#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
309#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
310#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
311#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
312
313#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */
314
315#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
316#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
317#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
318#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
319#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
320#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
321#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
322#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */
323
324#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
325
326#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
327
328#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
329
330#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */
331
332/*
333 * The RSA DSV/II board has two fixed clock frequencies. One is the
334 * standard rate, and the other is 8 times faster.
335 */
336#define SERIAL_RSA_BAUD_BASE (921600)
337#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
338
339/* Extra registers for TI DA8xx/66AK2x */
340#define UART_DA830_PWREMU_MGMT 12
341
342/* PWREMU_MGMT register bits */
343#define UART_DA830_PWREMU_MGMT_FREE (1 << 0) /* Free-running mode */
344#define UART_DA830_PWREMU_MGMT_URRST (1 << 13) /* Receiver reset/enable */
345#define UART_DA830_PWREMU_MGMT_UTRST (1 << 14) /* Transmitter reset/enable */
346
347/*
348 * Extra serial register definitions for the internal UARTs
349 * in TI OMAP processors.
350 */
351#define OMAP1_UART1_BASE 0xfffb0000
352#define OMAP1_UART2_BASE 0xfffb0800
353#define OMAP1_UART3_BASE 0xfffb9800
354#define UART_OMAP_MDR1 0x08 /* Mode definition register */
355#define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */
356#define UART_OMAP_SCR 0x10 /* Supplementary control register */
357#define UART_OMAP_SSR 0x11 /* Supplementary status register */
358#define UART_OMAP_EBLR 0x12 /* BOF length register */
359#define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */
360#define UART_OMAP_MVER 0x14 /* Module version register */
361#define UART_OMAP_SYSC 0x15 /* System configuration register */
362#define UART_OMAP_SYSS 0x16 /* System status register */
363#define UART_OMAP_WER 0x17 /* Wake-up enable register */
364#define UART_OMAP_TX_LVL 0x1a /* TX FIFO level register */
365
366/*
367 * These are the definitions for the MDR1 register
368 */
369#define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */
370#define UART_OMAP_MDR1_SIR_MODE 0x01 /* SIR mode */
371#define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */
372#define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */
373#define UART_OMAP_MDR1_MIR_MODE 0x04 /* MIR mode */
374#define UART_OMAP_MDR1_FIR_MODE 0x05 /* FIR mode */
375#define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */
376#define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */
377
378/*
379 * These are definitions for the Altera ALTR_16550_F32/F64/F128
380 * Normalized from 0x100 to 0x40 because of shift by 2 (32 bit regs).
381 */
382#define UART_ALTR_AFR 0x40 /* Additional Features Register */
383#define UART_ALTR_EN_TXFIFO_LW 0x01 /* Enable the TX FIFO Low Watermark */
384#define UART_ALTR_TX_LOW 0x41 /* Tx FIFO Low Watermark */
385
386#endif /* _LINUX_SERIAL_REG_H */
387
388