1/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
2/*
3 * Copyright (c) Meta Platforms, Inc. and affiliates.
4 * All rights reserved.
5 *
6 * This source code is licensed under both the BSD-style license (found in the
7 * LICENSE file in the root directory of this source tree) and the GPLv2 (found
8 * in the COPYING file in the root directory of this source tree).
9 * You may select, at your option, one of the above-listed licenses.
10 */
11
12#ifndef ZSTD_COMMON_CPU_H
13#define ZSTD_COMMON_CPU_H
14
15/*
16 * Implementation taken from folly/CpuId.h
17 * https://github.com/facebook/folly/blob/master/folly/CpuId.h
18 */
19
20#include "mem.h"
21
22
23typedef struct {
24 U32 f1c;
25 U32 f1d;
26 U32 f7b;
27 U32 f7c;
28} ZSTD_cpuid_t;
29
30MEM_STATIC ZSTD_cpuid_t ZSTD_cpuid(void) {
31 U32 f1c = 0;
32 U32 f1d = 0;
33 U32 f7b = 0;
34 U32 f7c = 0;
35#if defined(__i386__) && defined(__PIC__) && !defined(__clang__) && defined(__GNUC__)
36 /* The following block like the normal cpuid branch below, but gcc
37 * reserves ebx for use of its pic register so we must specially
38 * handle the save and restore to avoid clobbering the register
39 */
40 U32 n;
41 __asm__(
42 "pushl %%ebx\n\t"
43 "cpuid\n\t"
44 "popl %%ebx\n\t"
45 : "=a"(n)
46 : "a"(0)
47 : "ecx", "edx");
48 if (n >= 1) {
49 U32 f1a;
50 __asm__(
51 "pushl %%ebx\n\t"
52 "cpuid\n\t"
53 "popl %%ebx\n\t"
54 : "=a"(f1a), "=c"(f1c), "=d"(f1d)
55 : "a"(1));
56 }
57 if (n >= 7) {
58 __asm__(
59 "pushl %%ebx\n\t"
60 "cpuid\n\t"
61 "movl %%ebx, %%eax\n\t"
62 "popl %%ebx"
63 : "=a"(f7b), "=c"(f7c)
64 : "a"(7), "c"(0)
65 : "edx");
66 }
67#elif defined(__x86_64__) || defined(_M_X64) || defined(__i386__)
68 U32 n;
69 __asm__("cpuid" : "=a"(n) : "a"(0) : "ebx", "ecx", "edx");
70 if (n >= 1) {
71 U32 f1a;
72 __asm__("cpuid" : "=a"(f1a), "=c"(f1c), "=d"(f1d) : "a"(1) : "ebx");
73 }
74 if (n >= 7) {
75 U32 f7a;
76 __asm__("cpuid"
77 : "=a"(f7a), "=b"(f7b), "=c"(f7c)
78 : "a"(7), "c"(0)
79 : "edx");
80 }
81#endif
82 {
83 ZSTD_cpuid_t cpuid;
84 cpuid.f1c = f1c;
85 cpuid.f1d = f1d;
86 cpuid.f7b = f7b;
87 cpuid.f7c = f7c;
88 return cpuid;
89 }
90}
91
92#define X(name, r, bit) \
93 MEM_STATIC int ZSTD_cpuid_##name(ZSTD_cpuid_t const cpuid) { \
94 return ((cpuid.r) & (1U << bit)) != 0; \
95 }
96
97/* cpuid(1): Processor Info and Feature Bits. */
98#define C(name, bit) X(name, f1c, bit)
99 C(sse3, 0)
100 C(pclmuldq, 1)
101 C(dtes64, 2)
102 C(monitor, 3)
103 C(dscpl, 4)
104 C(vmx, 5)
105 C(smx, 6)
106 C(eist, 7)
107 C(tm2, 8)
108 C(ssse3, 9)
109 C(cnxtid, 10)
110 C(fma, 12)
111 C(cx16, 13)
112 C(xtpr, 14)
113 C(pdcm, 15)
114 C(pcid, 17)
115 C(dca, 18)
116 C(sse41, 19)
117 C(sse42, 20)
118 C(x2apic, 21)
119 C(movbe, 22)
120 C(popcnt, 23)
121 C(tscdeadline, 24)
122 C(aes, 25)
123 C(xsave, 26)
124 C(osxsave, 27)
125 C(avx, 28)
126 C(f16c, 29)
127 C(rdrand, 30)
128#undef C
129#define D(name, bit) X(name, f1d, bit)
130 D(fpu, 0)
131 D(vme, 1)
132 D(de, 2)
133 D(pse, 3)
134 D(tsc, 4)
135 D(msr, 5)
136 D(pae, 6)
137 D(mce, 7)
138 D(cx8, 8)
139 D(apic, 9)
140 D(sep, 11)
141 D(mtrr, 12)
142 D(pge, 13)
143 D(mca, 14)
144 D(cmov, 15)
145 D(pat, 16)
146 D(pse36, 17)
147 D(psn, 18)
148 D(clfsh, 19)
149 D(ds, 21)
150 D(acpi, 22)
151 D(mmx, 23)
152 D(fxsr, 24)
153 D(sse, 25)
154 D(sse2, 26)
155 D(ss, 27)
156 D(htt, 28)
157 D(tm, 29)
158 D(pbe, 31)
159#undef D
160
161/* cpuid(7): Extended Features. */
162#define B(name, bit) X(name, f7b, bit)
163 B(bmi1, 3)
164 B(hle, 4)
165 B(avx2, 5)
166 B(smep, 7)
167 B(bmi2, 8)
168 B(erms, 9)
169 B(invpcid, 10)
170 B(rtm, 11)
171 B(mpx, 14)
172 B(avx512f, 16)
173 B(avx512dq, 17)
174 B(rdseed, 18)
175 B(adx, 19)
176 B(smap, 20)
177 B(avx512ifma, 21)
178 B(pcommit, 22)
179 B(clflushopt, 23)
180 B(clwb, 24)
181 B(avx512pf, 26)
182 B(avx512er, 27)
183 B(avx512cd, 28)
184 B(sha, 29)
185 B(avx512bw, 30)
186 B(avx512vl, 31)
187#undef B
188#define C(name, bit) X(name, f7c, bit)
189 C(prefetchwt1, 0)
190 C(avx512vbmi, 1)
191#undef C
192
193#undef X
194
195#endif /* ZSTD_COMMON_CPU_H */
196