1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __SVM_H
3#define __SVM_H
4
5#include <uapi/asm/svm.h>
6#include <uapi/asm/kvm.h>
7
8#include <hyperv/hvhdk.h>
9
10/*
11 * 32-bit intercept words in the VMCB Control Area, starting
12 * at Byte offset 000h.
13 */
14
15enum intercept_words {
16 INTERCEPT_CR = 0,
17 INTERCEPT_DR,
18 INTERCEPT_EXCEPTION,
19 INTERCEPT_WORD3,
20 INTERCEPT_WORD4,
21 INTERCEPT_WORD5,
22 MAX_INTERCEPT,
23};
24
25enum {
26 /* Byte offset 000h (word 0) */
27 INTERCEPT_CR0_READ = 0,
28 INTERCEPT_CR3_READ = 3,
29 INTERCEPT_CR4_READ = 4,
30 INTERCEPT_CR8_READ = 8,
31 INTERCEPT_CR0_WRITE = 16,
32 INTERCEPT_CR3_WRITE = 16 + 3,
33 INTERCEPT_CR4_WRITE = 16 + 4,
34 INTERCEPT_CR8_WRITE = 16 + 8,
35 /* Byte offset 004h (word 1) */
36 INTERCEPT_DR0_READ = 32,
37 INTERCEPT_DR1_READ,
38 INTERCEPT_DR2_READ,
39 INTERCEPT_DR3_READ,
40 INTERCEPT_DR4_READ,
41 INTERCEPT_DR5_READ,
42 INTERCEPT_DR6_READ,
43 INTERCEPT_DR7_READ,
44 INTERCEPT_DR0_WRITE = 48,
45 INTERCEPT_DR1_WRITE,
46 INTERCEPT_DR2_WRITE,
47 INTERCEPT_DR3_WRITE,
48 INTERCEPT_DR4_WRITE,
49 INTERCEPT_DR5_WRITE,
50 INTERCEPT_DR6_WRITE,
51 INTERCEPT_DR7_WRITE,
52 /* Byte offset 008h (word 2) */
53 INTERCEPT_EXCEPTION_OFFSET = 64,
54 /* Byte offset 00Ch (word 3) */
55 INTERCEPT_INTR = 96,
56 INTERCEPT_NMI,
57 INTERCEPT_SMI,
58 INTERCEPT_INIT,
59 INTERCEPT_VINTR,
60 INTERCEPT_SELECTIVE_CR0,
61 INTERCEPT_STORE_IDTR,
62 INTERCEPT_STORE_GDTR,
63 INTERCEPT_STORE_LDTR,
64 INTERCEPT_STORE_TR,
65 INTERCEPT_LOAD_IDTR,
66 INTERCEPT_LOAD_GDTR,
67 INTERCEPT_LOAD_LDTR,
68 INTERCEPT_LOAD_TR,
69 INTERCEPT_RDTSC,
70 INTERCEPT_RDPMC,
71 INTERCEPT_PUSHF,
72 INTERCEPT_POPF,
73 INTERCEPT_CPUID,
74 INTERCEPT_RSM,
75 INTERCEPT_IRET,
76 INTERCEPT_INTn,
77 INTERCEPT_INVD,
78 INTERCEPT_PAUSE,
79 INTERCEPT_HLT,
80 INTERCEPT_INVLPG,
81 INTERCEPT_INVLPGA,
82 INTERCEPT_IOIO_PROT,
83 INTERCEPT_MSR_PROT,
84 INTERCEPT_TASK_SWITCH,
85 INTERCEPT_FERR_FREEZE,
86 INTERCEPT_SHUTDOWN,
87 /* Byte offset 010h (word 4) */
88 INTERCEPT_VMRUN = 128,
89 INTERCEPT_VMMCALL,
90 INTERCEPT_VMLOAD,
91 INTERCEPT_VMSAVE,
92 INTERCEPT_STGI,
93 INTERCEPT_CLGI,
94 INTERCEPT_SKINIT,
95 INTERCEPT_RDTSCP,
96 INTERCEPT_ICEBP,
97 INTERCEPT_WBINVD,
98 INTERCEPT_MONITOR,
99 INTERCEPT_MWAIT,
100 INTERCEPT_MWAIT_COND,
101 INTERCEPT_XSETBV,
102 INTERCEPT_RDPRU,
103 TRAP_EFER_WRITE,
104 TRAP_CR0_WRITE,
105 TRAP_CR1_WRITE,
106 TRAP_CR2_WRITE,
107 TRAP_CR3_WRITE,
108 TRAP_CR4_WRITE,
109 TRAP_CR5_WRITE,
110 TRAP_CR6_WRITE,
111 TRAP_CR7_WRITE,
112 TRAP_CR8_WRITE,
113 /* Byte offset 014h (word 5) */
114 INTERCEPT_INVLPGB = 160,
115 INTERCEPT_INVLPGB_ILLEGAL,
116 INTERCEPT_INVPCID,
117 INTERCEPT_MCOMMIT,
118 INTERCEPT_TLBSYNC,
119 INTERCEPT_BUSLOCK,
120 INTERCEPT_IDLE_HLT = 166,
121};
122
123
124struct __attribute__ ((__packed__)) vmcb_control_area {
125 u32 intercepts[MAX_INTERCEPT];
126 u32 reserved_1[15 - MAX_INTERCEPT];
127 u16 pause_filter_thresh;
128 u16 pause_filter_count;
129 u64 iopm_base_pa;
130 u64 msrpm_base_pa;
131 u64 tsc_offset;
132 u32 asid;
133 u8 tlb_ctl;
134 u8 reserved_2[3];
135 u32 int_ctl;
136 u32 int_vector;
137 u32 int_state;
138 u8 reserved_3[4];
139 u32 exit_code;
140 u32 exit_code_hi;
141 u64 exit_info_1;
142 u64 exit_info_2;
143 u32 exit_int_info;
144 u32 exit_int_info_err;
145 u64 nested_ctl;
146 u64 avic_vapic_bar;
147 u64 ghcb_gpa;
148 u32 event_inj;
149 u32 event_inj_err;
150 u64 nested_cr3;
151 u64 virt_ext;
152 u32 clean;
153 u32 reserved_5;
154 u64 next_rip;
155 u8 insn_len;
156 u8 insn_bytes[15];
157 u64 avic_backing_page; /* Offset 0xe0 */
158 u8 reserved_6[8]; /* Offset 0xe8 */
159 u64 avic_logical_id; /* Offset 0xf0 */
160 u64 avic_physical_id; /* Offset 0xf8 */
161 u8 reserved_7[8];
162 u64 vmsa_pa; /* Used for an SEV-ES guest */
163 u8 reserved_8[16];
164 u16 bus_lock_counter; /* Offset 0x120 */
165 u8 reserved_9[22];
166 u64 allowed_sev_features; /* Offset 0x138 */
167 u64 guest_sev_features; /* Offset 0x140 */
168 u8 reserved_10[664];
169 /*
170 * Offset 0x3e0, 32 bytes reserved
171 * for use by hypervisor/software.
172 */
173 union {
174 struct hv_vmcb_enlightenments hv_enlightenments;
175 u8 reserved_sw[32];
176 };
177};
178
179
180#define TLB_CONTROL_DO_NOTHING 0
181#define TLB_CONTROL_FLUSH_ALL_ASID 1
182#define TLB_CONTROL_FLUSH_ASID 3
183#define TLB_CONTROL_FLUSH_ASID_LOCAL 7
184
185#define V_TPR_MASK 0x0f
186
187#define V_IRQ_SHIFT 8
188#define V_IRQ_MASK (1 << V_IRQ_SHIFT)
189
190#define V_GIF_SHIFT 9
191#define V_GIF_MASK (1 << V_GIF_SHIFT)
192
193#define V_NMI_PENDING_SHIFT 11
194#define V_NMI_PENDING_MASK (1 << V_NMI_PENDING_SHIFT)
195
196#define V_NMI_BLOCKING_SHIFT 12
197#define V_NMI_BLOCKING_MASK (1 << V_NMI_BLOCKING_SHIFT)
198
199#define V_INTR_PRIO_SHIFT 16
200#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
201
202#define V_IGN_TPR_SHIFT 20
203#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
204
205#define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK)
206
207#define V_INTR_MASKING_SHIFT 24
208#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
209
210#define V_GIF_ENABLE_SHIFT 25
211#define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
212
213#define V_NMI_ENABLE_SHIFT 26
214#define V_NMI_ENABLE_MASK (1 << V_NMI_ENABLE_SHIFT)
215
216#define AVIC_ENABLE_SHIFT 31
217#define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
218
219#define X2APIC_MODE_SHIFT 30
220#define X2APIC_MODE_MASK (1 << X2APIC_MODE_SHIFT)
221
222#define LBR_CTL_ENABLE_MASK BIT_ULL(0)
223#define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
224
225#define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0)
226#define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1)
227
228#define SVM_IOIO_STR_SHIFT 2
229#define SVM_IOIO_REP_SHIFT 3
230#define SVM_IOIO_SIZE_SHIFT 4
231#define SVM_IOIO_ASIZE_SHIFT 7
232
233#define SVM_IOIO_TYPE_MASK 1
234#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
235#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
236#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
237#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
238
239#define SVM_NESTED_CTL_NP_ENABLE BIT(0)
240#define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
241#define SVM_NESTED_CTL_SEV_ES_ENABLE BIT(2)
242
243
244#define SVM_TSC_RATIO_RSVD 0xffffff0000000000ULL
245#define SVM_TSC_RATIO_MIN 0x0000000000000001ULL
246#define SVM_TSC_RATIO_MAX 0x000000ffffffffffULL
247#define SVM_TSC_RATIO_DEFAULT 0x0100000000ULL
248
249
250/* AVIC */
251#define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFFULL)
252#define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
253#define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
254
255/*
256 * GA_LOG_INTR is a synthetic flag that's never propagated to hardware-visible
257 * tables. GA_LOG_INTR is set if the vCPU needs device posted IRQs to generate
258 * GA log interrupts to wake the vCPU (because it's blocking or about to block).
259 */
260#define AVIC_PHYSICAL_ID_ENTRY_GA_LOG_INTR BIT_ULL(61)
261
262#define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)
263#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK GENMASK_ULL(51, 12)
264#define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
265#define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
266#define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK (0xFFULL)
267
268#define AVIC_DOORBELL_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)
269
270#define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
271#define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
272#define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
273
274enum avic_ipi_failure_cause {
275 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
276 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
277 AVIC_IPI_FAILURE_INVALID_TARGET,
278 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
279 AVIC_IPI_FAILURE_INVALID_IPI_VECTOR,
280};
281
282#define AVIC_PHYSICAL_MAX_INDEX_MASK GENMASK_ULL(8, 0)
283
284/*
285 * For AVIC, the max index allowed for physical APIC ID table is 0xfe (254), as
286 * 0xff is a broadcast to all CPUs, i.e. can't be targeted individually.
287 */
288#define AVIC_MAX_PHYSICAL_ID 0XFEULL
289
290/*
291 * For x2AVIC, the max index allowed for physical APIC ID table is 0x1ff (511).
292 */
293#define X2AVIC_MAX_PHYSICAL_ID 0x1FFUL
294
295static_assert((AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == AVIC_MAX_PHYSICAL_ID);
296static_assert((X2AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == X2AVIC_MAX_PHYSICAL_ID);
297
298#define SVM_SEV_FEAT_SNP_ACTIVE BIT(0)
299#define SVM_SEV_FEAT_RESTRICTED_INJECTION BIT(3)
300#define SVM_SEV_FEAT_ALTERNATE_INJECTION BIT(4)
301#define SVM_SEV_FEAT_DEBUG_SWAP BIT(5)
302#define SVM_SEV_FEAT_SECURE_TSC BIT(9)
303
304#define VMCB_ALLOWED_SEV_FEATURES_VALID BIT_ULL(63)
305
306struct vmcb_seg {
307 u16 selector;
308 u16 attrib;
309 u32 limit;
310 u64 base;
311} __packed;
312
313/* Save area definition for legacy and SEV-MEM guests */
314struct vmcb_save_area {
315 struct vmcb_seg es;
316 struct vmcb_seg cs;
317 struct vmcb_seg ss;
318 struct vmcb_seg ds;
319 struct vmcb_seg fs;
320 struct vmcb_seg gs;
321 struct vmcb_seg gdtr;
322 struct vmcb_seg ldtr;
323 struct vmcb_seg idtr;
324 struct vmcb_seg tr;
325 /* Reserved fields are named following their struct offset */
326 u8 reserved_0xa0[42];
327 u8 vmpl;
328 u8 cpl;
329 u8 reserved_0xcc[4];
330 u64 efer;
331 u8 reserved_0xd8[112];
332 u64 cr4;
333 u64 cr3;
334 u64 cr0;
335 u64 dr7;
336 u64 dr6;
337 u64 rflags;
338 u64 rip;
339 u8 reserved_0x180[88];
340 u64 rsp;
341 u64 s_cet;
342 u64 ssp;
343 u64 isst_addr;
344 u64 rax;
345 u64 star;
346 u64 lstar;
347 u64 cstar;
348 u64 sfmask;
349 u64 kernel_gs_base;
350 u64 sysenter_cs;
351 u64 sysenter_esp;
352 u64 sysenter_eip;
353 u64 cr2;
354 u8 reserved_0x248[32];
355 u64 g_pat;
356 u64 dbgctl;
357 u64 br_from;
358 u64 br_to;
359 u64 last_excp_from;
360 u64 last_excp_to;
361 u8 reserved_0x298[72];
362 u64 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */
363} __packed;
364
365/* Save area definition for SEV-ES and SEV-SNP guests */
366struct sev_es_save_area {
367 struct vmcb_seg es;
368 struct vmcb_seg cs;
369 struct vmcb_seg ss;
370 struct vmcb_seg ds;
371 struct vmcb_seg fs;
372 struct vmcb_seg gs;
373 struct vmcb_seg gdtr;
374 struct vmcb_seg ldtr;
375 struct vmcb_seg idtr;
376 struct vmcb_seg tr;
377 u64 pl0_ssp;
378 u64 pl1_ssp;
379 u64 pl2_ssp;
380 u64 pl3_ssp;
381 u64 u_cet;
382 u8 reserved_0xc8[2];
383 u8 vmpl;
384 u8 cpl;
385 u8 reserved_0xcc[4];
386 u64 efer;
387 u8 reserved_0xd8[104];
388 u64 xss;
389 u64 cr4;
390 u64 cr3;
391 u64 cr0;
392 u64 dr7;
393 u64 dr6;
394 u64 rflags;
395 u64 rip;
396 u64 dr0;
397 u64 dr1;
398 u64 dr2;
399 u64 dr3;
400 u64 dr0_addr_mask;
401 u64 dr1_addr_mask;
402 u64 dr2_addr_mask;
403 u64 dr3_addr_mask;
404 u8 reserved_0x1c0[24];
405 u64 rsp;
406 u64 s_cet;
407 u64 ssp;
408 u64 isst_addr;
409 u64 rax;
410 u64 star;
411 u64 lstar;
412 u64 cstar;
413 u64 sfmask;
414 u64 kernel_gs_base;
415 u64 sysenter_cs;
416 u64 sysenter_esp;
417 u64 sysenter_eip;
418 u64 cr2;
419 u8 reserved_0x248[32];
420 u64 g_pat;
421 u64 dbgctl;
422 u64 br_from;
423 u64 br_to;
424 u64 last_excp_from;
425 u64 last_excp_to;
426 u8 reserved_0x298[80];
427 u32 pkru;
428 u32 tsc_aux;
429 u64 tsc_scale;
430 u64 tsc_offset;
431 u8 reserved_0x300[8];
432 u64 rcx;
433 u64 rdx;
434 u64 rbx;
435 u64 reserved_0x320; /* rsp already available at 0x01d8 */
436 u64 rbp;
437 u64 rsi;
438 u64 rdi;
439 u64 r8;
440 u64 r9;
441 u64 r10;
442 u64 r11;
443 u64 r12;
444 u64 r13;
445 u64 r14;
446 u64 r15;
447 u8 reserved_0x380[16];
448 u64 guest_exit_info_1;
449 u64 guest_exit_info_2;
450 u64 guest_exit_int_info;
451 u64 guest_nrip;
452 u64 sev_features;
453 u64 vintr_ctrl;
454 u64 guest_exit_code;
455 u64 virtual_tom;
456 u64 tlb_id;
457 u64 pcpu_id;
458 u64 event_inj;
459 u64 xcr0;
460 u8 reserved_0x3f0[16];
461
462 /* Floating point area */
463 u64 x87_dp;
464 u32 mxcsr;
465 u16 x87_ftw;
466 u16 x87_fsw;
467 u16 x87_fcw;
468 u16 x87_fop;
469 u16 x87_ds;
470 u16 x87_cs;
471 u64 x87_rip;
472 u8 fpreg_x87[80];
473 u8 fpreg_xmm[256];
474 u8 fpreg_ymm[256];
475} __packed;
476
477struct ghcb_save_area {
478 u8 reserved_0x0[203];
479 u8 cpl;
480 u8 reserved_0xcc[116];
481 u64 xss;
482 u8 reserved_0x148[24];
483 u64 dr7;
484 u8 reserved_0x168[16];
485 u64 rip;
486 u8 reserved_0x180[88];
487 u64 rsp;
488 u8 reserved_0x1e0[24];
489 u64 rax;
490 u8 reserved_0x200[264];
491 u64 rcx;
492 u64 rdx;
493 u64 rbx;
494 u8 reserved_0x320[8];
495 u64 rbp;
496 u64 rsi;
497 u64 rdi;
498 u64 r8;
499 u64 r9;
500 u64 r10;
501 u64 r11;
502 u64 r12;
503 u64 r13;
504 u64 r14;
505 u64 r15;
506 u8 reserved_0x380[16];
507 u64 sw_exit_code;
508 u64 sw_exit_info_1;
509 u64 sw_exit_info_2;
510 u64 sw_scratch;
511 u8 reserved_0x3b0[56];
512 u64 xcr0;
513 u8 valid_bitmap[16];
514 u64 x87_state_gpa;
515} __packed;
516
517#define GHCB_SHARED_BUF_SIZE 2032
518
519struct ghcb {
520 struct ghcb_save_area save;
521 u8 reserved_save[2048 - sizeof(struct ghcb_save_area)];
522
523 u8 shared_buffer[GHCB_SHARED_BUF_SIZE];
524
525 u8 reserved_0xff0[10];
526 u16 protocol_version; /* negotiated SEV-ES/GHCB protocol version */
527 u32 ghcb_usage;
528} __packed;
529
530struct vmcb {
531 struct vmcb_control_area control;
532 union {
533 struct vmcb_save_area save;
534
535 /*
536 * For SEV-ES VMs, the save area in the VMCB is used only to
537 * save/load host state. Guest state resides in a separate
538 * page, the aptly named VM Save Area (VMSA), that is encrypted
539 * with the guest's private key.
540 */
541 struct sev_es_save_area host_sev_es_save;
542 };
543} __packed;
544
545#define EXPECTED_VMCB_SAVE_AREA_SIZE 744
546#define EXPECTED_GHCB_SAVE_AREA_SIZE 1032
547#define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1648
548#define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024
549#define EXPECTED_GHCB_SIZE PAGE_SIZE
550
551#define BUILD_BUG_RESERVED_OFFSET(x, y) \
552 ASSERT_STRUCT_OFFSET(struct x, reserved ## _ ## y, y)
553
554static inline void __unused_size_checks(void)
555{
556 BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE);
557 BUILD_BUG_ON(sizeof(struct ghcb_save_area) != EXPECTED_GHCB_SAVE_AREA_SIZE);
558 BUILD_BUG_ON(sizeof(struct sev_es_save_area) != EXPECTED_SEV_ES_SAVE_AREA_SIZE);
559 BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE);
560 BUILD_BUG_ON(offsetof(struct vmcb, save) != EXPECTED_VMCB_CONTROL_AREA_SIZE);
561 BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE);
562
563 /* Check offsets of reserved fields */
564
565 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xa0);
566 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xcc);
567 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xd8);
568 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x180);
569 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x248);
570 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x298);
571
572 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xc8);
573 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xcc);
574 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xd8);
575 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x1c0);
576 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x248);
577 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x298);
578 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x300);
579 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x320);
580 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x380);
581 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x3f0);
582
583 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x0);
584 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0xcc);
585 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x148);
586 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x168);
587 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x180);
588 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x1e0);
589 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x200);
590 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x320);
591 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x380);
592 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x3b0);
593
594 BUILD_BUG_RESERVED_OFFSET(ghcb, 0xff0);
595}
596
597#define SVM_CPUID_FUNC 0x8000000a
598
599#define SVM_SELECTOR_S_SHIFT 4
600#define SVM_SELECTOR_DPL_SHIFT 5
601#define SVM_SELECTOR_P_SHIFT 7
602#define SVM_SELECTOR_AVL_SHIFT 8
603#define SVM_SELECTOR_L_SHIFT 9
604#define SVM_SELECTOR_DB_SHIFT 10
605#define SVM_SELECTOR_G_SHIFT 11
606
607#define SVM_SELECTOR_TYPE_MASK (0xf)
608#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
609#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
610#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
611#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
612#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
613#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
614#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
615
616#define SVM_SELECTOR_WRITE_MASK (1 << 1)
617#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
618#define SVM_SELECTOR_CODE_MASK (1 << 3)
619
620#define SVM_EVTINJ_VEC_MASK 0xff
621
622#define SVM_EVTINJ_TYPE_SHIFT 8
623#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
624
625#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
626#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
627#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
628#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
629
630#define SVM_EVTINJ_VALID (1 << 31)
631#define SVM_EVTINJ_VALID_ERR (1 << 11)
632
633#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
634#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
635
636#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
637#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
638#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
639#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
640
641#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
642#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
643
644#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
645#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
646#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
647
648#define SVM_EXITINFO_REG_MASK 0x0F
649
650#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
651
652/* GHCB Accessor functions */
653
654#define GHCB_BITMAP_IDX(field) \
655 (offsetof(struct ghcb_save_area, field) / sizeof(u64))
656
657#define DEFINE_GHCB_ACCESSORS(field) \
658 static __always_inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \
659 { \
660 return test_bit(GHCB_BITMAP_IDX(field), \
661 (unsigned long *)&ghcb->save.valid_bitmap); \
662 } \
663 \
664 static __always_inline u64 ghcb_get_##field(struct ghcb *ghcb) \
665 { \
666 return ghcb->save.field; \
667 } \
668 \
669 static __always_inline u64 ghcb_get_##field##_if_valid(struct ghcb *ghcb) \
670 { \
671 return ghcb_##field##_is_valid(ghcb) ? ghcb->save.field : 0; \
672 } \
673 \
674 static __always_inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \
675 { \
676 __set_bit(GHCB_BITMAP_IDX(field), \
677 (unsigned long *)&ghcb->save.valid_bitmap); \
678 ghcb->save.field = value; \
679 }
680
681DEFINE_GHCB_ACCESSORS(cpl)
682DEFINE_GHCB_ACCESSORS(rip)
683DEFINE_GHCB_ACCESSORS(rsp)
684DEFINE_GHCB_ACCESSORS(rax)
685DEFINE_GHCB_ACCESSORS(rcx)
686DEFINE_GHCB_ACCESSORS(rdx)
687DEFINE_GHCB_ACCESSORS(rbx)
688DEFINE_GHCB_ACCESSORS(rbp)
689DEFINE_GHCB_ACCESSORS(rsi)
690DEFINE_GHCB_ACCESSORS(rdi)
691DEFINE_GHCB_ACCESSORS(r8)
692DEFINE_GHCB_ACCESSORS(r9)
693DEFINE_GHCB_ACCESSORS(r10)
694DEFINE_GHCB_ACCESSORS(r11)
695DEFINE_GHCB_ACCESSORS(r12)
696DEFINE_GHCB_ACCESSORS(r13)
697DEFINE_GHCB_ACCESSORS(r14)
698DEFINE_GHCB_ACCESSORS(r15)
699DEFINE_GHCB_ACCESSORS(sw_exit_code)
700DEFINE_GHCB_ACCESSORS(sw_exit_info_1)
701DEFINE_GHCB_ACCESSORS(sw_exit_info_2)
702DEFINE_GHCB_ACCESSORS(sw_scratch)
703DEFINE_GHCB_ACCESSORS(xcr0)
704
705#endif
706