1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong
4 * because MTRRs can span up to 40 bits (36bits on most modern x86)
5 */
6
7#include <linux/export.h>
8#include <linux/init.h>
9#include <linux/io.h>
10#include <linux/mm.h>
11#include <linux/cc_platform.h>
12#include <linux/string_choices.h>
13#include <asm/processor-flags.h>
14#include <asm/cacheinfo.h>
15#include <asm/cpufeature.h>
16#include <asm/cpu_device_id.h>
17#include <asm/hypervisor.h>
18#include <asm/mshyperv.h>
19#include <asm/tlbflush.h>
20#include <asm/mtrr.h>
21#include <asm/msr.h>
22#include <asm/memtype.h>
23
24#include "mtrr.h"
25
26struct fixed_range_block {
27 int base_msr; /* start address of an MTRR block */
28 int ranges; /* number of MTRRs in this block */
29};
30
31static struct fixed_range_block fixed_range_blocks[] = {
32 { MSR_MTRRfix64K_00000, 1 }, /* one 64k MTRR */
33 { MSR_MTRRfix16K_80000, .ranges: 2 }, /* two 16k MTRRs */
34 { MSR_MTRRfix4K_C0000, .ranges: 8 }, /* eight 4k MTRRs */
35 {}
36};
37
38struct cache_map {
39 u64 start;
40 u64 end;
41 u64 flags;
42 u64 type:8;
43 u64 fixed:1;
44};
45
46bool mtrr_debug;
47
48static int __init mtrr_param_setup(char *str)
49{
50 int rc = 0;
51
52 if (!str)
53 return -EINVAL;
54 if (!strcmp(str, "debug"))
55 mtrr_debug = true;
56 else
57 rc = -EINVAL;
58
59 return rc;
60}
61early_param("mtrr", mtrr_param_setup);
62
63/*
64 * CACHE_MAP_MAX is the maximum number of memory ranges in cache_map, where
65 * no 2 adjacent ranges have the same cache mode (those would be merged).
66 * The number is based on the worst case:
67 * - no two adjacent fixed MTRRs share the same cache mode
68 * - one variable MTRR is spanning a huge area with mode WB
69 * - 255 variable MTRRs with mode UC all overlap with the WB MTRR, creating 2
70 * additional ranges each (result like "ababababa...aba" with a = WB, b = UC),
71 * accounting for MTRR_MAX_VAR_RANGES * 2 - 1 range entries
72 * - a TOP_MEM2 area (even with overlapping an UC MTRR can't add 2 range entries
73 * to the possible maximum, as it always starts at 4GB, thus it can't be in
74 * the middle of that MTRR, unless that MTRR starts at 0, which would remove
75 * the initial "a" from the "abababa" pattern above)
76 * The map won't contain ranges with no matching MTRR (those fall back to the
77 * default cache mode).
78 */
79#define CACHE_MAP_MAX (MTRR_NUM_FIXED_RANGES + MTRR_MAX_VAR_RANGES * 2)
80
81static struct cache_map init_cache_map[CACHE_MAP_MAX] __initdata;
82static struct cache_map *cache_map __refdata = init_cache_map;
83static unsigned int cache_map_size = CACHE_MAP_MAX;
84static unsigned int cache_map_n;
85static unsigned int cache_map_fixed;
86
87static unsigned long smp_changes_mask;
88static int mtrr_state_set;
89u64 mtrr_tom2;
90
91struct mtrr_state_type mtrr_state;
92EXPORT_SYMBOL_GPL(mtrr_state);
93
94/* Reserved bits in the high portion of the MTRRphysBaseN MSR. */
95u32 phys_hi_rsvd;
96
97/*
98 * BIOS is expected to clear MtrrFixDramModEn bit, see for example
99 * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD
100 * Opteron Processors" (26094 Rev. 3.30 February 2006), section
101 * "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set
102 * to 1 during BIOS initialization of the fixed MTRRs, then cleared to
103 * 0 for operation."
104 */
105static inline void k8_check_syscfg_dram_mod_en(void)
106{
107 u32 lo, hi;
108
109 if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
110 (boot_cpu_data.x86 >= 0x0f)))
111 return;
112
113 if (cc_platform_has(attr: CC_ATTR_HOST_SEV_SNP))
114 return;
115
116 rdmsr(MSR_AMD64_SYSCFG, lo, hi);
117 if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) {
118 pr_err(FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]"
119 " not cleared by BIOS, clearing this bit\n",
120 smp_processor_id());
121 lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
122 mtrr_wrmsr(MSR_AMD64_SYSCFG, lo, hi);
123 }
124}
125
126/* Get the size of contiguous MTRR range */
127static u64 get_mtrr_size(u64 mask)
128{
129 u64 size;
130
131 mask |= (u64)phys_hi_rsvd << 32;
132 size = -mask;
133
134 return size;
135}
136
137static u8 get_var_mtrr_state(unsigned int reg, u64 *start, u64 *size)
138{
139 struct mtrr_var_range *mtrr = mtrr_state.var_ranges + reg;
140
141 if (!(mtrr->mask_lo & MTRR_PHYSMASK_V))
142 return MTRR_TYPE_INVALID;
143
144 *start = (((u64)mtrr->base_hi) << 32) + (mtrr->base_lo & PAGE_MASK);
145 *size = get_mtrr_size(mask: (((u64)mtrr->mask_hi) << 32) +
146 (mtrr->mask_lo & PAGE_MASK));
147
148 return mtrr->base_lo & MTRR_PHYSBASE_TYPE;
149}
150
151static u8 get_effective_type(u8 type1, u8 type2)
152{
153 if (type1 == MTRR_TYPE_UNCACHABLE || type2 == MTRR_TYPE_UNCACHABLE)
154 return MTRR_TYPE_UNCACHABLE;
155
156 if ((type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH) ||
157 (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK))
158 return MTRR_TYPE_WRTHROUGH;
159
160 if (type1 != type2)
161 return MTRR_TYPE_UNCACHABLE;
162
163 return type1;
164}
165
166static void rm_map_entry_at(int idx)
167{
168 cache_map_n--;
169 if (cache_map_n > idx) {
170 memmove(dest: cache_map + idx, src: cache_map + idx + 1,
171 count: sizeof(*cache_map) * (cache_map_n - idx));
172 }
173}
174
175/*
176 * Add an entry into cache_map at a specific index. Merges adjacent entries if
177 * appropriate. Return the number of merges for correcting the scan index
178 * (this is needed as merging will reduce the number of entries, which will
179 * result in skipping entries in future iterations if the scan index isn't
180 * corrected).
181 * Note that the corrected index can never go below -1 (resulting in being 0 in
182 * the next scan iteration), as "2" is returned only if the current index is
183 * larger than zero.
184 */
185static int add_map_entry_at(u64 start, u64 end, u8 type, int idx)
186{
187 bool merge_prev = false, merge_next = false;
188
189 if (start >= end)
190 return 0;
191
192 if (idx > 0) {
193 struct cache_map *prev = cache_map + idx - 1;
194
195 if (!prev->fixed && start == prev->end && type == prev->type)
196 merge_prev = true;
197 }
198
199 if (idx < cache_map_n) {
200 struct cache_map *next = cache_map + idx;
201
202 if (!next->fixed && end == next->start && type == next->type)
203 merge_next = true;
204 }
205
206 if (merge_prev && merge_next) {
207 cache_map[idx - 1].end = cache_map[idx].end;
208 rm_map_entry_at(idx);
209 return 2;
210 }
211 if (merge_prev) {
212 cache_map[idx - 1].end = end;
213 return 1;
214 }
215 if (merge_next) {
216 cache_map[idx].start = start;
217 return 1;
218 }
219
220 /* Sanity check: the array should NEVER be too small! */
221 if (cache_map_n == cache_map_size) {
222 WARN(1, "MTRR cache mode memory map exhausted!\n");
223 cache_map_n = cache_map_fixed;
224 return 0;
225 }
226
227 if (cache_map_n > idx) {
228 memmove(dest: cache_map + idx + 1, src: cache_map + idx,
229 count: sizeof(*cache_map) * (cache_map_n - idx));
230 }
231
232 cache_map[idx].start = start;
233 cache_map[idx].end = end;
234 cache_map[idx].type = type;
235 cache_map[idx].fixed = 0;
236 cache_map_n++;
237
238 return 0;
239}
240
241/* Clear a part of an entry. Return 1 if start of entry is still valid. */
242static int clr_map_range_at(u64 start, u64 end, int idx)
243{
244 int ret = start != cache_map[idx].start;
245 u64 tmp;
246
247 if (start == cache_map[idx].start && end == cache_map[idx].end) {
248 rm_map_entry_at(idx);
249 } else if (start == cache_map[idx].start) {
250 cache_map[idx].start = end;
251 } else if (end == cache_map[idx].end) {
252 cache_map[idx].end = start;
253 } else {
254 tmp = cache_map[idx].end;
255 cache_map[idx].end = start;
256 add_map_entry_at(start: end, end: tmp, type: cache_map[idx].type, idx: idx + 1);
257 }
258
259 return ret;
260}
261
262/*
263 * Add MTRR to the map. The current map is scanned and each part of the MTRR
264 * either overlapping with an existing entry or with a hole in the map is
265 * handled separately.
266 */
267static void add_map_entry(u64 start, u64 end, u8 type)
268{
269 u8 new_type, old_type;
270 u64 tmp;
271 int i;
272
273 for (i = 0; i < cache_map_n && start < end; i++) {
274 if (start >= cache_map[i].end)
275 continue;
276
277 if (start < cache_map[i].start) {
278 /* Region start has no overlap. */
279 tmp = min(end, cache_map[i].start);
280 i -= add_map_entry_at(start, end: tmp, type, idx: i);
281 start = tmp;
282 continue;
283 }
284
285 new_type = get_effective_type(type1: type, type2: cache_map[i].type);
286 old_type = cache_map[i].type;
287
288 if (cache_map[i].fixed || new_type == old_type) {
289 /* Cut off start of new entry. */
290 start = cache_map[i].end;
291 continue;
292 }
293
294 /* Handle only overlapping part of region. */
295 tmp = min(end, cache_map[i].end);
296 i += clr_map_range_at(start, end: tmp, idx: i);
297 i -= add_map_entry_at(start, end: tmp, type: new_type, idx: i);
298 start = tmp;
299 }
300
301 /* Add rest of region after last map entry (rest might be empty). */
302 add_map_entry_at(start, end, type, idx: i);
303}
304
305/* Add variable MTRRs to cache map. */
306static void map_add_var(void)
307{
308 u64 start, size;
309 unsigned int i;
310 u8 type;
311
312 /*
313 * Add AMD TOP_MEM2 area. Can't be added in mtrr_build_map(), as it
314 * needs to be added again when rebuilding the map due to potentially
315 * having moved as a result of variable MTRRs for memory below 4GB.
316 */
317 if (mtrr_tom2) {
318 add_map_entry(BIT_ULL(32), end: mtrr_tom2, MTRR_TYPE_WRBACK);
319 cache_map[cache_map_n - 1].fixed = 1;
320 }
321
322 for (i = 0; i < num_var_ranges; i++) {
323 type = get_var_mtrr_state(reg: i, start: &start, size: &size);
324 if (type != MTRR_TYPE_INVALID)
325 add_map_entry(start, end: start + size, type);
326 }
327}
328
329/*
330 * Rebuild map by replacing variable entries. Needs to be called when MTRR
331 * registers are being changed after boot, as such changes could include
332 * removals of registers, which are complicated to handle without rebuild of
333 * the map.
334 */
335void generic_rebuild_map(void)
336{
337 if (mtrr_if != &generic_mtrr_ops)
338 return;
339
340 cache_map_n = cache_map_fixed;
341
342 map_add_var();
343}
344
345static unsigned int __init get_cache_map_size(void)
346{
347 return cache_map_fixed + 2 * num_var_ranges + (mtrr_tom2 != 0);
348}
349
350/* Build the cache_map containing the cache modes per memory range. */
351void __init mtrr_build_map(void)
352{
353 u64 start, end, size;
354 unsigned int i;
355 u8 type;
356
357 /* Add fixed MTRRs, optimize for adjacent entries with same type. */
358 if (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED) {
359 /*
360 * Start with 64k size fixed entries, preset 1st one (hence the
361 * loop below is starting with index 1).
362 */
363 start = 0;
364 end = size = 0x10000;
365 type = mtrr_state.fixed_ranges[0];
366
367 for (i = 1; i < MTRR_NUM_FIXED_RANGES; i++) {
368 /* 8 64k entries, then 16 16k ones, rest 4k. */
369 if (i == 8 || i == 24)
370 size >>= 2;
371
372 if (mtrr_state.fixed_ranges[i] != type) {
373 add_map_entry(start, end, type);
374 start = end;
375 type = mtrr_state.fixed_ranges[i];
376 }
377 end += size;
378 }
379 add_map_entry(start, end, type);
380 }
381
382 /* Mark fixed, they take precedence. */
383 for (i = 0; i < cache_map_n; i++)
384 cache_map[i].fixed = 1;
385 cache_map_fixed = cache_map_n;
386
387 map_add_var();
388
389 pr_info("MTRR map: %u entries (%u fixed + %u variable; max %u), built from %u variable MTRRs\n",
390 cache_map_n, cache_map_fixed, cache_map_n - cache_map_fixed,
391 get_cache_map_size(), num_var_ranges + (mtrr_tom2 != 0));
392
393 if (mtrr_debug) {
394 for (i = 0; i < cache_map_n; i++) {
395 pr_info("%3u: %016llx-%016llx %s\n", i,
396 cache_map[i].start, cache_map[i].end - 1,
397 mtrr_attrib_to_str(cache_map[i].type));
398 }
399 }
400}
401
402/* Copy the cache_map from __initdata memory to dynamically allocated one. */
403void __init mtrr_copy_map(void)
404{
405 unsigned int new_size = get_cache_map_size();
406
407 if (!mtrr_state.enabled || !new_size) {
408 cache_map = NULL;
409 return;
410 }
411
412 mutex_lock(lock: &mtrr_mutex);
413
414 cache_map = kcalloc(new_size, sizeof(*cache_map), GFP_KERNEL);
415 if (cache_map) {
416 memmove(dest: cache_map, src: init_cache_map,
417 count: cache_map_n * sizeof(*cache_map));
418 cache_map_size = new_size;
419 } else {
420 mtrr_state.enabled = 0;
421 pr_err("MTRRs disabled due to allocation failure for lookup map.\n");
422 }
423
424 mutex_unlock(lock: &mtrr_mutex);
425}
426
427/**
428 * guest_force_mtrr_state - set static MTRR state for a guest
429 *
430 * Used to set MTRR state via different means (e.g. with data obtained from
431 * a hypervisor).
432 * Is allowed only for special cases when running virtualized. Must be called
433 * from the x86_init.hyper.init_platform() hook. It can be called only once.
434 * The MTRR state can't be changed afterwards. To ensure that, X86_FEATURE_MTRR
435 * is cleared.
436 *
437 * @var: MTRR variable range array to use
438 * @num_var: length of the @var array
439 * @def_type: default caching type
440 */
441void guest_force_mtrr_state(struct mtrr_var_range *var, unsigned int num_var,
442 mtrr_type def_type)
443{
444 unsigned int i;
445
446 /* Only allowed to be called once before mtrr_bp_init(). */
447 if (WARN_ON_ONCE(mtrr_state_set))
448 return;
449
450 /* Only allowed when running virtualized. */
451 if (!cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
452 return;
453
454 /*
455 * Only allowed for special virtualization cases:
456 * - when running as Hyper-V, SEV-SNP guest using vTOM
457 * - when running as Xen PV guest
458 * - when running as SEV-SNP or TDX guest to avoid unnecessary
459 * VMM communication/Virtualization exceptions (#VC, #VE)
460 */
461 if (!cc_platform_has(attr: CC_ATTR_GUEST_SEV_SNP) &&
462 !hv_is_isolation_supported() &&
463 !cpu_feature_enabled(X86_FEATURE_XENPV) &&
464 !cpu_feature_enabled(X86_FEATURE_TDX_GUEST))
465 return;
466
467 /* Disable MTRR in order to disable MTRR modifications. */
468 setup_clear_cpu_cap(X86_FEATURE_MTRR);
469
470 if (var) {
471 if (num_var > MTRR_MAX_VAR_RANGES) {
472 pr_warn("Trying to overwrite MTRR state with %u variable entries\n",
473 num_var);
474 num_var = MTRR_MAX_VAR_RANGES;
475 }
476 for (i = 0; i < num_var; i++)
477 mtrr_state.var_ranges[i] = var[i];
478 num_var_ranges = num_var;
479 }
480
481 mtrr_state.def_type = def_type;
482 mtrr_state.enabled |= MTRR_STATE_MTRR_ENABLED;
483
484 mtrr_state_set = 1;
485}
486
487static u8 type_merge(u8 type, u8 new_type, u8 *uniform)
488{
489 u8 effective_type;
490
491 if (type == MTRR_TYPE_INVALID)
492 return new_type;
493
494 effective_type = get_effective_type(type1: type, type2: new_type);
495 if (type != effective_type)
496 *uniform = 0;
497
498 return effective_type;
499}
500
501/**
502 * mtrr_type_lookup - look up memory type in MTRR
503 *
504 * @start: Begin of the physical address range
505 * @end: End of the physical address range
506 * @uniform: output argument:
507 * - 1: the returned MTRR type is valid for the whole region
508 * - 0: otherwise
509 *
510 * Return Values:
511 * MTRR_TYPE_(type) - The effective MTRR type for the region
512 * MTRR_TYPE_INVALID - MTRR is disabled
513 */
514u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform)
515{
516 u8 type = MTRR_TYPE_INVALID;
517 unsigned int i;
518
519 if (!mtrr_state_set) {
520 /* Uniformity is unknown. */
521 *uniform = 0;
522 return MTRR_TYPE_UNCACHABLE;
523 }
524
525 *uniform = 1;
526
527 if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED))
528 return MTRR_TYPE_UNCACHABLE;
529
530 for (i = 0; i < cache_map_n && start < end; i++) {
531 /* Region after current map entry? -> continue with next one. */
532 if (start >= cache_map[i].end)
533 continue;
534
535 /* Start of region not covered by current map entry? */
536 if (start < cache_map[i].start) {
537 /* At least some part of region has default type. */
538 type = type_merge(type, new_type: mtrr_state.def_type, uniform);
539 /* End of region not covered, too? -> lookup done. */
540 if (end <= cache_map[i].start)
541 return type;
542 }
543
544 /* At least part of region covered by map entry. */
545 type = type_merge(type, new_type: cache_map[i].type, uniform);
546
547 start = cache_map[i].end;
548 }
549
550 /* End of region past last entry in map? -> use default type. */
551 if (start < end)
552 type = type_merge(type, new_type: mtrr_state.def_type, uniform);
553
554 return type;
555}
556
557/* Get the MSR pair relating to a var range */
558static void
559get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
560{
561 rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
562 rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
563}
564
565/* Fill the MSR pair relating to a var range */
566void fill_mtrr_var_range(unsigned int index,
567 u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi)
568{
569 struct mtrr_var_range *vr;
570
571 vr = mtrr_state.var_ranges;
572
573 vr[index].base_lo = base_lo;
574 vr[index].base_hi = base_hi;
575 vr[index].mask_lo = mask_lo;
576 vr[index].mask_hi = mask_hi;
577}
578
579static void get_fixed_ranges(mtrr_type *frs)
580{
581 unsigned int *p = (unsigned int *)frs;
582 int i;
583
584 k8_check_syscfg_dram_mod_en();
585
586 rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]);
587
588 for (i = 0; i < 2; i++)
589 rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]);
590 for (i = 0; i < 8; i++)
591 rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]);
592}
593
594void mtrr_save_fixed_ranges(void *info)
595{
596 if (mtrr_state.have_fixed)
597 get_fixed_ranges(frs: mtrr_state.fixed_ranges);
598}
599
600static unsigned __initdata last_fixed_start;
601static unsigned __initdata last_fixed_end;
602static mtrr_type __initdata last_fixed_type;
603
604static void __init print_fixed_last(void)
605{
606 if (!last_fixed_end)
607 return;
608
609 pr_info(" %05X-%05X %s\n", last_fixed_start,
610 last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type));
611
612 last_fixed_end = 0;
613}
614
615static void __init update_fixed_last(unsigned base, unsigned end,
616 mtrr_type type)
617{
618 last_fixed_start = base;
619 last_fixed_end = end;
620 last_fixed_type = type;
621}
622
623static void __init
624print_fixed(unsigned base, unsigned step, const mtrr_type *types)
625{
626 unsigned i;
627
628 for (i = 0; i < 8; ++i, ++types, base += step) {
629 if (last_fixed_end == 0) {
630 update_fixed_last(base, end: base + step, type: *types);
631 continue;
632 }
633 if (last_fixed_end == base && last_fixed_type == *types) {
634 last_fixed_end = base + step;
635 continue;
636 }
637 /* new segments: gap or different type */
638 print_fixed_last();
639 update_fixed_last(base, end: base + step, type: *types);
640 }
641}
642
643static void __init print_mtrr_state(void)
644{
645 unsigned int i;
646 int high_width;
647
648 pr_info("MTRR default type: %s\n",
649 mtrr_attrib_to_str(mtrr_state.def_type));
650 if (mtrr_state.have_fixed) {
651 pr_info("MTRR fixed ranges %s:\n",
652 str_enabled_disabled(
653 (mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED) &&
654 (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)));
655 print_fixed(base: 0x00000, step: 0x10000, types: mtrr_state.fixed_ranges + 0);
656 for (i = 0; i < 2; ++i)
657 print_fixed(base: 0x80000 + i * 0x20000, step: 0x04000,
658 types: mtrr_state.fixed_ranges + (i + 1) * 8);
659 for (i = 0; i < 8; ++i)
660 print_fixed(base: 0xC0000 + i * 0x08000, step: 0x01000,
661 types: mtrr_state.fixed_ranges + (i + 3) * 8);
662
663 /* tail */
664 print_fixed_last();
665 }
666 pr_info("MTRR variable ranges %s:\n",
667 str_enabled_disabled(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED));
668 high_width = (boot_cpu_data.x86_phys_bits - (32 - PAGE_SHIFT) + 3) / 4;
669
670 for (i = 0; i < num_var_ranges; ++i) {
671 if (mtrr_state.var_ranges[i].mask_lo & MTRR_PHYSMASK_V)
672 pr_info(" %u base %0*X%05X000 mask %0*X%05X000 %s\n",
673 i,
674 high_width,
675 mtrr_state.var_ranges[i].base_hi,
676 mtrr_state.var_ranges[i].base_lo >> 12,
677 high_width,
678 mtrr_state.var_ranges[i].mask_hi,
679 mtrr_state.var_ranges[i].mask_lo >> 12,
680 mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo &
681 MTRR_PHYSBASE_TYPE));
682 else
683 pr_info(" %u disabled\n", i);
684 }
685 if (mtrr_tom2)
686 pr_info("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20);
687}
688
689/* Grab all of the MTRR state for this CPU into *state */
690bool __init get_mtrr_state(void)
691{
692 struct mtrr_var_range *vrs;
693 unsigned lo, dummy;
694 unsigned int i;
695
696 vrs = mtrr_state.var_ranges;
697
698 rdmsr(MSR_MTRRcap, lo, dummy);
699 mtrr_state.have_fixed = lo & MTRR_CAP_FIX;
700
701 for (i = 0; i < num_var_ranges; i++)
702 get_mtrr_var_range(index: i, vr: &vrs[i]);
703 if (mtrr_state.have_fixed)
704 get_fixed_ranges(frs: mtrr_state.fixed_ranges);
705
706 rdmsr(MSR_MTRRdefType, lo, dummy);
707 mtrr_state.def_type = lo & MTRR_DEF_TYPE_TYPE;
708 mtrr_state.enabled = (lo & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT;
709
710 if (amd_special_default_mtrr()) {
711 unsigned low, high;
712
713 /* TOP_MEM2 */
714 rdmsr(MSR_K8_TOP_MEM2, low, high);
715 mtrr_tom2 = high;
716 mtrr_tom2 <<= 32;
717 mtrr_tom2 |= low;
718 mtrr_tom2 &= 0xffffff800000ULL;
719 }
720
721 if (mtrr_debug)
722 print_mtrr_state();
723
724 mtrr_state_set = 1;
725
726 return !!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED);
727}
728
729/* Some BIOS's are messed up and don't set all MTRRs the same! */
730void __init mtrr_state_warn(void)
731{
732 unsigned long mask = smp_changes_mask;
733
734 if (!mask)
735 return;
736 if (mask & MTRR_CHANGE_MASK_FIXED)
737 pr_warn("mtrr: your CPUs had inconsistent fixed MTRR settings\n");
738 if (mask & MTRR_CHANGE_MASK_VARIABLE)
739 pr_warn("mtrr: your CPUs had inconsistent variable MTRR settings\n");
740 if (mask & MTRR_CHANGE_MASK_DEFTYPE)
741 pr_warn("mtrr: your CPUs had inconsistent MTRRdefType settings\n");
742
743 pr_info("mtrr: probably your BIOS does not setup all CPUs.\n");
744 pr_info("mtrr: corrected configuration.\n");
745}
746
747/*
748 * Doesn't attempt to pass an error out to MTRR users
749 * because it's quite complicated in some cases and probably not
750 * worth it because the best error handling is to ignore it.
751 */
752void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b)
753{
754 if (wrmsr_safe(msr, low: a, high: b) < 0) {
755 pr_err("MTRR: CPU %u: Writing MSR %x to %x:%x failed\n",
756 smp_processor_id(), msr, a, b);
757 }
758}
759
760/**
761 * set_fixed_range - checks & updates a fixed-range MTRR if it
762 * differs from the value it should have
763 * @msr: MSR address of the MTTR which should be checked and updated
764 * @changed: pointer which indicates whether the MTRR needed to be changed
765 * @msrwords: pointer to the MSR values which the MSR should have
766 */
767static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
768{
769 unsigned lo, hi;
770
771 rdmsr(msr, lo, hi);
772
773 if (lo != msrwords[0] || hi != msrwords[1]) {
774 mtrr_wrmsr(msr, a: msrwords[0], b: msrwords[1]);
775 *changed = true;
776 }
777}
778
779/**
780 * generic_get_free_region - Get a free MTRR.
781 * @base: The starting (base) address of the region.
782 * @size: The size (in bytes) of the region.
783 * @replace_reg: mtrr index to be replaced; set to invalid value if none.
784 *
785 * Returns: The index of the region on success, else negative on error.
786 */
787int
788generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)
789{
790 unsigned long lbase, lsize;
791 mtrr_type ltype;
792 int i, max;
793
794 max = num_var_ranges;
795 if (replace_reg >= 0 && replace_reg < max)
796 return replace_reg;
797
798 for (i = 0; i < max; ++i) {
799 mtrr_if->get(i, &lbase, &lsize, &ltype);
800 if (lsize == 0)
801 return i;
802 }
803
804 return -ENOSPC;
805}
806
807static void generic_get_mtrr(unsigned int reg, unsigned long *base,
808 unsigned long *size, mtrr_type *type)
809{
810 u32 mask_lo, mask_hi, base_lo, base_hi;
811 unsigned int hi;
812 u64 tmp, mask;
813
814 /*
815 * get_mtrr doesn't need to update mtrr_state, also it could be called
816 * from any cpu, so try to print it out directly.
817 */
818 get_cpu();
819
820 rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
821
822 if (!(mask_lo & MTRR_PHYSMASK_V)) {
823 /* Invalid (i.e. free) range */
824 *base = 0;
825 *size = 0;
826 *type = 0;
827 goto out_put_cpu;
828 }
829
830 rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi);
831
832 /* Work out the shifted address mask: */
833 tmp = (u64)mask_hi << 32 | (mask_lo & PAGE_MASK);
834 mask = (u64)phys_hi_rsvd << 32 | tmp;
835
836 /* Expand tmp with high bits to all 1s: */
837 hi = fls64(x: tmp);
838 if (hi > 0) {
839 tmp |= ~((1ULL<<(hi - 1)) - 1);
840
841 if (tmp != mask) {
842 pr_warn("mtrr: your BIOS has configured an incorrect mask, fixing it.\n");
843 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
844 mask = tmp;
845 }
846 }
847
848 /*
849 * This works correctly if size is a power of two, i.e. a
850 * contiguous range:
851 */
852 *size = -mask >> PAGE_SHIFT;
853 *base = (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
854 *type = base_lo & MTRR_PHYSBASE_TYPE;
855
856out_put_cpu:
857 put_cpu();
858}
859
860/**
861 * set_fixed_ranges - checks & updates the fixed-range MTRRs if they
862 * differ from the saved set
863 * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges()
864 */
865static int set_fixed_ranges(mtrr_type *frs)
866{
867 unsigned long long *saved = (unsigned long long *)frs;
868 bool changed = false;
869 int block = -1, range;
870
871 k8_check_syscfg_dram_mod_en();
872
873 while (fixed_range_blocks[++block].ranges) {
874 for (range = 0; range < fixed_range_blocks[block].ranges; range++)
875 set_fixed_range(msr: fixed_range_blocks[block].base_msr + range,
876 changed: &changed, msrwords: (unsigned int *)saved++);
877 }
878
879 return changed;
880}
881
882/*
883 * Set the MSR pair relating to a var range.
884 * Returns true if changes are made.
885 */
886static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
887{
888 unsigned int lo, hi;
889 bool changed = false;
890
891 rdmsr(MTRRphysBase_MSR(index), lo, hi);
892 if ((vr->base_lo & ~MTRR_PHYSBASE_RSVD) != (lo & ~MTRR_PHYSBASE_RSVD)
893 || (vr->base_hi & ~phys_hi_rsvd) != (hi & ~phys_hi_rsvd)) {
894
895 mtrr_wrmsr(MTRRphysBase_MSR(index), a: vr->base_lo, b: vr->base_hi);
896 changed = true;
897 }
898
899 rdmsr(MTRRphysMask_MSR(index), lo, hi);
900
901 if ((vr->mask_lo & ~MTRR_PHYSMASK_RSVD) != (lo & ~MTRR_PHYSMASK_RSVD)
902 || (vr->mask_hi & ~phys_hi_rsvd) != (hi & ~phys_hi_rsvd)) {
903 mtrr_wrmsr(MTRRphysMask_MSR(index), a: vr->mask_lo, b: vr->mask_hi);
904 changed = true;
905 }
906 return changed;
907}
908
909static u32 deftype_lo, deftype_hi;
910
911/**
912 * set_mtrr_state - Set the MTRR state for this CPU.
913 *
914 * NOTE: The CPU must already be in a safe state for MTRR changes, including
915 * measures that only a single CPU can be active in set_mtrr_state() in
916 * order to not be subject to races for usage of deftype_lo. This is
917 * accomplished by taking cache_disable_lock.
918 * RETURNS: 0 if no changes made, else a mask indicating what was changed.
919 */
920static unsigned long set_mtrr_state(void)
921{
922 unsigned long change_mask = 0;
923 unsigned int i;
924
925 for (i = 0; i < num_var_ranges; i++) {
926 if (set_mtrr_var_ranges(index: i, vr: &mtrr_state.var_ranges[i]))
927 change_mask |= MTRR_CHANGE_MASK_VARIABLE;
928 }
929
930 if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges))
931 change_mask |= MTRR_CHANGE_MASK_FIXED;
932
933 /*
934 * Set_mtrr_restore restores the old value of MTRRdefType,
935 * so to set it we fiddle with the saved value:
936 */
937 if ((deftype_lo & MTRR_DEF_TYPE_TYPE) != mtrr_state.def_type ||
938 ((deftype_lo & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT) != mtrr_state.enabled) {
939
940 deftype_lo = (deftype_lo & MTRR_DEF_TYPE_DISABLE) |
941 mtrr_state.def_type |
942 (mtrr_state.enabled << MTRR_STATE_SHIFT);
943 change_mask |= MTRR_CHANGE_MASK_DEFTYPE;
944 }
945
946 return change_mask;
947}
948
949void mtrr_disable(void)
950{
951 /* Save MTRR state */
952 rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
953
954 /* Disable MTRRs, and set the default type to uncached */
955 mtrr_wrmsr(MSR_MTRRdefType, a: deftype_lo & MTRR_DEF_TYPE_DISABLE, b: deftype_hi);
956}
957
958void mtrr_enable(void)
959{
960 /* Intel (P6) standard MTRRs */
961 mtrr_wrmsr(MSR_MTRRdefType, a: deftype_lo, b: deftype_hi);
962}
963
964void mtrr_generic_set_state(void)
965{
966 unsigned long mask, count;
967
968 /* Actually set the state */
969 mask = set_mtrr_state();
970
971 /* Use the atomic bitops to update the global mask */
972 for (count = 0; count < sizeof(mask) * 8; ++count) {
973 if (mask & 0x01)
974 set_bit(nr: count, addr: &smp_changes_mask);
975 mask >>= 1;
976 }
977}
978
979/**
980 * generic_set_mtrr - set variable MTRR register on the local CPU.
981 *
982 * @reg: The register to set.
983 * @base: The base address of the region.
984 * @size: The size of the region. If this is 0 the region is disabled.
985 * @type: The type of the region.
986 *
987 * Returns nothing.
988 */
989static void generic_set_mtrr(unsigned int reg, unsigned long base,
990 unsigned long size, mtrr_type type)
991{
992 unsigned long flags;
993 struct mtrr_var_range *vr;
994
995 vr = &mtrr_state.var_ranges[reg];
996
997 local_irq_save(flags);
998 cache_disable();
999
1000 if (size == 0) {
1001 /*
1002 * The invalid bit is kept in the mask, so we simply
1003 * clear the relevant mask register to disable a range.
1004 */
1005 mtrr_wrmsr(MTRRphysMask_MSR(reg), a: 0, b: 0);
1006 memset(s: vr, c: 0, n: sizeof(struct mtrr_var_range));
1007 } else {
1008 vr->base_lo = base << PAGE_SHIFT | type;
1009 vr->base_hi = (base >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd;
1010 vr->mask_lo = -size << PAGE_SHIFT | MTRR_PHYSMASK_V;
1011 vr->mask_hi = (-size >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd;
1012
1013 mtrr_wrmsr(MTRRphysBase_MSR(reg), a: vr->base_lo, b: vr->base_hi);
1014 mtrr_wrmsr(MTRRphysMask_MSR(reg), a: vr->mask_lo, b: vr->mask_hi);
1015 }
1016
1017 cache_enable();
1018 local_irq_restore(flags);
1019}
1020
1021int generic_validate_add_page(unsigned long base, unsigned long size,
1022 unsigned int type)
1023{
1024 unsigned long lbase, last;
1025
1026 /*
1027 * For Intel PPro stepping <= 7
1028 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF
1029 */
1030 if (mtrr_if == &generic_mtrr_ops && boot_cpu_data.x86_vfm == INTEL_PENTIUM_PRO &&
1031 boot_cpu_data.x86_stepping <= 7) {
1032 if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
1033 pr_warn("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
1034 return -EINVAL;
1035 }
1036 if (!(base + size < 0x70000 || base > 0x7003F) &&
1037 (type == MTRR_TYPE_WRCOMB
1038 || type == MTRR_TYPE_WRBACK)) {
1039 pr_warn("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n");
1040 return -EINVAL;
1041 }
1042 }
1043
1044 /*
1045 * Check upper bits of base and last are equal and lower bits are 0
1046 * for base and 1 for last
1047 */
1048 last = base + size - 1;
1049 for (lbase = base; !(lbase & 1) && (last & 1);
1050 lbase = lbase >> 1, last = last >> 1)
1051 ;
1052 if (lbase != last) {
1053 pr_warn("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size);
1054 return -EINVAL;
1055 }
1056 return 0;
1057}
1058
1059static int generic_have_wrcomb(void)
1060{
1061 unsigned long config, dummy;
1062 rdmsr(MSR_MTRRcap, config, dummy);
1063 return config & MTRR_CAP_WC;
1064}
1065
1066int positive_have_wrcomb(void)
1067{
1068 return 1;
1069}
1070
1071/*
1072 * Generic structure...
1073 */
1074const struct mtrr_ops generic_mtrr_ops = {
1075 .get = generic_get_mtrr,
1076 .get_free_region = generic_get_free_region,
1077 .set = generic_set_mtrr,
1078 .validate_add_page = generic_validate_add_page,
1079 .have_wrcomb = generic_have_wrcomb,
1080};
1081