1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Low-Level PCI Support for PC -- Routing of Interrupts
4 *
5 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
6 */
7
8#include <linux/types.h>
9#include <linux/kernel.h>
10#include <linux/pci.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/dmi.h>
14#include <linux/io.h>
15#include <linux/smp.h>
16#include <linux/spinlock.h>
17#include <asm/io_apic.h>
18#include <linux/irq.h>
19#include <linux/acpi.h>
20
21#include <asm/i8259.h>
22#include <asm/pc-conf-reg.h>
23#include <asm/pci_x86.h>
24
25#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
26#define PIRQ_VERSION 0x0100
27
28#define IRT_SIGNATURE (('$' << 0) + ('I' << 8) + ('R' << 16) + ('T' << 24))
29
30static int broken_hp_bios_irq9;
31static int acer_tm360_irqrouting;
32
33static struct irq_routing_table *pirq_table;
34
35static int pirq_enable_irq(struct pci_dev *dev);
36static void pirq_disable_irq(struct pci_dev *dev);
37
38/*
39 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
40 * Avoid using: 13, 14 and 15 (FP error and IDE).
41 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
42 */
43unsigned int pcibios_irq_mask = 0xfff8;
44
45static int pirq_penalty[16] = {
46 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
47 0, 0, 0, 0, 1000, 100000, 100000, 100000
48};
49
50struct irq_router {
51 char *name;
52 u16 vendor, device;
53 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
54 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq,
55 int new);
56 int (*lvl)(struct pci_dev *router, struct pci_dev *dev, int pirq,
57 int irq);
58};
59
60struct irq_router_handler {
61 u16 vendor;
62 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
63};
64
65int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq;
66void (*pcibios_disable_irq)(struct pci_dev *dev) = pirq_disable_irq;
67
68/*
69 * Check passed address for the PCI IRQ Routing Table signature
70 * and perform checksum verification.
71 */
72
73static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr,
74 u8 *limit)
75{
76 struct irq_routing_table *rt;
77 int i;
78 u8 sum;
79
80 rt = (struct irq_routing_table *)addr;
81 if (rt->signature != PIRQ_SIGNATURE ||
82 rt->version != PIRQ_VERSION ||
83 rt->size % 16 ||
84 rt->size < sizeof(struct irq_routing_table) ||
85 (limit && rt->size > limit - addr))
86 return NULL;
87 sum = 0;
88 for (i = 0; i < rt->size; i++)
89 sum += addr[i];
90 if (!sum) {
91 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%lx\n",
92 __pa(rt));
93 return rt;
94 }
95 return NULL;
96}
97
98/*
99 * Handle the $IRT PCI IRQ Routing Table format used by AMI for its BCP
100 * (BIOS Configuration Program) external tool meant for tweaking BIOS
101 * structures without the need to rebuild it from sources. The $IRT
102 * format has been invented by AMI before Microsoft has come up with its
103 * $PIR format and a $IRT table is therefore there in some systems that
104 * lack a $PIR table.
105 *
106 * It uses the same PCI BIOS 2.1 format for interrupt routing entries
107 * themselves but has a different simpler header prepended instead,
108 * occupying 8 bytes, where a `$IRT' signature is followed by one byte
109 * specifying the total number of interrupt routing entries allocated in
110 * the table, then one byte specifying the actual number of entries used
111 * (which the BCP tool can take advantage of when modifying the table),
112 * and finally a 16-bit word giving the IRQs devoted exclusively to PCI.
113 * Unlike with the $PIR table there is no alignment guarantee.
114 *
115 * Given the similarity of the two formats the $IRT one is trivial to
116 * convert to the $PIR one, which we do here, except that obviously we
117 * have no information as to the router device to use, but we can handle
118 * it by matching PCI device IDs actually seen on the bus against ones
119 * that our individual routers recognise.
120 *
121 * Reportedly there is another $IRT table format where a 16-bit word
122 * follows the header instead that points to interrupt routing entries
123 * in a $PIR table provided elsewhere. In that case this code will not
124 * be reached though as the $PIR table will have been chosen instead.
125 */
126static inline struct irq_routing_table *pirq_convert_irt_table(u8 *addr,
127 u8 *limit)
128{
129 struct irt_routing_table *ir;
130 struct irq_routing_table *rt;
131 u16 size;
132 u8 sum;
133 int i;
134
135 ir = (struct irt_routing_table *)addr;
136 if (ir->signature != IRT_SIGNATURE || !ir->used || ir->size < ir->used)
137 return NULL;
138
139 size = struct_size(ir, slots, ir->used);
140 if (size > limit - addr)
141 return NULL;
142
143 DBG(KERN_DEBUG "PCI: $IRT Interrupt Routing Table found at 0x%lx\n",
144 __pa(ir));
145
146 size = struct_size(rt, slots, ir->used);
147 rt = kzalloc(size, GFP_KERNEL);
148 if (!rt)
149 return NULL;
150
151 rt->signature = PIRQ_SIGNATURE;
152 rt->version = PIRQ_VERSION;
153 rt->size = size;
154 rt->exclusive_irqs = ir->exclusive_irqs;
155 for (i = 0; i < ir->used; i++)
156 rt->slots[i] = ir->slots[i];
157
158 addr = (u8 *)rt;
159 sum = 0;
160 for (i = 0; i < size; i++)
161 sum += addr[i];
162 rt->checksum = -sum;
163
164 return rt;
165}
166
167/*
168 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
169 */
170
171static struct irq_routing_table * __init pirq_find_routing_table(void)
172{
173 u8 * const bios_start = (u8 *)__va(0xf0000);
174 u8 * const bios_end = (u8 *)__va(0x100000);
175 u8 *addr;
176 struct irq_routing_table *rt;
177
178 if (pirq_table_addr) {
179 rt = pirq_check_routing_table(addr: (u8 *)__va(pirq_table_addr),
180 NULL);
181 if (rt)
182 return rt;
183 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n");
184 }
185 for (addr = bios_start;
186 addr < bios_end - sizeof(struct irq_routing_table);
187 addr += 16) {
188 rt = pirq_check_routing_table(addr, limit: bios_end);
189 if (rt)
190 return rt;
191 }
192 for (addr = bios_start;
193 addr < bios_end - sizeof(struct irt_routing_table);
194 addr++) {
195 rt = pirq_convert_irt_table(addr, limit: bios_end);
196 if (rt)
197 return rt;
198 }
199 return NULL;
200}
201
202/*
203 * If we have a IRQ routing table, use it to search for peer host
204 * bridges. It's a gross hack, but since there are no other known
205 * ways how to get a list of buses, we have to go this way.
206 */
207
208static void __init pirq_peer_trick(void)
209{
210 struct irq_routing_table *rt = pirq_table;
211 u8 busmap[256];
212 int i;
213 struct irq_info *e;
214
215 memset(s: busmap, c: 0, n: sizeof(busmap));
216 for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
217 e = &rt->slots[i];
218#ifdef DEBUG
219 {
220 int j;
221 DBG(KERN_DEBUG "%02x:%02x.%x slot=%02x",
222 e->bus, e->devfn / 8, e->devfn % 8, e->slot);
223 for (j = 0; j < 4; j++)
224 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
225 DBG("\n");
226 }
227#endif
228 busmap[e->bus] = 1;
229 }
230 for (i = 1; i < 256; i++) {
231 if (!busmap[i] || pci_find_bus(domain: 0, busnr: i))
232 continue;
233 pcibios_scan_root(bus: i);
234 }
235 pcibios_last_bus = -1;
236}
237
238/*
239 * Code for querying and setting of IRQ routes on various interrupt routers.
240 * PIC Edge/Level Control Registers (ELCR) 0x4d0 & 0x4d1.
241 */
242
243void elcr_set_level_irq(unsigned int irq)
244{
245 unsigned char mask = 1 << (irq & 7);
246 unsigned int port = PIC_ELCR1 + (irq >> 3);
247 unsigned char val;
248 static u16 elcr_irq_mask;
249
250 if (irq >= 16 || (1 << irq) & elcr_irq_mask)
251 return;
252
253 elcr_irq_mask |= (1 << irq);
254 printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq);
255 val = inb(port);
256 if (!(val & mask)) {
257 DBG(KERN_DEBUG " -> edge");
258 outb(value: val | mask, port);
259 }
260}
261
262/*
263 * PIRQ routing for the M1487 ISA Bus Controller (IBC) ASIC used
264 * with the ALi FinALi 486 chipset. The IBC is not decoded in the
265 * PCI configuration space, so we identify it by the accompanying
266 * M1489 Cache-Memory PCI Controller (CMP) ASIC.
267 *
268 * There are four 4-bit mappings provided, spread across two PCI
269 * INTx Routing Table Mapping Registers, available in the port I/O
270 * space accessible indirectly via the index/data register pair at
271 * 0x22/0x23, located at indices 0x42 and 0x43 for the INT1/INT2
272 * and INT3/INT4 lines respectively. The INT1/INT3 and INT2/INT4
273 * lines are mapped in the low and the high 4-bit nibble of the
274 * corresponding register as follows:
275 *
276 * 0000 : Disabled
277 * 0001 : IRQ9
278 * 0010 : IRQ3
279 * 0011 : IRQ10
280 * 0100 : IRQ4
281 * 0101 : IRQ5
282 * 0110 : IRQ7
283 * 0111 : IRQ6
284 * 1000 : Reserved
285 * 1001 : IRQ11
286 * 1010 : Reserved
287 * 1011 : IRQ12
288 * 1100 : Reserved
289 * 1101 : IRQ14
290 * 1110 : Reserved
291 * 1111 : IRQ15
292 *
293 * In addition to the usual ELCR register pair there is a separate
294 * PCI INTx Sensitivity Register at index 0x44 in the same port I/O
295 * space, whose bits 3:0 select the trigger mode for INT[4:1] lines
296 * respectively. Any bit set to 1 causes interrupts coming on the
297 * corresponding line to be passed to ISA as edge-triggered and
298 * otherwise they are passed as level-triggered. Manufacturer's
299 * documentation says this register has to be set consistently with
300 * the relevant ELCR register.
301 *
302 * Accesses to the port I/O space concerned here need to be unlocked
303 * by writing the value of 0xc5 to the Lock Register at index 0x03
304 * beforehand. Any other value written to said register prevents
305 * further accesses from reaching the register file, except for the
306 * Lock Register being written with 0xc5 again.
307 *
308 * References:
309 *
310 * "M1489/M1487: 486 PCI Chip Set", Version 1.2, Acer Laboratories
311 * Inc., July 1997
312 */
313
314#define PC_CONF_FINALI_LOCK 0x03u
315#define PC_CONF_FINALI_PCI_INTX_RT1 0x42u
316#define PC_CONF_FINALI_PCI_INTX_RT2 0x43u
317#define PC_CONF_FINALI_PCI_INTX_SENS 0x44u
318
319#define PC_CONF_FINALI_LOCK_KEY 0xc5u
320
321static u8 read_pc_conf_nybble(u8 base, u8 index)
322{
323 u8 reg = base + (index >> 1);
324 u8 x;
325
326 x = pc_conf_get(reg);
327 return index & 1 ? x >> 4 : x & 0xf;
328}
329
330static void write_pc_conf_nybble(u8 base, u8 index, u8 val)
331{
332 u8 reg = base + (index >> 1);
333 u8 x;
334
335 x = pc_conf_get(reg);
336 x = index & 1 ? (x & 0x0f) | (val << 4) : (x & 0xf0) | val;
337 pc_conf_set(reg, data: x);
338}
339
340/*
341 * FinALi pirq rules are as follows:
342 *
343 * - bit 0 selects between INTx Routing Table Mapping Registers,
344 *
345 * - bit 3 selects the nibble within the INTx Routing Table Mapping Register,
346 *
347 * - bits 7:4 map to bits 3:0 of the PCI INTx Sensitivity Register.
348 */
349static int pirq_finali_get(struct pci_dev *router, struct pci_dev *dev,
350 int pirq)
351{
352 static const u8 irqmap[16] = {
353 0, 9, 3, 10, 4, 5, 7, 6, 0, 11, 0, 12, 0, 14, 0, 15
354 };
355 unsigned long flags;
356 u8 index;
357 u8 x;
358
359 index = (pirq & 1) << 1 | (pirq & 8) >> 3;
360 raw_spin_lock_irqsave(&pc_conf_lock, flags);
361 pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY);
362 x = irqmap[read_pc_conf_nybble(PC_CONF_FINALI_PCI_INTX_RT1, index)];
363 pc_conf_set(PC_CONF_FINALI_LOCK, data: 0);
364 raw_spin_unlock_irqrestore(&pc_conf_lock, flags);
365 return x;
366}
367
368static int pirq_finali_set(struct pci_dev *router, struct pci_dev *dev,
369 int pirq, int irq)
370{
371 static const u8 irqmap[16] = {
372 0, 0, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15
373 };
374 u8 val = irqmap[irq];
375 unsigned long flags;
376 u8 index;
377
378 if (!val)
379 return 0;
380
381 index = (pirq & 1) << 1 | (pirq & 8) >> 3;
382 raw_spin_lock_irqsave(&pc_conf_lock, flags);
383 pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY);
384 write_pc_conf_nybble(PC_CONF_FINALI_PCI_INTX_RT1, index, val);
385 pc_conf_set(PC_CONF_FINALI_LOCK, data: 0);
386 raw_spin_unlock_irqrestore(&pc_conf_lock, flags);
387 return 1;
388}
389
390static int pirq_finali_lvl(struct pci_dev *router, struct pci_dev *dev,
391 int pirq, int irq)
392{
393 u8 mask = ~((pirq & 0xf0u) >> 4);
394 unsigned long flags;
395 u8 trig;
396
397 elcr_set_level_irq(irq);
398 raw_spin_lock_irqsave(&pc_conf_lock, flags);
399 pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY);
400 trig = pc_conf_get(PC_CONF_FINALI_PCI_INTX_SENS);
401 trig &= mask;
402 pc_conf_set(PC_CONF_FINALI_PCI_INTX_SENS, data: trig);
403 pc_conf_set(PC_CONF_FINALI_LOCK, data: 0);
404 raw_spin_unlock_irqrestore(&pc_conf_lock, flags);
405 return 1;
406}
407
408/*
409 * Common IRQ routing practice: nibbles in config space,
410 * offset by some magic constant.
411 */
412static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
413{
414 u8 x;
415 unsigned reg = offset + (nr >> 1);
416
417 pci_read_config_byte(dev: router, where: reg, val: &x);
418 return (nr & 1) ? (x >> 4) : (x & 0xf);
419}
420
421static void write_config_nybble(struct pci_dev *router, unsigned offset,
422 unsigned nr, unsigned int val)
423{
424 u8 x;
425 unsigned reg = offset + (nr >> 1);
426
427 pci_read_config_byte(dev: router, where: reg, val: &x);
428 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
429 pci_write_config_byte(dev: router, where: reg, val: x);
430}
431
432/*
433 * ALI pirq entries are damn ugly, and completely undocumented.
434 * This has been figured out from pirq tables, and it's not a pretty
435 * picture.
436 */
437static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
438{
439 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
440
441 WARN_ON_ONCE(pirq > 16);
442 return irqmap[read_config_nybble(router, offset: 0x48, nr: pirq-1)];
443}
444
445static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
446{
447 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
448 unsigned int val = irqmap[irq];
449
450 WARN_ON_ONCE(pirq > 16);
451 if (val) {
452 write_config_nybble(router, offset: 0x48, nr: pirq-1, val);
453 return 1;
454 }
455 return 0;
456}
457
458/*
459 * PIRQ routing for the 82374EB/82374SB EISA System Component (ESC)
460 * ASIC used with the Intel 82420 and 82430 PCIsets. The ESC is not
461 * decoded in the PCI configuration space, so we identify it by the
462 * accompanying 82375EB/82375SB PCI-EISA Bridge (PCEB) ASIC.
463 *
464 * There are four PIRQ Route Control registers, available in the
465 * port I/O space accessible indirectly via the index/data register
466 * pair at 0x22/0x23, located at indices 0x60/0x61/0x62/0x63 for the
467 * PIRQ0/1/2/3# lines respectively. The semantics is the same as
468 * with the PIIX router.
469 *
470 * Accesses to the port I/O space concerned here need to be unlocked
471 * by writing the value of 0x0f to the ESC ID Register at index 0x02
472 * beforehand. Any other value written to said register prevents
473 * further accesses from reaching the register file, except for the
474 * ESC ID Register being written with 0x0f again.
475 *
476 * References:
477 *
478 * "82374EB/82374SB EISA System Component (ESC)", Intel Corporation,
479 * Order Number: 290476-004, March 1996
480 *
481 * "82375EB/82375SB PCI-EISA Bridge (PCEB)", Intel Corporation, Order
482 * Number: 290477-004, March 1996
483 */
484
485#define PC_CONF_I82374_ESC_ID 0x02u
486#define PC_CONF_I82374_PIRQ_ROUTE_CONTROL 0x60u
487
488#define PC_CONF_I82374_ESC_ID_KEY 0x0fu
489
490static int pirq_esc_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
491{
492 unsigned long flags;
493 int reg;
494 u8 x;
495
496 reg = pirq;
497 if (reg >= 1 && reg <= 4)
498 reg += PC_CONF_I82374_PIRQ_ROUTE_CONTROL - 1;
499
500 raw_spin_lock_irqsave(&pc_conf_lock, flags);
501 pc_conf_set(PC_CONF_I82374_ESC_ID, PC_CONF_I82374_ESC_ID_KEY);
502 x = pc_conf_get(reg);
503 pc_conf_set(PC_CONF_I82374_ESC_ID, data: 0);
504 raw_spin_unlock_irqrestore(&pc_conf_lock, flags);
505 return (x < 16) ? x : 0;
506}
507
508static int pirq_esc_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
509 int irq)
510{
511 unsigned long flags;
512 int reg;
513
514 reg = pirq;
515 if (reg >= 1 && reg <= 4)
516 reg += PC_CONF_I82374_PIRQ_ROUTE_CONTROL - 1;
517
518 raw_spin_lock_irqsave(&pc_conf_lock, flags);
519 pc_conf_set(PC_CONF_I82374_ESC_ID, PC_CONF_I82374_ESC_ID_KEY);
520 pc_conf_set(reg, data: irq);
521 pc_conf_set(PC_CONF_I82374_ESC_ID, data: 0);
522 raw_spin_unlock_irqrestore(&pc_conf_lock, flags);
523 return 1;
524}
525
526/*
527 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
528 * just a pointer to the config space.
529 */
530static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
531{
532 u8 x;
533
534 pci_read_config_byte(dev: router, where: pirq, val: &x);
535 return (x < 16) ? x : 0;
536}
537
538static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
539{
540 pci_write_config_byte(dev: router, where: pirq, val: irq);
541 return 1;
542}
543
544/*
545 * PIRQ routing for the 82426EX ISA Bridge (IB) ASIC used with the
546 * Intel 82420EX PCIset.
547 *
548 * There are only two PIRQ Route Control registers, available in the
549 * combined 82425EX/82426EX PCI configuration space, at 0x66 and 0x67
550 * for the PIRQ0# and PIRQ1# lines respectively. The semantics is
551 * the same as with the PIIX router.
552 *
553 * References:
554 *
555 * "82420EX PCIset Data Sheet, 82425EX PCI System Controller (PSC)
556 * and 82426EX ISA Bridge (IB)", Intel Corporation, Order Number:
557 * 290488-004, December 1995
558 */
559
560#define PCI_I82426EX_PIRQ_ROUTE_CONTROL 0x66u
561
562static int pirq_ib_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
563{
564 int reg;
565 u8 x;
566
567 reg = pirq;
568 if (reg >= 1 && reg <= 2)
569 reg += PCI_I82426EX_PIRQ_ROUTE_CONTROL - 1;
570
571 pci_read_config_byte(dev: router, where: reg, val: &x);
572 return (x < 16) ? x : 0;
573}
574
575static int pirq_ib_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
576 int irq)
577{
578 int reg;
579
580 reg = pirq;
581 if (reg >= 1 && reg <= 2)
582 reg += PCI_I82426EX_PIRQ_ROUTE_CONTROL - 1;
583
584 pci_write_config_byte(dev: router, where: reg, val: irq);
585 return 1;
586}
587
588/*
589 * The VIA pirq rules are nibble-based, like ALI,
590 * but without the ugly irq number munging.
591 * However, PIRQD is in the upper instead of lower 4 bits.
592 */
593static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
594{
595 return read_config_nybble(router, offset: 0x55, nr: pirq == 4 ? 5 : pirq);
596}
597
598static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
599{
600 write_config_nybble(router, offset: 0x55, nr: pirq == 4 ? 5 : pirq, val: irq);
601 return 1;
602}
603
604/*
605 * The VIA pirq rules are nibble-based, like ALI,
606 * but without the ugly irq number munging.
607 * However, for 82C586, nibble map is different .
608 */
609static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
610{
611 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
612
613 WARN_ON_ONCE(pirq > 5);
614 return read_config_nybble(router, offset: 0x55, nr: pirqmap[pirq-1]);
615}
616
617static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
618{
619 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
620
621 WARN_ON_ONCE(pirq > 5);
622 write_config_nybble(router, offset: 0x55, nr: pirqmap[pirq-1], val: irq);
623 return 1;
624}
625
626/*
627 * ITE 8330G pirq rules are nibble-based
628 * FIXME: pirqmap may be { 1, 0, 3, 2 },
629 * 2+3 are both mapped to irq 9 on my system
630 */
631static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
632{
633 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
634
635 WARN_ON_ONCE(pirq > 4);
636 return read_config_nybble(router, offset: 0x43, nr: pirqmap[pirq-1]);
637}
638
639static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
640{
641 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
642
643 WARN_ON_ONCE(pirq > 4);
644 write_config_nybble(router, offset: 0x43, nr: pirqmap[pirq-1], val: irq);
645 return 1;
646}
647
648/*
649 * OPTI: high four bits are nibble pointer..
650 * I wonder what the low bits do?
651 */
652static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
653{
654 return read_config_nybble(router, offset: 0xb8, nr: pirq >> 4);
655}
656
657static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
658{
659 write_config_nybble(router, offset: 0xb8, nr: pirq >> 4, val: irq);
660 return 1;
661}
662
663/*
664 * Cyrix: nibble offset 0x5C
665 * 0x5C bits 7:4 is INTB bits 3:0 is INTA
666 * 0x5D bits 7:4 is INTD bits 3:0 is INTC
667 */
668static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
669{
670 return read_config_nybble(router, offset: 0x5C, nr: (pirq-1)^1);
671}
672
673static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
674{
675 write_config_nybble(router, offset: 0x5C, nr: (pirq-1)^1, val: irq);
676 return 1;
677}
678
679
680/*
681 * PIRQ routing for the SiS85C497 AT Bus Controller & Megacell (ATM)
682 * ISA bridge used with the SiS 85C496/497 486 Green PC VESA/ISA/PCI
683 * Chipset.
684 *
685 * There are four PCI INTx#-to-IRQ Link registers provided in the
686 * SiS85C497 part of the peculiar combined 85C496/497 configuration
687 * space decoded by the SiS85C496 PCI & CPU Memory Controller (PCM)
688 * host bridge, at 0xc0/0xc1/0xc2/0xc3 respectively for the PCI INT
689 * A/B/C/D lines. Bit 7 enables the respective link if set and bits
690 * 3:0 select the 8259A IRQ line as follows:
691 *
692 * 0000 : Reserved
693 * 0001 : Reserved
694 * 0010 : Reserved
695 * 0011 : IRQ3
696 * 0100 : IRQ4
697 * 0101 : IRQ5
698 * 0110 : IRQ6
699 * 0111 : IRQ7
700 * 1000 : Reserved
701 * 1001 : IRQ9
702 * 1010 : IRQ10
703 * 1011 : IRQ11
704 * 1100 : IRQ12
705 * 1101 : Reserved
706 * 1110 : IRQ14
707 * 1111 : IRQ15
708 *
709 * We avoid using a reserved value for disabled links, hence the
710 * choice of IRQ15 for that case.
711 *
712 * References:
713 *
714 * "486 Green PC VESA/ISA/PCI Chipset, SiS 85C496/497", Rev 3.0,
715 * Silicon Integrated Systems Corp., July 1995
716 */
717
718#define PCI_SIS497_INTA_TO_IRQ_LINK 0xc0u
719
720#define PIRQ_SIS497_IRQ_MASK 0x0fu
721#define PIRQ_SIS497_IRQ_ENABLE 0x80u
722
723static int pirq_sis497_get(struct pci_dev *router, struct pci_dev *dev,
724 int pirq)
725{
726 int reg;
727 u8 x;
728
729 reg = pirq;
730 if (reg >= 1 && reg <= 4)
731 reg += PCI_SIS497_INTA_TO_IRQ_LINK - 1;
732
733 pci_read_config_byte(dev: router, where: reg, val: &x);
734 return (x & PIRQ_SIS497_IRQ_ENABLE) ? (x & PIRQ_SIS497_IRQ_MASK) : 0;
735}
736
737static int pirq_sis497_set(struct pci_dev *router, struct pci_dev *dev,
738 int pirq, int irq)
739{
740 int reg;
741 u8 x;
742
743 reg = pirq;
744 if (reg >= 1 && reg <= 4)
745 reg += PCI_SIS497_INTA_TO_IRQ_LINK - 1;
746
747 pci_read_config_byte(dev: router, where: reg, val: &x);
748 x &= ~(PIRQ_SIS497_IRQ_MASK | PIRQ_SIS497_IRQ_ENABLE);
749 x |= irq ? (PIRQ_SIS497_IRQ_ENABLE | irq) : PIRQ_SIS497_IRQ_MASK;
750 pci_write_config_byte(dev: router, where: reg, val: x);
751 return 1;
752}
753
754/*
755 * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
756 * We have to deal with the following issues here:
757 * - vendors have different ideas about the meaning of link values
758 * - some onboard devices (integrated in the chipset) have special
759 * links and are thus routed differently (i.e. not via PCI INTA-INTD)
760 * - different revision of the router have a different layout for
761 * the routing registers, particularly for the onchip devices
762 *
763 * For all routing registers the common thing is we have one byte
764 * per routeable link which is defined as:
765 * bit 7 IRQ mapping enabled (0) or disabled (1)
766 * bits [6:4] reserved (sometimes used for onchip devices)
767 * bits [3:0] IRQ to map to
768 * allowed: 3-7, 9-12, 14-15
769 * reserved: 0, 1, 2, 8, 13
770 *
771 * The config-space registers located at 0x41/0x42/0x43/0x44 are
772 * always used to route the normal PCI INT A/B/C/D respectively.
773 * Apparently there are systems implementing PCI routing table using
774 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
775 * We try our best to handle both link mappings.
776 *
777 * Currently (2003-05-21) it appears most SiS chipsets follow the
778 * definition of routing registers from the SiS-5595 southbridge.
779 * According to the SiS 5595 datasheets the revision id's of the
780 * router (ISA-bridge) should be 0x01 or 0xb0.
781 *
782 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
783 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
784 * They seem to work with the current routing code. However there is
785 * some concern because of the two USB-OHCI HCs (original SiS 5595
786 * had only one). YMMV.
787 *
788 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
789 *
790 * 0x61: IDEIRQ:
791 * bits [6:5] must be written 01
792 * bit 4 channel-select primary (0), secondary (1)
793 *
794 * 0x62: USBIRQ:
795 * bit 6 OHCI function disabled (0), enabled (1)
796 *
797 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
798 *
799 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
800 *
801 * We support USBIRQ (in addition to INTA-INTD) and keep the
802 * IDE, ACPI and DAQ routing untouched as set by the BIOS.
803 *
804 * Currently the only reported exception is the new SiS 65x chipset
805 * which includes the SiS 69x southbridge. Here we have the 85C503
806 * router revision 0x04 and there are changes in the register layout
807 * mostly related to the different USB HCs with USB 2.0 support.
808 *
809 * Onchip routing for router rev-id 0x04 (try-and-error observation)
810 *
811 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
812 * bit 6-4 are probably unused, not like 5595
813 */
814
815#define PIRQ_SIS503_IRQ_MASK 0x0f
816#define PIRQ_SIS503_IRQ_DISABLE 0x80
817#define PIRQ_SIS503_USB_ENABLE 0x40
818
819static int pirq_sis503_get(struct pci_dev *router, struct pci_dev *dev,
820 int pirq)
821{
822 u8 x;
823 int reg;
824
825 reg = pirq;
826 if (reg >= 0x01 && reg <= 0x04)
827 reg += 0x40;
828 pci_read_config_byte(dev: router, where: reg, val: &x);
829 return (x & PIRQ_SIS503_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS503_IRQ_MASK);
830}
831
832static int pirq_sis503_set(struct pci_dev *router, struct pci_dev *dev,
833 int pirq, int irq)
834{
835 u8 x;
836 int reg;
837
838 reg = pirq;
839 if (reg >= 0x01 && reg <= 0x04)
840 reg += 0x40;
841 pci_read_config_byte(dev: router, where: reg, val: &x);
842 x &= ~(PIRQ_SIS503_IRQ_MASK | PIRQ_SIS503_IRQ_DISABLE);
843 x |= irq ? irq : PIRQ_SIS503_IRQ_DISABLE;
844 pci_write_config_byte(dev: router, where: reg, val: x);
845 return 1;
846}
847
848
849/*
850 * VLSI: nibble offset 0x74 - educated guess due to routing table and
851 * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
852 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
853 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
854 * for the busbridge to the docking station.
855 */
856
857static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
858{
859 WARN_ON_ONCE(pirq >= 9);
860 if (pirq > 8) {
861 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
862 return 0;
863 }
864 return read_config_nybble(router, offset: 0x74, nr: pirq-1);
865}
866
867static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
868{
869 WARN_ON_ONCE(pirq >= 9);
870 if (pirq > 8) {
871 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
872 return 0;
873 }
874 write_config_nybble(router, offset: 0x74, nr: pirq-1, val: irq);
875 return 1;
876}
877
878/*
879 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
880 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
881 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
882 * register is a straight binary coding of desired PIC IRQ (low nibble).
883 *
884 * The 'link' value in the PIRQ table is already in the correct format
885 * for the Index register. There are some special index values:
886 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
887 * and 0x03 for SMBus.
888 */
889static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
890{
891 outb(value: pirq, port: 0xc00);
892 return inb(port: 0xc01) & 0xf;
893}
894
895static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev,
896 int pirq, int irq)
897{
898 outb(value: pirq, port: 0xc00);
899 outb(value: irq, port: 0xc01);
900 return 1;
901}
902
903/* Support for AMD756 PCI IRQ Routing
904 * Jhon H. Caicedo <jhcaiced@osso.org.co>
905 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
906 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
907 * The AMD756 pirq rules are nibble-based
908 * offset 0x56 0-3 PIRQA 4-7 PIRQB
909 * offset 0x57 0-3 PIRQC 4-7 PIRQD
910 */
911static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
912{
913 u8 irq;
914 irq = 0;
915 if (pirq <= 4)
916 irq = read_config_nybble(router, offset: 0x56, nr: pirq - 1);
917 dev_info(&dev->dev,
918 "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n",
919 dev->vendor, dev->device, pirq, irq);
920 return irq;
921}
922
923static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
924{
925 dev_info(&dev->dev,
926 "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n",
927 dev->vendor, dev->device, pirq, irq);
928 if (pirq <= 4)
929 write_config_nybble(router, offset: 0x56, nr: pirq - 1, val: irq);
930 return 1;
931}
932
933/*
934 * PicoPower PT86C523
935 */
936static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
937{
938 outb(value: 0x10 + ((pirq - 1) >> 1), port: 0x24);
939 return ((pirq - 1) & 1) ? (inb(port: 0x26) >> 4) : (inb(port: 0x26) & 0xf);
940}
941
942static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
943 int irq)
944{
945 unsigned int x;
946 outb(value: 0x10 + ((pirq - 1) >> 1), port: 0x24);
947 x = inb(port: 0x26);
948 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq));
949 outb(value: x, port: 0x26);
950 return 1;
951}
952
953#ifdef CONFIG_PCI_BIOS
954
955static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
956{
957 struct pci_dev *bridge;
958 int pin = pci_get_interrupt_pin(dev, &bridge);
959 return pcibios_set_irq_routing(bridge, pin - 1, irq);
960}
961
962#endif
963
964static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
965{
966 static struct pci_device_id __initdata pirq_440gx[] = {
967 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
968 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
969 { },
970 };
971
972 /* 440GX has a proprietary PIRQ router -- don't use it */
973 if (pci_dev_present(ids: pirq_440gx))
974 return 0;
975
976 switch (device) {
977 case PCI_DEVICE_ID_INTEL_82375:
978 r->name = "PCEB/ESC";
979 r->get = pirq_esc_get;
980 r->set = pirq_esc_set;
981 return 1;
982 case PCI_DEVICE_ID_INTEL_82371FB_0:
983 case PCI_DEVICE_ID_INTEL_82371SB_0:
984 case PCI_DEVICE_ID_INTEL_82371AB_0:
985 case PCI_DEVICE_ID_INTEL_82371MX:
986 case PCI_DEVICE_ID_INTEL_82443MX_0:
987 case PCI_DEVICE_ID_INTEL_82801AA_0:
988 case PCI_DEVICE_ID_INTEL_82801AB_0:
989 case PCI_DEVICE_ID_INTEL_82801BA_0:
990 case PCI_DEVICE_ID_INTEL_82801BA_10:
991 case PCI_DEVICE_ID_INTEL_82801CA_0:
992 case PCI_DEVICE_ID_INTEL_82801CA_12:
993 case PCI_DEVICE_ID_INTEL_82801DB_0:
994 case PCI_DEVICE_ID_INTEL_82801E_0:
995 case PCI_DEVICE_ID_INTEL_82801EB_0:
996 case PCI_DEVICE_ID_INTEL_ESB_1:
997 case PCI_DEVICE_ID_INTEL_ICH6_0:
998 case PCI_DEVICE_ID_INTEL_ICH6_1:
999 case PCI_DEVICE_ID_INTEL_ICH7_0:
1000 case PCI_DEVICE_ID_INTEL_ICH7_1:
1001 case PCI_DEVICE_ID_INTEL_ICH7_30:
1002 case PCI_DEVICE_ID_INTEL_ICH7_31:
1003 case PCI_DEVICE_ID_INTEL_TGP_LPC:
1004 case PCI_DEVICE_ID_INTEL_ESB2_0:
1005 case PCI_DEVICE_ID_INTEL_ICH8_0:
1006 case PCI_DEVICE_ID_INTEL_ICH8_1:
1007 case PCI_DEVICE_ID_INTEL_ICH8_2:
1008 case PCI_DEVICE_ID_INTEL_ICH8_3:
1009 case PCI_DEVICE_ID_INTEL_ICH8_4:
1010 case PCI_DEVICE_ID_INTEL_ICH9_0:
1011 case PCI_DEVICE_ID_INTEL_ICH9_1:
1012 case PCI_DEVICE_ID_INTEL_ICH9_2:
1013 case PCI_DEVICE_ID_INTEL_ICH9_3:
1014 case PCI_DEVICE_ID_INTEL_ICH9_4:
1015 case PCI_DEVICE_ID_INTEL_ICH9_5:
1016 case PCI_DEVICE_ID_INTEL_EP80579_0:
1017 case PCI_DEVICE_ID_INTEL_ICH10_0:
1018 case PCI_DEVICE_ID_INTEL_ICH10_1:
1019 case PCI_DEVICE_ID_INTEL_ICH10_2:
1020 case PCI_DEVICE_ID_INTEL_ICH10_3:
1021 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0:
1022 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1:
1023 r->name = "PIIX/ICH";
1024 r->get = pirq_piix_get;
1025 r->set = pirq_piix_set;
1026 return 1;
1027 case PCI_DEVICE_ID_INTEL_82425:
1028 r->name = "PSC/IB";
1029 r->get = pirq_ib_get;
1030 r->set = pirq_ib_set;
1031 return 1;
1032 }
1033
1034 if ((device >= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN &&
1035 device <= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX)
1036 || (device >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
1037 device <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX)
1038 || (device >= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN &&
1039 device <= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX)
1040 || (device >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
1041 device <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) {
1042 r->name = "PIIX/ICH";
1043 r->get = pirq_piix_get;
1044 r->set = pirq_piix_set;
1045 return 1;
1046 }
1047
1048 return 0;
1049}
1050
1051static __init int via_router_probe(struct irq_router *r,
1052 struct pci_dev *router, u16 device)
1053{
1054 /* FIXME: We should move some of the quirk fixup stuff here */
1055
1056 /*
1057 * workarounds for some buggy BIOSes
1058 */
1059 if (device == PCI_DEVICE_ID_VIA_82C586_0) {
1060 switch (router->device) {
1061 case PCI_DEVICE_ID_VIA_82C686:
1062 /*
1063 * Asus k7m bios wrongly reports 82C686A
1064 * as 586-compatible
1065 */
1066 device = PCI_DEVICE_ID_VIA_82C686;
1067 break;
1068 case PCI_DEVICE_ID_VIA_8235:
1069 /**
1070 * Asus a7v-x bios wrongly reports 8235
1071 * as 586-compatible
1072 */
1073 device = PCI_DEVICE_ID_VIA_8235;
1074 break;
1075 case PCI_DEVICE_ID_VIA_8237:
1076 /**
1077 * Asus a7v600 bios wrongly reports 8237
1078 * as 586-compatible
1079 */
1080 device = PCI_DEVICE_ID_VIA_8237;
1081 break;
1082 }
1083 }
1084
1085 switch (device) {
1086 case PCI_DEVICE_ID_VIA_82C586_0:
1087 r->name = "VIA";
1088 r->get = pirq_via586_get;
1089 r->set = pirq_via586_set;
1090 return 1;
1091 case PCI_DEVICE_ID_VIA_82C596:
1092 case PCI_DEVICE_ID_VIA_82C686:
1093 case PCI_DEVICE_ID_VIA_8231:
1094 case PCI_DEVICE_ID_VIA_8233A:
1095 case PCI_DEVICE_ID_VIA_8235:
1096 case PCI_DEVICE_ID_VIA_8237:
1097 /* FIXME: add new ones for 8233/5 */
1098 r->name = "VIA";
1099 r->get = pirq_via_get;
1100 r->set = pirq_via_set;
1101 return 1;
1102 }
1103 return 0;
1104}
1105
1106static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1107{
1108 switch (device) {
1109 case PCI_DEVICE_ID_VLSI_82C534:
1110 r->name = "VLSI 82C534";
1111 r->get = pirq_vlsi_get;
1112 r->set = pirq_vlsi_set;
1113 return 1;
1114 }
1115 return 0;
1116}
1117
1118
1119static __init int serverworks_router_probe(struct irq_router *r,
1120 struct pci_dev *router, u16 device)
1121{
1122 switch (device) {
1123 case PCI_DEVICE_ID_SERVERWORKS_OSB4:
1124 case PCI_DEVICE_ID_SERVERWORKS_CSB5:
1125 r->name = "ServerWorks";
1126 r->get = pirq_serverworks_get;
1127 r->set = pirq_serverworks_set;
1128 return 1;
1129 }
1130 return 0;
1131}
1132
1133static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1134{
1135 switch (device) {
1136 case PCI_DEVICE_ID_SI_496:
1137 r->name = "SiS85C497";
1138 r->get = pirq_sis497_get;
1139 r->set = pirq_sis497_set;
1140 return 1;
1141 case PCI_DEVICE_ID_SI_503:
1142 r->name = "SiS85C503";
1143 r->get = pirq_sis503_get;
1144 r->set = pirq_sis503_set;
1145 return 1;
1146 }
1147 return 0;
1148}
1149
1150static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1151{
1152 switch (device) {
1153 case PCI_DEVICE_ID_CYRIX_5520:
1154 r->name = "NatSemi";
1155 r->get = pirq_cyrix_get;
1156 r->set = pirq_cyrix_set;
1157 return 1;
1158 }
1159 return 0;
1160}
1161
1162static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1163{
1164 switch (device) {
1165 case PCI_DEVICE_ID_OPTI_82C700:
1166 r->name = "OPTI";
1167 r->get = pirq_opti_get;
1168 r->set = pirq_opti_set;
1169 return 1;
1170 }
1171 return 0;
1172}
1173
1174static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1175{
1176 switch (device) {
1177 case PCI_DEVICE_ID_ITE_IT8330G_0:
1178 r->name = "ITE";
1179 r->get = pirq_ite_get;
1180 r->set = pirq_ite_set;
1181 return 1;
1182 }
1183 return 0;
1184}
1185
1186static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1187{
1188 switch (device) {
1189 case PCI_DEVICE_ID_AL_M1489:
1190 r->name = "FinALi";
1191 r->get = pirq_finali_get;
1192 r->set = pirq_finali_set;
1193 r->lvl = pirq_finali_lvl;
1194 return 1;
1195 case PCI_DEVICE_ID_AL_M1533:
1196 case PCI_DEVICE_ID_AL_M1563:
1197 r->name = "ALI";
1198 r->get = pirq_ali_get;
1199 r->set = pirq_ali_set;
1200 return 1;
1201 }
1202 return 0;
1203}
1204
1205static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1206{
1207 switch (device) {
1208 case PCI_DEVICE_ID_AMD_VIPER_740B:
1209 r->name = "AMD756";
1210 break;
1211 case PCI_DEVICE_ID_AMD_VIPER_7413:
1212 r->name = "AMD766";
1213 break;
1214 case PCI_DEVICE_ID_AMD_VIPER_7443:
1215 r->name = "AMD768";
1216 break;
1217 default:
1218 return 0;
1219 }
1220 r->get = pirq_amd756_get;
1221 r->set = pirq_amd756_set;
1222 return 1;
1223}
1224
1225static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1226{
1227 switch (device) {
1228 case PCI_DEVICE_ID_PICOPOWER_PT86C523:
1229 r->name = "PicoPower PT86C523";
1230 r->get = pirq_pico_get;
1231 r->set = pirq_pico_set;
1232 return 1;
1233
1234 case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP:
1235 r->name = "PicoPower PT86C523 rev. BB+";
1236 r->get = pirq_pico_get;
1237 r->set = pirq_pico_set;
1238 return 1;
1239 }
1240 return 0;
1241}
1242
1243static __initdata struct irq_router_handler pirq_routers[] = {
1244 { PCI_VENDOR_ID_INTEL, intel_router_probe },
1245 { PCI_VENDOR_ID_AL, ali_router_probe },
1246 { PCI_VENDOR_ID_ITE, ite_router_probe },
1247 { PCI_VENDOR_ID_VIA, via_router_probe },
1248 { PCI_VENDOR_ID_OPTI, opti_router_probe },
1249 { PCI_VENDOR_ID_SI, sis_router_probe },
1250 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
1251 { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
1252 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
1253 { PCI_VENDOR_ID_AMD, amd_router_probe },
1254 { PCI_VENDOR_ID_PICOPOWER, pico_router_probe },
1255 /* Someone with docs needs to add the ATI Radeon IGP */
1256 { 0, NULL }
1257};
1258static struct irq_router pirq_router;
1259static struct pci_dev *pirq_router_dev;
1260
1261
1262/*
1263 * FIXME: should we have an option to say "generic for
1264 * chipset" ?
1265 */
1266
1267static bool __init pirq_try_router(struct irq_router *r,
1268 struct irq_routing_table *rt,
1269 struct pci_dev *dev)
1270{
1271 struct irq_router_handler *h;
1272
1273 DBG(KERN_DEBUG "PCI: Trying IRQ router for [%04x:%04x]\n",
1274 dev->vendor, dev->device);
1275
1276 for (h = pirq_routers; h->vendor; h++) {
1277 /* First look for a router match */
1278 if (rt->rtr_vendor == h->vendor &&
1279 h->probe(r, dev, rt->rtr_device))
1280 return true;
1281 /* Fall back to a device match */
1282 if (dev->vendor == h->vendor &&
1283 h->probe(r, dev, dev->device))
1284 return true;
1285 }
1286 return false;
1287}
1288
1289static void __init pirq_find_router(struct irq_router *r)
1290{
1291 struct irq_routing_table *rt = pirq_table;
1292 struct pci_dev *dev;
1293
1294#ifdef CONFIG_PCI_BIOS
1295 if (!rt->signature) {
1296 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
1297 r->set = pirq_bios_set;
1298 r->name = "BIOS";
1299 return;
1300 }
1301#endif
1302
1303 /* Default unless a driver reloads it */
1304 r->name = "default";
1305 r->get = NULL;
1306 r->set = NULL;
1307
1308 DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n",
1309 rt->rtr_vendor, rt->rtr_device);
1310
1311 /* Use any vendor:device provided by the routing table or try all. */
1312 if (rt->rtr_vendor) {
1313 dev = pci_get_domain_bus_and_slot(domain: 0, bus: rt->rtr_bus,
1314 devfn: rt->rtr_devfn);
1315 if (dev && pirq_try_router(r, rt, dev))
1316 pirq_router_dev = dev;
1317 } else {
1318 dev = NULL;
1319 for_each_pci_dev(dev) {
1320 if (pirq_try_router(r, rt, dev)) {
1321 pirq_router_dev = dev;
1322 break;
1323 }
1324 }
1325 }
1326
1327 if (pirq_router_dev)
1328 dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n",
1329 pirq_router.name,
1330 pirq_router_dev->vendor, pirq_router_dev->device);
1331 else
1332 DBG(KERN_DEBUG "PCI: Interrupt router not found at "
1333 "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
1334
1335 /* The device remains referenced for the kernel lifetime */
1336}
1337
1338/*
1339 * We're supposed to match on the PCI device only and not the function,
1340 * but some BIOSes build their tables with the PCI function included
1341 * for motherboard devices, so if a complete match is found, then give
1342 * it precedence over a slot match.
1343 */
1344static struct irq_info *pirq_get_dev_info(struct pci_dev *dev)
1345{
1346 struct irq_routing_table *rt = pirq_table;
1347 int entries = (rt->size - sizeof(struct irq_routing_table)) /
1348 sizeof(struct irq_info);
1349 struct irq_info *slotinfo = NULL;
1350 struct irq_info *info;
1351
1352 for (info = rt->slots; entries--; info++)
1353 if (info->bus == dev->bus->number) {
1354 if (info->devfn == dev->devfn)
1355 return info;
1356 if (!slotinfo &&
1357 PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
1358 slotinfo = info;
1359 }
1360 return slotinfo;
1361}
1362
1363/*
1364 * Buses behind bridges are typically not listed in the PIRQ routing table.
1365 * Do the usual dance then and walk the tree of bridges up adjusting the
1366 * pin number accordingly on the way until the originating root bus device
1367 * has been reached and then use its routing information.
1368 */
1369static struct irq_info *pirq_get_info(struct pci_dev *dev, u8 *pin)
1370{
1371 struct pci_dev *temp_dev = dev;
1372 struct irq_info *info;
1373 u8 temp_pin = *pin;
1374 u8 dpin = temp_pin;
1375
1376 info = pirq_get_dev_info(dev);
1377 while (!info && temp_dev->bus->parent) {
1378 struct pci_dev *bridge = temp_dev->bus->self;
1379
1380 temp_pin = pci_swizzle_interrupt_pin(dev: temp_dev, pin: temp_pin);
1381 info = pirq_get_dev_info(dev: bridge);
1382 if (info)
1383 dev_warn(&dev->dev,
1384 "using bridge %s INT %c to get INT %c\n",
1385 pci_name(bridge),
1386 'A' + temp_pin - 1, 'A' + dpin - 1);
1387
1388 temp_dev = bridge;
1389 }
1390 *pin = temp_pin;
1391 return info;
1392}
1393
1394static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
1395{
1396 struct irq_info *info;
1397 int i, pirq, newirq;
1398 u8 dpin, pin;
1399 int irq = 0;
1400 u32 mask;
1401 struct irq_router *r = &pirq_router;
1402 struct pci_dev *dev2 = NULL;
1403 char *msg = NULL;
1404
1405 /* Find IRQ pin */
1406 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, val: &dpin);
1407 if (!dpin) {
1408 dev_dbg(&dev->dev, "no interrupt pin\n");
1409 return 0;
1410 }
1411
1412 if (io_apic_assign_pci_irqs)
1413 return 0;
1414
1415 /* Find IRQ routing entry */
1416
1417 if (!pirq_table)
1418 return 0;
1419
1420 pin = dpin;
1421 info = pirq_get_info(dev, pin: &pin);
1422 if (!info) {
1423 dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n",
1424 'A' + dpin - 1);
1425 return 0;
1426 }
1427 pirq = info->irq[pin - 1].link;
1428 mask = info->irq[pin - 1].bitmap;
1429 if (!pirq) {
1430 dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + dpin - 1);
1431 return 0;
1432 }
1433 dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x",
1434 'A' + dpin - 1, pirq, mask, pirq_table->exclusive_irqs);
1435 mask &= pcibios_irq_mask;
1436
1437 /* Work around broken HP Pavilion Notebooks which assign USB to
1438 IRQ 9 even though it is actually wired to IRQ 11 */
1439
1440 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
1441 dev->irq = 11;
1442 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, val: 11);
1443 r->set(pirq_router_dev, dev, pirq, 11);
1444 }
1445
1446 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
1447 if (acer_tm360_irqrouting && dev->irq == 11 &&
1448 dev->vendor == PCI_VENDOR_ID_O2) {
1449 pirq = 0x68;
1450 mask = 0x400;
1451 dev->irq = r->get(pirq_router_dev, dev, pirq);
1452 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, val: dev->irq);
1453 }
1454
1455 /*
1456 * Find the best IRQ to assign: use the one
1457 * reported by the device if possible.
1458 */
1459 newirq = dev->irq;
1460 if (newirq && !((1 << newirq) & mask)) {
1461 if (pci_probe & PCI_USE_PIRQ_MASK)
1462 newirq = 0;
1463 else
1464 dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask "
1465 "%#x; try pci=usepirqmask\n", newirq, mask);
1466 }
1467 if (!newirq && assign) {
1468 for (i = 0; i < 16; i++) {
1469 if (!(mask & (1 << i)))
1470 continue;
1471 if (pirq_penalty[i] < pirq_penalty[newirq] &&
1472 can_request_irq(irq: i, IRQF_SHARED))
1473 newirq = i;
1474 }
1475 }
1476 dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + dpin - 1, newirq);
1477
1478 /* Check if it is hardcoded */
1479 if ((pirq & 0xf0) == 0xf0) {
1480 irq = pirq & 0xf;
1481 msg = "hardcoded";
1482 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
1483 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) {
1484 msg = "found";
1485 if (r->lvl)
1486 r->lvl(pirq_router_dev, dev, pirq, irq);
1487 else
1488 elcr_set_level_irq(irq);
1489 } else if (newirq && r->set &&
1490 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
1491 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
1492 if (r->lvl)
1493 r->lvl(pirq_router_dev, dev, pirq, newirq);
1494 else
1495 elcr_set_level_irq(irq: newirq);
1496 msg = "assigned";
1497 irq = newirq;
1498 }
1499 }
1500
1501 if (!irq) {
1502 if (newirq && mask == (1 << newirq)) {
1503 msg = "guessed";
1504 irq = newirq;
1505 } else {
1506 dev_dbg(&dev->dev, "can't route interrupt\n");
1507 return 0;
1508 }
1509 }
1510 dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n",
1511 msg, 'A' + dpin - 1, irq);
1512
1513 /* Update IRQ for all devices with the same pirq value */
1514 for_each_pci_dev(dev2) {
1515 pci_read_config_byte(dev: dev2, PCI_INTERRUPT_PIN, val: &dpin);
1516 if (!dpin)
1517 continue;
1518
1519 pin = dpin;
1520 info = pirq_get_info(dev: dev2, pin: &pin);
1521 if (!info)
1522 continue;
1523 if (info->irq[pin - 1].link == pirq) {
1524 /*
1525 * We refuse to override the dev->irq
1526 * information. Give a warning!
1527 */
1528 if (dev2->irq && dev2->irq != irq && \
1529 (!(pci_probe & PCI_USE_PIRQ_MASK) || \
1530 ((1 << dev2->irq) & mask))) {
1531#ifndef CONFIG_PCI_MSI
1532 dev_info(&dev2->dev, "IRQ routing conflict: "
1533 "have IRQ %d, want IRQ %d\n",
1534 dev2->irq, irq);
1535#endif
1536 continue;
1537 }
1538 dev2->irq = irq;
1539 pirq_penalty[irq]++;
1540 if (dev != dev2)
1541 dev_info(&dev->dev, "sharing IRQ %d with %s\n",
1542 irq, pci_name(dev2));
1543 }
1544 }
1545 return 1;
1546}
1547
1548void __init pcibios_fixup_irqs(void)
1549{
1550 struct pci_dev *dev = NULL;
1551 u8 pin;
1552
1553 DBG(KERN_DEBUG "PCI: IRQ fixup\n");
1554 for_each_pci_dev(dev) {
1555 /*
1556 * If the BIOS has set an out of range IRQ number, just
1557 * ignore it. Also keep track of which IRQ's are
1558 * already in use.
1559 */
1560 if (dev->irq >= 16) {
1561 dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq);
1562 dev->irq = 0;
1563 }
1564 /*
1565 * If the IRQ is already assigned to a PCI device,
1566 * ignore its ISA use penalty
1567 */
1568 if (pirq_penalty[dev->irq] >= 100 &&
1569 pirq_penalty[dev->irq] < 100000)
1570 pirq_penalty[dev->irq] = 0;
1571 pirq_penalty[dev->irq]++;
1572 }
1573
1574 if (io_apic_assign_pci_irqs)
1575 return;
1576
1577 dev = NULL;
1578 for_each_pci_dev(dev) {
1579 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, val: &pin);
1580 if (!pin)
1581 continue;
1582
1583 /*
1584 * Still no IRQ? Try to lookup one...
1585 */
1586 if (!dev->irq)
1587 pcibios_lookup_irq(dev, assign: 0);
1588 }
1589}
1590
1591/*
1592 * Work around broken HP Pavilion Notebooks which assign USB to
1593 * IRQ 9 even though it is actually wired to IRQ 11
1594 */
1595static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d)
1596{
1597 if (!broken_hp_bios_irq9) {
1598 broken_hp_bios_irq9 = 1;
1599 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1600 d->ident);
1601 }
1602 return 0;
1603}
1604
1605/*
1606 * Work around broken Acer TravelMate 360 Notebooks which assign
1607 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
1608 */
1609static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d)
1610{
1611 if (!acer_tm360_irqrouting) {
1612 acer_tm360_irqrouting = 1;
1613 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1614 d->ident);
1615 }
1616 return 0;
1617}
1618
1619static const struct dmi_system_id pciirq_dmi_table[] __initconst = {
1620 {
1621 .callback = fix_broken_hp_bios_irq9,
1622 .ident = "HP Pavilion N5400 Series Laptop",
1623 .matches = {
1624 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1625 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
1626 DMI_MATCH(DMI_PRODUCT_VERSION,
1627 "HP Pavilion Notebook Model GE"),
1628 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
1629 },
1630 },
1631 {
1632 .callback = fix_acer_tm360_irqrouting,
1633 .ident = "Acer TravelMate 36x Laptop",
1634 .matches = {
1635 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1636 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
1637 },
1638 },
1639 { }
1640};
1641
1642void __init pcibios_irq_init(void)
1643{
1644 struct irq_routing_table *rtable = NULL;
1645
1646 DBG(KERN_DEBUG "PCI: IRQ init\n");
1647
1648 if (raw_pci_ops == NULL)
1649 return;
1650
1651 dmi_check_system(list: pciirq_dmi_table);
1652
1653 pirq_table = pirq_find_routing_table();
1654
1655#ifdef CONFIG_PCI_BIOS
1656 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) {
1657 pirq_table = pcibios_get_irq_routing_table();
1658 rtable = pirq_table;
1659 }
1660#endif
1661 if (pirq_table) {
1662 pirq_peer_trick();
1663 pirq_find_router(r: &pirq_router);
1664 if (pirq_table->exclusive_irqs) {
1665 int i;
1666 for (i = 0; i < 16; i++)
1667 if (!(pirq_table->exclusive_irqs & (1 << i)))
1668 pirq_penalty[i] += 100;
1669 }
1670 /*
1671 * If we're using the I/O APIC, avoid using the PCI IRQ
1672 * routing table
1673 */
1674 if (io_apic_assign_pci_irqs) {
1675 kfree(objp: rtable);
1676 pirq_table = NULL;
1677 }
1678 }
1679
1680 x86_init.pci.fixup_irqs();
1681
1682 if (io_apic_assign_pci_irqs && pci_routeirq) {
1683 struct pci_dev *dev = NULL;
1684 /*
1685 * PCI IRQ routing is set up by pci_enable_device(), but we
1686 * also do it here in case there are still broken drivers that
1687 * don't use pci_enable_device().
1688 */
1689 printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n");
1690 for_each_pci_dev(dev)
1691 pirq_enable_irq(dev);
1692 }
1693}
1694
1695static void pirq_penalize_isa_irq(int irq, int active)
1696{
1697 /*
1698 * If any ISAPnP device reports an IRQ in its list of possible
1699 * IRQ's, we try to avoid assigning it to PCI devices.
1700 */
1701 if (irq < 16) {
1702 if (active)
1703 pirq_penalty[irq] += 1000;
1704 else
1705 pirq_penalty[irq] += 100;
1706 }
1707}
1708
1709void pcibios_penalize_isa_irq(int irq, int active)
1710{
1711#ifdef CONFIG_ACPI
1712 if (!acpi_noirq)
1713 acpi_penalize_isa_irq(irq, active);
1714 else
1715#endif
1716 pirq_penalize_isa_irq(irq, active);
1717}
1718
1719static int pirq_enable_irq(struct pci_dev *dev)
1720{
1721 u8 pin = 0;
1722
1723 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, val: &pin);
1724 if (pin && !pcibios_lookup_irq(dev, assign: 1)) {
1725 char *msg = "";
1726
1727 if (!io_apic_assign_pci_irqs && dev->irq)
1728 return 0;
1729
1730 if (io_apic_assign_pci_irqs) {
1731#ifdef CONFIG_X86_IO_APIC
1732 struct pci_dev *temp_dev;
1733 int irq;
1734
1735 if (dev->irq_managed && dev->irq > 0)
1736 return 0;
1737
1738 irq = IO_APIC_get_PCI_irq_vector(bus: dev->bus->number,
1739 PCI_SLOT(dev->devfn), pin: pin - 1);
1740 /*
1741 * Busses behind bridges are typically not listed in the MP-table.
1742 * In this case we have to look up the IRQ based on the parent bus,
1743 * parent slot, and pin number. The SMP code detects such bridged
1744 * busses itself so we should get into this branch reliably.
1745 */
1746 temp_dev = dev;
1747 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1748 struct pci_dev *bridge = dev->bus->self;
1749
1750 pin = pci_swizzle_interrupt_pin(dev, pin);
1751 irq = IO_APIC_get_PCI_irq_vector(bus: bridge->bus->number,
1752 PCI_SLOT(bridge->devfn),
1753 pin: pin - 1);
1754 if (irq >= 0)
1755 dev_warn(&dev->dev, "using bridge %s "
1756 "INT %c to get IRQ %d\n",
1757 pci_name(bridge), 'A' + pin - 1,
1758 irq);
1759 dev = bridge;
1760 }
1761 dev = temp_dev;
1762 if (irq >= 0) {
1763 dev->irq_managed = 1;
1764 dev->irq = irq;
1765 dev_info(&dev->dev, "PCI->APIC IRQ transform: "
1766 "INT %c -> IRQ %d\n", 'A' + pin - 1, irq);
1767 return 0;
1768 } else
1769 msg = "; probably buggy MP table";
1770#endif
1771 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1772 msg = "";
1773 else
1774 msg = "; please try using pci=biosirq";
1775
1776 /*
1777 * With IDE legacy devices the IRQ lookup failure is not
1778 * a problem..
1779 */
1780 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE &&
1781 !(dev->class & 0x5))
1782 return 0;
1783
1784 dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n",
1785 'A' + pin - 1, msg);
1786 }
1787 return 0;
1788}
1789
1790bool mp_should_keep_irq(struct device *dev)
1791{
1792 if (dev->power.is_prepared)
1793 return true;
1794#ifdef CONFIG_PM
1795 if (dev->power.runtime_status == RPM_SUSPENDING)
1796 return true;
1797#endif
1798
1799 return false;
1800}
1801
1802static void pirq_disable_irq(struct pci_dev *dev)
1803{
1804 if (io_apic_assign_pci_irqs && !mp_should_keep_irq(dev: &dev->dev) &&
1805 dev->irq_managed && dev->irq) {
1806 mp_unmap_irq(irq: dev->irq);
1807 dev->irq = 0;
1808 dev->irq_managed = 0;
1809 }
1810}
1811