1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ahci.c - AHCI SATA support
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/dma-mapping.h>
26#include <linux/device.h>
27#include <linux/dmi.h>
28#include <linux/gfp.h>
29#include <scsi/scsi_host.h>
30#include <scsi/scsi_cmnd.h>
31#include <linux/libata.h>
32#include <linux/ahci-remap.h>
33#include <linux/io-64-nonatomic-lo-hi.h>
34#include "ahci.h"
35
36#define DRV_NAME "ahci"
37#define DRV_VERSION "3.0"
38
39enum {
40 AHCI_PCI_BAR_STA2X11 = 0,
41 AHCI_PCI_BAR_CAVIUM = 0,
42 AHCI_PCI_BAR_LOONGSON = 0,
43 AHCI_PCI_BAR_ENMOTUS = 2,
44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
45 AHCI_PCI_BAR_STANDARD = 5,
46};
47
48enum board_ids {
49 /* board IDs by feature in alphabetical order */
50 board_ahci,
51 board_ahci_43bit_dma,
52 board_ahci_ign_iferr,
53 board_ahci_no_debounce_delay,
54 board_ahci_no_msi,
55 /*
56 * board_ahci_pcs_quirk is for legacy Intel platforms.
57 * Modern Intel platforms should use board_ahci instead.
58 * (Some modern Intel platforms might have been added with
59 * board_ahci_pcs_quirk, however, we cannot change them to board_ahci
60 * without testing that the platform actually works without the quirk.)
61 */
62 board_ahci_pcs_quirk,
63 board_ahci_pcs_quirk_no_devslp,
64 board_ahci_pcs_quirk_no_sntf,
65 board_ahci_yes_fbs,
66 board_ahci_yes_fbs_atapi_dma,
67
68 /* board IDs for specific chipsets in alphabetical order */
69 board_ahci_al,
70 board_ahci_avn,
71 board_ahci_mcp65,
72 board_ahci_mcp77,
73 board_ahci_mcp89,
74 board_ahci_mv,
75 board_ahci_sb600,
76 board_ahci_sb700, /* for SB700 and SB800 */
77 board_ahci_vt8251,
78
79 /* aliases */
80 board_ahci_mcp_linux = board_ahci_mcp65,
81 board_ahci_mcp67 = board_ahci_mcp65,
82 board_ahci_mcp73 = board_ahci_mcp65,
83 board_ahci_mcp79 = board_ahci_mcp77,
84};
85
86static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
87static void ahci_remove_one(struct pci_dev *dev);
88static void ahci_shutdown_one(struct pci_dev *dev);
89static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
90static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
91 unsigned long deadline);
92static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
94static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
95static bool is_mcp89_apple(struct pci_dev *pdev);
96static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
97 unsigned long deadline);
98#ifdef CONFIG_PM
99static int ahci_pci_device_runtime_suspend(struct device *dev);
100static int ahci_pci_device_runtime_resume(struct device *dev);
101#ifdef CONFIG_PM_SLEEP
102static int ahci_pci_device_suspend(struct device *dev);
103static int ahci_pci_device_resume(struct device *dev);
104#endif
105#endif /* CONFIG_PM */
106
107static const struct scsi_host_template ahci_sht = {
108 AHCI_SHT("ahci"),
109};
110
111static struct ata_port_operations ahci_vt8251_ops = {
112 .inherits = &ahci_ops,
113 .reset.hardreset = ahci_vt8251_hardreset,
114};
115
116static struct ata_port_operations ahci_p5wdh_ops = {
117 .inherits = &ahci_ops,
118 .reset.hardreset = ahci_p5wdh_hardreset,
119};
120
121static struct ata_port_operations ahci_avn_ops = {
122 .inherits = &ahci_ops,
123 .reset.hardreset = ahci_avn_hardreset,
124};
125
126static const struct ata_port_info ahci_port_info[] = {
127 /* by features */
128 [board_ahci] = {
129 .flags = AHCI_FLAG_COMMON,
130 .pio_mask = ATA_PIO4,
131 .udma_mask = ATA_UDMA6,
132 .port_ops = &ahci_ops,
133 },
134 [board_ahci_43bit_dma] = {
135 AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY),
136 .flags = AHCI_FLAG_COMMON,
137 .pio_mask = ATA_PIO4,
138 .udma_mask = ATA_UDMA6,
139 .port_ops = &ahci_ops,
140 },
141 [board_ahci_ign_iferr] = {
142 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
143 .flags = AHCI_FLAG_COMMON,
144 .pio_mask = ATA_PIO4,
145 .udma_mask = ATA_UDMA6,
146 .port_ops = &ahci_ops,
147 },
148 [board_ahci_no_debounce_delay] = {
149 .flags = AHCI_FLAG_COMMON,
150 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
151 .pio_mask = ATA_PIO4,
152 .udma_mask = ATA_UDMA6,
153 .port_ops = &ahci_ops,
154 },
155 [board_ahci_no_msi] = {
156 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
157 .flags = AHCI_FLAG_COMMON,
158 .pio_mask = ATA_PIO4,
159 .udma_mask = ATA_UDMA6,
160 .port_ops = &ahci_ops,
161 },
162 [board_ahci_pcs_quirk] = {
163 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK),
164 .flags = AHCI_FLAG_COMMON,
165 .pio_mask = ATA_PIO4,
166 .udma_mask = ATA_UDMA6,
167 .port_ops = &ahci_ops,
168 },
169 [board_ahci_pcs_quirk_no_devslp] = {
170 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK |
171 AHCI_HFLAG_NO_DEVSLP),
172 .flags = AHCI_FLAG_COMMON,
173 .pio_mask = ATA_PIO4,
174 .udma_mask = ATA_UDMA6,
175 .port_ops = &ahci_ops,
176 },
177 [board_ahci_pcs_quirk_no_sntf] = {
178 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK |
179 AHCI_HFLAG_NO_SNTF),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_ops,
184 },
185 [board_ahci_yes_fbs] = {
186 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_ops,
191 },
192 [board_ahci_yes_fbs_atapi_dma] = {
193 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS |
194 AHCI_HFLAG_ATAPI_DMA_QUIRK),
195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_ops,
199 },
200 /* by chipsets */
201 [board_ahci_al] = {
202 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
203 .flags = AHCI_FLAG_COMMON,
204 .pio_mask = ATA_PIO4,
205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_ops,
207 },
208 [board_ahci_avn] = {
209 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK),
210 .flags = AHCI_FLAG_COMMON,
211 .pio_mask = ATA_PIO4,
212 .udma_mask = ATA_UDMA6,
213 .port_ops = &ahci_avn_ops,
214 },
215 [board_ahci_mcp65] = {
216 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
217 AHCI_HFLAG_YES_NCQ),
218 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
219 .pio_mask = ATA_PIO4,
220 .udma_mask = ATA_UDMA6,
221 .port_ops = &ahci_ops,
222 },
223 [board_ahci_mcp77] = {
224 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
225 .flags = AHCI_FLAG_COMMON,
226 .pio_mask = ATA_PIO4,
227 .udma_mask = ATA_UDMA6,
228 .port_ops = &ahci_ops,
229 },
230 [board_ahci_mcp89] = {
231 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
232 .flags = AHCI_FLAG_COMMON,
233 .pio_mask = ATA_PIO4,
234 .udma_mask = ATA_UDMA6,
235 .port_ops = &ahci_ops,
236 },
237 [board_ahci_mv] = {
238 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
239 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
240 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
241 .pio_mask = ATA_PIO4,
242 .udma_mask = ATA_UDMA6,
243 .port_ops = &ahci_ops,
244 },
245 [board_ahci_sb600] = {
246 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
247 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
248 AHCI_HFLAG_32BIT_ONLY),
249 .flags = AHCI_FLAG_COMMON,
250 .pio_mask = ATA_PIO4,
251 .udma_mask = ATA_UDMA6,
252 .port_ops = &ahci_pmp_retry_srst_ops,
253 },
254 [board_ahci_sb700] = { /* for SB700 and SB800 */
255 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
256 .flags = AHCI_FLAG_COMMON,
257 .pio_mask = ATA_PIO4,
258 .udma_mask = ATA_UDMA6,
259 .port_ops = &ahci_pmp_retry_srst_ops,
260 },
261 [board_ahci_vt8251] = {
262 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
263 .flags = AHCI_FLAG_COMMON,
264 .pio_mask = ATA_PIO4,
265 .udma_mask = ATA_UDMA6,
266 .port_ops = &ahci_vt8251_ops,
267 },
268};
269
270static const struct pci_device_id ahci_pci_tbl[] = {
271 /* Intel */
272 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci_pcs_quirk }, /* Comet Lake PCH-H RAID */
273 { PCI_VDEVICE(INTEL, 0x2652), .driver_data: board_ahci_pcs_quirk }, /* ICH6 */
274 { PCI_VDEVICE(INTEL, 0x2653), .driver_data: board_ahci_pcs_quirk }, /* ICH6M */
275 { PCI_VDEVICE(INTEL, 0x27c1), .driver_data: board_ahci_pcs_quirk }, /* ICH7 */
276 { PCI_VDEVICE(INTEL, 0x27c5), .driver_data: board_ahci_pcs_quirk }, /* ICH7M */
277 { PCI_VDEVICE(INTEL, 0x27c3), .driver_data: board_ahci_pcs_quirk }, /* ICH7R */
278 { PCI_VDEVICE(AL, 0x5288), .driver_data: board_ahci_ign_iferr }, /* ULi M5288 */
279 { PCI_VDEVICE(INTEL, 0x2681), .driver_data: board_ahci_pcs_quirk }, /* ESB2 */
280 { PCI_VDEVICE(INTEL, 0x2682), .driver_data: board_ahci_pcs_quirk }, /* ESB2 */
281 { PCI_VDEVICE(INTEL, 0x2683), .driver_data: board_ahci_pcs_quirk }, /* ESB2 */
282 { PCI_VDEVICE(INTEL, 0x27c6), .driver_data: board_ahci_pcs_quirk }, /* ICH7-M DH */
283 { PCI_VDEVICE(INTEL, 0x2821), .driver_data: board_ahci_pcs_quirk }, /* ICH8 */
284 { PCI_VDEVICE(INTEL, 0x2822), .driver_data: board_ahci_pcs_quirk_no_sntf }, /* ICH8/Lewisburg RAID*/
285 { PCI_VDEVICE(INTEL, 0x2824), .driver_data: board_ahci_pcs_quirk }, /* ICH8 */
286 { PCI_VDEVICE(INTEL, 0x2829), .driver_data: board_ahci_pcs_quirk }, /* ICH8M */
287 { PCI_VDEVICE(INTEL, 0x282a), .driver_data: board_ahci_pcs_quirk }, /* ICH8M */
288 { PCI_VDEVICE(INTEL, 0x2922), .driver_data: board_ahci_pcs_quirk }, /* ICH9 */
289 { PCI_VDEVICE(INTEL, 0x2923), .driver_data: board_ahci_pcs_quirk }, /* ICH9 */
290 { PCI_VDEVICE(INTEL, 0x2924), .driver_data: board_ahci_pcs_quirk }, /* ICH9 */
291 { PCI_VDEVICE(INTEL, 0x2925), .driver_data: board_ahci_pcs_quirk }, /* ICH9 */
292 { PCI_VDEVICE(INTEL, 0x2927), .driver_data: board_ahci_pcs_quirk }, /* ICH9 */
293 { PCI_VDEVICE(INTEL, 0x2929), .driver_data: board_ahci_pcs_quirk }, /* ICH9M */
294 { PCI_VDEVICE(INTEL, 0x292a), .driver_data: board_ahci_pcs_quirk }, /* ICH9M */
295 { PCI_VDEVICE(INTEL, 0x292b), .driver_data: board_ahci_pcs_quirk }, /* ICH9M */
296 { PCI_VDEVICE(INTEL, 0x292c), .driver_data: board_ahci_pcs_quirk }, /* ICH9M */
297 { PCI_VDEVICE(INTEL, 0x292f), .driver_data: board_ahci_pcs_quirk }, /* ICH9M */
298 { PCI_VDEVICE(INTEL, 0x294d), .driver_data: board_ahci_pcs_quirk }, /* ICH9 */
299 { PCI_VDEVICE(INTEL, 0x294e), .driver_data: board_ahci_pcs_quirk }, /* ICH9M */
300 { PCI_VDEVICE(INTEL, 0x502a), .driver_data: board_ahci_pcs_quirk }, /* Tolapai */
301 { PCI_VDEVICE(INTEL, 0x502b), .driver_data: board_ahci_pcs_quirk }, /* Tolapai */
302 { PCI_VDEVICE(INTEL, 0x3a05), .driver_data: board_ahci_pcs_quirk }, /* ICH10 */
303 { PCI_VDEVICE(INTEL, 0x3a22), .driver_data: board_ahci_pcs_quirk }, /* ICH10 */
304 { PCI_VDEVICE(INTEL, 0x3a25), .driver_data: board_ahci_pcs_quirk }, /* ICH10 */
305 { PCI_VDEVICE(INTEL, 0x3b22), .driver_data: board_ahci_pcs_quirk }, /* PCH AHCI */
306 { PCI_VDEVICE(INTEL, 0x3b23), .driver_data: board_ahci_pcs_quirk }, /* PCH AHCI */
307 { PCI_VDEVICE(INTEL, 0x3b24), .driver_data: board_ahci_pcs_quirk }, /* PCH RAID */
308 { PCI_VDEVICE(INTEL, 0x3b25), .driver_data: board_ahci_pcs_quirk }, /* PCH RAID */
309 { PCI_VDEVICE(INTEL, 0x3b29), .driver_data: board_ahci_pcs_quirk }, /* PCH M AHCI */
310 { PCI_VDEVICE(INTEL, 0x3b2b), .driver_data: board_ahci_pcs_quirk }, /* PCH RAID */
311 { PCI_VDEVICE(INTEL, 0x3b2c), .driver_data: board_ahci_pcs_quirk }, /* PCH M RAID */
312 { PCI_VDEVICE(INTEL, 0x3b2f), .driver_data: board_ahci_pcs_quirk }, /* PCH AHCI */
313 { PCI_VDEVICE(INTEL, 0x19b0), .driver_data: board_ahci }, /* DNV AHCI */
314 { PCI_VDEVICE(INTEL, 0x19b1), .driver_data: board_ahci }, /* DNV AHCI */
315 { PCI_VDEVICE(INTEL, 0x19b2), .driver_data: board_ahci }, /* DNV AHCI */
316 { PCI_VDEVICE(INTEL, 0x19b3), .driver_data: board_ahci }, /* DNV AHCI */
317 { PCI_VDEVICE(INTEL, 0x19b4), .driver_data: board_ahci }, /* DNV AHCI */
318 { PCI_VDEVICE(INTEL, 0x19b5), .driver_data: board_ahci }, /* DNV AHCI */
319 { PCI_VDEVICE(INTEL, 0x19b6), .driver_data: board_ahci }, /* DNV AHCI */
320 { PCI_VDEVICE(INTEL, 0x19b7), .driver_data: board_ahci }, /* DNV AHCI */
321 { PCI_VDEVICE(INTEL, 0x19bE), .driver_data: board_ahci }, /* DNV AHCI */
322 { PCI_VDEVICE(INTEL, 0x19bF), .driver_data: board_ahci }, /* DNV AHCI */
323 { PCI_VDEVICE(INTEL, 0x19c0), .driver_data: board_ahci }, /* DNV AHCI */
324 { PCI_VDEVICE(INTEL, 0x19c1), .driver_data: board_ahci }, /* DNV AHCI */
325 { PCI_VDEVICE(INTEL, 0x19c2), .driver_data: board_ahci }, /* DNV AHCI */
326 { PCI_VDEVICE(INTEL, 0x19c3), .driver_data: board_ahci }, /* DNV AHCI */
327 { PCI_VDEVICE(INTEL, 0x19c4), .driver_data: board_ahci }, /* DNV AHCI */
328 { PCI_VDEVICE(INTEL, 0x19c5), .driver_data: board_ahci }, /* DNV AHCI */
329 { PCI_VDEVICE(INTEL, 0x19c6), .driver_data: board_ahci }, /* DNV AHCI */
330 { PCI_VDEVICE(INTEL, 0x19c7), .driver_data: board_ahci }, /* DNV AHCI */
331 { PCI_VDEVICE(INTEL, 0x19cE), .driver_data: board_ahci }, /* DNV AHCI */
332 { PCI_VDEVICE(INTEL, 0x19cF), .driver_data: board_ahci }, /* DNV AHCI */
333 { PCI_VDEVICE(INTEL, 0x1c02), .driver_data: board_ahci_pcs_quirk }, /* CPT AHCI */
334 { PCI_VDEVICE(INTEL, 0x1c03), .driver_data: board_ahci_pcs_quirk }, /* CPT M AHCI */
335 { PCI_VDEVICE(INTEL, 0x1c04), .driver_data: board_ahci_pcs_quirk }, /* CPT RAID */
336 { PCI_VDEVICE(INTEL, 0x1c05), .driver_data: board_ahci_pcs_quirk }, /* CPT M RAID */
337 { PCI_VDEVICE(INTEL, 0x1c06), .driver_data: board_ahci_pcs_quirk }, /* CPT RAID */
338 { PCI_VDEVICE(INTEL, 0x1c07), .driver_data: board_ahci_pcs_quirk }, /* CPT RAID */
339 { PCI_VDEVICE(INTEL, 0x1d02), .driver_data: board_ahci_pcs_quirk }, /* PBG AHCI */
340 { PCI_VDEVICE(INTEL, 0x1d04), .driver_data: board_ahci_pcs_quirk }, /* PBG RAID */
341 { PCI_VDEVICE(INTEL, 0x1d06), .driver_data: board_ahci_pcs_quirk }, /* PBG RAID */
342 { PCI_VDEVICE(INTEL, 0x2323), .driver_data: board_ahci_pcs_quirk }, /* DH89xxCC AHCI */
343 { PCI_VDEVICE(INTEL, 0x1e02), .driver_data: board_ahci_pcs_quirk }, /* Panther Point AHCI */
344 { PCI_VDEVICE(INTEL, 0x1e03), .driver_data: board_ahci_pcs_quirk }, /* Panther M AHCI */
345 { PCI_VDEVICE(INTEL, 0x1e04), .driver_data: board_ahci_pcs_quirk }, /* Panther Point RAID */
346 { PCI_VDEVICE(INTEL, 0x1e05), .driver_data: board_ahci_pcs_quirk }, /* Panther Point RAID */
347 { PCI_VDEVICE(INTEL, 0x1e06), .driver_data: board_ahci_pcs_quirk }, /* Panther Point RAID */
348 { PCI_VDEVICE(INTEL, 0x1e07), .driver_data: board_ahci_pcs_quirk }, /* Panther M RAID */
349 { PCI_VDEVICE(INTEL, 0x1e0e), .driver_data: board_ahci_pcs_quirk }, /* Panther Point RAID */
350 { PCI_VDEVICE(INTEL, 0x8c02), .driver_data: board_ahci_pcs_quirk }, /* Lynx Point AHCI */
351 { PCI_VDEVICE(INTEL, 0x8c03), .driver_data: board_ahci_pcs_quirk }, /* Lynx M AHCI */
352 { PCI_VDEVICE(INTEL, 0x8c04), .driver_data: board_ahci_pcs_quirk }, /* Lynx Point RAID */
353 { PCI_VDEVICE(INTEL, 0x8c05), .driver_data: board_ahci_pcs_quirk }, /* Lynx M RAID */
354 { PCI_VDEVICE(INTEL, 0x8c06), .driver_data: board_ahci_pcs_quirk }, /* Lynx Point RAID */
355 { PCI_VDEVICE(INTEL, 0x8c07), .driver_data: board_ahci_pcs_quirk }, /* Lynx M RAID */
356 { PCI_VDEVICE(INTEL, 0x8c0e), .driver_data: board_ahci_pcs_quirk }, /* Lynx Point RAID */
357 { PCI_VDEVICE(INTEL, 0x8c0f), .driver_data: board_ahci_pcs_quirk }, /* Lynx M RAID */
358 { PCI_VDEVICE(INTEL, 0x9c02), .driver_data: board_ahci_pcs_quirk }, /* Lynx LP AHCI */
359 { PCI_VDEVICE(INTEL, 0x9c03), .driver_data: board_ahci_pcs_quirk }, /* Lynx LP AHCI */
360 { PCI_VDEVICE(INTEL, 0x9c04), .driver_data: board_ahci_pcs_quirk }, /* Lynx LP RAID */
361 { PCI_VDEVICE(INTEL, 0x9c05), .driver_data: board_ahci_pcs_quirk }, /* Lynx LP RAID */
362 { PCI_VDEVICE(INTEL, 0x9c06), .driver_data: board_ahci_pcs_quirk }, /* Lynx LP RAID */
363 { PCI_VDEVICE(INTEL, 0x9c07), .driver_data: board_ahci_pcs_quirk }, /* Lynx LP RAID */
364 { PCI_VDEVICE(INTEL, 0x9c0e), .driver_data: board_ahci_pcs_quirk }, /* Lynx LP RAID */
365 { PCI_VDEVICE(INTEL, 0x9c0f), .driver_data: board_ahci_pcs_quirk }, /* Lynx LP RAID */
366 { PCI_VDEVICE(INTEL, 0x9dd3), .driver_data: board_ahci_pcs_quirk }, /* Cannon Lake PCH-LP AHCI */
367 { PCI_VDEVICE(INTEL, 0x1f22), .driver_data: board_ahci_pcs_quirk }, /* Avoton AHCI */
368 { PCI_VDEVICE(INTEL, 0x1f23), .driver_data: board_ahci_pcs_quirk }, /* Avoton AHCI */
369 { PCI_VDEVICE(INTEL, 0x1f24), .driver_data: board_ahci_pcs_quirk }, /* Avoton RAID */
370 { PCI_VDEVICE(INTEL, 0x1f25), .driver_data: board_ahci_pcs_quirk }, /* Avoton RAID */
371 { PCI_VDEVICE(INTEL, 0x1f26), .driver_data: board_ahci_pcs_quirk }, /* Avoton RAID */
372 { PCI_VDEVICE(INTEL, 0x1f27), .driver_data: board_ahci_pcs_quirk }, /* Avoton RAID */
373 { PCI_VDEVICE(INTEL, 0x1f2e), .driver_data: board_ahci_pcs_quirk }, /* Avoton RAID */
374 { PCI_VDEVICE(INTEL, 0x1f2f), .driver_data: board_ahci_pcs_quirk }, /* Avoton RAID */
375 { PCI_VDEVICE(INTEL, 0x1f32), .driver_data: board_ahci_avn }, /* Avoton AHCI */
376 { PCI_VDEVICE(INTEL, 0x1f33), .driver_data: board_ahci_avn }, /* Avoton AHCI */
377 { PCI_VDEVICE(INTEL, 0x1f34), .driver_data: board_ahci_avn }, /* Avoton RAID */
378 { PCI_VDEVICE(INTEL, 0x1f35), .driver_data: board_ahci_avn }, /* Avoton RAID */
379 { PCI_VDEVICE(INTEL, 0x1f36), .driver_data: board_ahci_avn }, /* Avoton RAID */
380 { PCI_VDEVICE(INTEL, 0x1f37), .driver_data: board_ahci_avn }, /* Avoton RAID */
381 { PCI_VDEVICE(INTEL, 0x1f3e), .driver_data: board_ahci_avn }, /* Avoton RAID */
382 { PCI_VDEVICE(INTEL, 0x1f3f), .driver_data: board_ahci_avn }, /* Avoton RAID */
383 { PCI_VDEVICE(INTEL, 0x2823), .driver_data: board_ahci_pcs_quirk }, /* Wellsburg/Lewisburg AHCI*/
384 { PCI_VDEVICE(INTEL, 0x2826), .driver_data: board_ahci_pcs_quirk }, /* *burg SATA0 'RAID' */
385 { PCI_VDEVICE(INTEL, 0x2827), .driver_data: board_ahci_pcs_quirk }, /* *burg SATA1 'RAID' */
386 { PCI_VDEVICE(INTEL, 0x282f), .driver_data: board_ahci_pcs_quirk }, /* *burg SATA2 'RAID' */
387 { PCI_VDEVICE(INTEL, 0x43d4), .driver_data: board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
388 { PCI_VDEVICE(INTEL, 0x43d5), .driver_data: board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
389 { PCI_VDEVICE(INTEL, 0x43d6), .driver_data: board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
390 { PCI_VDEVICE(INTEL, 0x43d7), .driver_data: board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
391 { PCI_VDEVICE(INTEL, 0x8d02), .driver_data: board_ahci_pcs_quirk }, /* Wellsburg AHCI */
392 { PCI_VDEVICE(INTEL, 0x8d04), .driver_data: board_ahci_pcs_quirk }, /* Wellsburg RAID */
393 { PCI_VDEVICE(INTEL, 0x8d06), .driver_data: board_ahci_pcs_quirk }, /* Wellsburg RAID */
394 { PCI_VDEVICE(INTEL, 0x8d0e), .driver_data: board_ahci_pcs_quirk }, /* Wellsburg RAID */
395 { PCI_VDEVICE(INTEL, 0x8d62), .driver_data: board_ahci_pcs_quirk }, /* Wellsburg AHCI */
396 { PCI_VDEVICE(INTEL, 0x8d64), .driver_data: board_ahci_pcs_quirk }, /* Wellsburg RAID */
397 { PCI_VDEVICE(INTEL, 0x8d66), .driver_data: board_ahci_pcs_quirk }, /* Wellsburg RAID */
398 { PCI_VDEVICE(INTEL, 0x8d6e), .driver_data: board_ahci_pcs_quirk }, /* Wellsburg RAID */
399 { PCI_VDEVICE(INTEL, 0x23a3), .driver_data: board_ahci_pcs_quirk }, /* Coleto Creek AHCI */
400 { PCI_VDEVICE(INTEL, 0x9c83), .driver_data: board_ahci_pcs_quirk }, /* Wildcat LP AHCI */
401 { PCI_VDEVICE(INTEL, 0x9c85), .driver_data: board_ahci_pcs_quirk }, /* Wildcat LP RAID */
402 { PCI_VDEVICE(INTEL, 0x9c87), .driver_data: board_ahci_pcs_quirk }, /* Wildcat LP RAID */
403 { PCI_VDEVICE(INTEL, 0x9c8f), .driver_data: board_ahci_pcs_quirk }, /* Wildcat LP RAID */
404 { PCI_VDEVICE(INTEL, 0x8c82), .driver_data: board_ahci_pcs_quirk }, /* 9 Series AHCI */
405 { PCI_VDEVICE(INTEL, 0x8c83), .driver_data: board_ahci_pcs_quirk }, /* 9 Series M AHCI */
406 { PCI_VDEVICE(INTEL, 0x8c84), .driver_data: board_ahci_pcs_quirk }, /* 9 Series RAID */
407 { PCI_VDEVICE(INTEL, 0x8c85), .driver_data: board_ahci_pcs_quirk }, /* 9 Series M RAID */
408 { PCI_VDEVICE(INTEL, 0x8c86), .driver_data: board_ahci_pcs_quirk }, /* 9 Series RAID */
409 { PCI_VDEVICE(INTEL, 0x8c87), .driver_data: board_ahci_pcs_quirk }, /* 9 Series M RAID */
410 { PCI_VDEVICE(INTEL, 0x8c8e), .driver_data: board_ahci_pcs_quirk }, /* 9 Series RAID */
411 { PCI_VDEVICE(INTEL, 0x8c8f), .driver_data: board_ahci_pcs_quirk }, /* 9 Series M RAID */
412 { PCI_VDEVICE(INTEL, 0x9d03), .driver_data: board_ahci_pcs_quirk }, /* Sunrise LP AHCI */
413 { PCI_VDEVICE(INTEL, 0x9d05), .driver_data: board_ahci_pcs_quirk }, /* Sunrise LP RAID */
414 { PCI_VDEVICE(INTEL, 0x9d07), .driver_data: board_ahci_pcs_quirk }, /* Sunrise LP RAID */
415 { PCI_VDEVICE(INTEL, 0xa102), .driver_data: board_ahci_pcs_quirk }, /* Sunrise Point-H AHCI */
416 { PCI_VDEVICE(INTEL, 0xa103), .driver_data: board_ahci_pcs_quirk }, /* Sunrise M AHCI */
417 { PCI_VDEVICE(INTEL, 0xa105), .driver_data: board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */
418 { PCI_VDEVICE(INTEL, 0xa106), .driver_data: board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */
419 { PCI_VDEVICE(INTEL, 0xa107), .driver_data: board_ahci_pcs_quirk }, /* Sunrise M RAID */
420 { PCI_VDEVICE(INTEL, 0xa10f), .driver_data: board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */
421 { PCI_VDEVICE(INTEL, 0xa182), .driver_data: board_ahci_pcs_quirk }, /* Lewisburg AHCI*/
422 { PCI_VDEVICE(INTEL, 0xa186), .driver_data: board_ahci_pcs_quirk }, /* Lewisburg RAID*/
423 { PCI_VDEVICE(INTEL, 0xa1d2), .driver_data: board_ahci_pcs_quirk }, /* Lewisburg RAID*/
424 { PCI_VDEVICE(INTEL, 0xa1d6), .driver_data: board_ahci_pcs_quirk }, /* Lewisburg RAID*/
425 { PCI_VDEVICE(INTEL, 0xa202), .driver_data: board_ahci_pcs_quirk }, /* Lewisburg AHCI*/
426 { PCI_VDEVICE(INTEL, 0xa206), .driver_data: board_ahci_pcs_quirk }, /* Lewisburg RAID*/
427 { PCI_VDEVICE(INTEL, 0xa252), .driver_data: board_ahci_pcs_quirk }, /* Lewisburg RAID*/
428 { PCI_VDEVICE(INTEL, 0xa256), .driver_data: board_ahci_pcs_quirk }, /* Lewisburg RAID*/
429 { PCI_VDEVICE(INTEL, 0xa356), .driver_data: board_ahci_pcs_quirk }, /* Cannon Lake PCH-H RAID */
430 { PCI_VDEVICE(INTEL, 0x06d7), .driver_data: board_ahci_pcs_quirk }, /* Comet Lake-H RAID */
431 { PCI_VDEVICE(INTEL, 0xa386), .driver_data: board_ahci_pcs_quirk }, /* Comet Lake PCH-V RAID */
432 { PCI_VDEVICE(INTEL, 0x0f22), .driver_data: board_ahci_pcs_quirk }, /* Bay Trail AHCI */
433 { PCI_VDEVICE(INTEL, 0x0f23), .driver_data: board_ahci_pcs_quirk_no_devslp }, /* Bay Trail AHCI */
434 { PCI_VDEVICE(INTEL, 0x22a3), .driver_data: board_ahci_pcs_quirk }, /* Cherry Tr. AHCI */
435 { PCI_VDEVICE(INTEL, 0x5ae3), .driver_data: board_ahci_pcs_quirk }, /* ApolloLake AHCI */
436 { PCI_VDEVICE(INTEL, 0x34d3), .driver_data: board_ahci_pcs_quirk }, /* Ice Lake LP AHCI */
437 { PCI_VDEVICE(INTEL, 0x02d3), .driver_data: board_ahci_pcs_quirk }, /* Comet Lake PCH-U AHCI */
438 { PCI_VDEVICE(INTEL, 0x02d7), .driver_data: board_ahci_pcs_quirk }, /* Comet Lake PCH RAID */
439 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
440 { PCI_VDEVICE(INTEL, 0x4b63), .driver_data: board_ahci_pcs_quirk }, /* Elkhart Lake AHCI */
441
442 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
443 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
444 PCI_CLASS_STORAGE_SATA_AHCI, .class_mask: 0xffffff, .driver_data: board_ahci_ign_iferr },
445 /* JMicron 362B and 362C have an AHCI function with IDE class code */
446 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
447 { PCI_VDEVICE(JMICRON, 0x236f), .driver_data: board_ahci_ign_iferr },
448 /* May need to update quirk_jmicron_async_suspend() for additions */
449
450 /* ATI */
451 { PCI_VDEVICE(ATI, 0x4380), .driver_data: board_ahci_sb600 }, /* ATI SB600 */
452 { PCI_VDEVICE(ATI, 0x4390), .driver_data: board_ahci_sb700 }, /* ATI SB700/800 */
453 { PCI_VDEVICE(ATI, 0x4391), .driver_data: board_ahci_sb700 }, /* ATI SB700/800 */
454 { PCI_VDEVICE(ATI, 0x4392), .driver_data: board_ahci_sb700 }, /* ATI SB700/800 */
455 { PCI_VDEVICE(ATI, 0x4393), .driver_data: board_ahci_sb700 }, /* ATI SB700/800 */
456 { PCI_VDEVICE(ATI, 0x4394), .driver_data: board_ahci_sb700 }, /* ATI SB700/800 */
457 { PCI_VDEVICE(ATI, 0x4395), .driver_data: board_ahci_sb700 }, /* ATI SB700/800 */
458
459 /* Amazon's Annapurna Labs support */
460 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
461 .class = PCI_CLASS_STORAGE_SATA_AHCI,
462 .class_mask = 0xffffff,
463 .driver_data: board_ahci_al },
464 /* AMD */
465 { PCI_VDEVICE(AMD, 0x7800), .driver_data: board_ahci }, /* AMD Hudson-2 */
466 { PCI_VDEVICE(AMD, 0x7801), .driver_data: board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
467 { PCI_VDEVICE(AMD, 0x7900), .driver_data: board_ahci }, /* AMD CZ */
468 { PCI_VDEVICE(AMD, 0x7901), .driver_data: board_ahci }, /* AMD Green Sardine */
469 /* AMD is using RAID class only for ahci controllers */
470 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
471 PCI_CLASS_STORAGE_RAID << 8, .class_mask: 0xffffff, .driver_data: board_ahci },
472
473 /* Dell S140/S150 */
474 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
475 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci_pcs_quirk },
476
477 /* VIA */
478 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
479 { PCI_VDEVICE(VIA, 0x6287), .driver_data: board_ahci_vt8251 }, /* VIA VT8251 */
480
481 /* NVIDIA */
482 { PCI_VDEVICE(NVIDIA, 0x044c), .driver_data: board_ahci_mcp65 }, /* MCP65 */
483 { PCI_VDEVICE(NVIDIA, 0x044d), .driver_data: board_ahci_mcp65 }, /* MCP65 */
484 { PCI_VDEVICE(NVIDIA, 0x044e), .driver_data: board_ahci_mcp65 }, /* MCP65 */
485 { PCI_VDEVICE(NVIDIA, 0x044f), .driver_data: board_ahci_mcp65 }, /* MCP65 */
486 { PCI_VDEVICE(NVIDIA, 0x045c), .driver_data: board_ahci_mcp65 }, /* MCP65 */
487 { PCI_VDEVICE(NVIDIA, 0x045d), .driver_data: board_ahci_mcp65 }, /* MCP65 */
488 { PCI_VDEVICE(NVIDIA, 0x045e), .driver_data: board_ahci_mcp65 }, /* MCP65 */
489 { PCI_VDEVICE(NVIDIA, 0x045f), .driver_data: board_ahci_mcp65 }, /* MCP65 */
490 { PCI_VDEVICE(NVIDIA, 0x0550), .driver_data: board_ahci_mcp67 }, /* MCP67 */
491 { PCI_VDEVICE(NVIDIA, 0x0551), .driver_data: board_ahci_mcp67 }, /* MCP67 */
492 { PCI_VDEVICE(NVIDIA, 0x0552), .driver_data: board_ahci_mcp67 }, /* MCP67 */
493 { PCI_VDEVICE(NVIDIA, 0x0553), .driver_data: board_ahci_mcp67 }, /* MCP67 */
494 { PCI_VDEVICE(NVIDIA, 0x0554), .driver_data: board_ahci_mcp67 }, /* MCP67 */
495 { PCI_VDEVICE(NVIDIA, 0x0555), .driver_data: board_ahci_mcp67 }, /* MCP67 */
496 { PCI_VDEVICE(NVIDIA, 0x0556), .driver_data: board_ahci_mcp67 }, /* MCP67 */
497 { PCI_VDEVICE(NVIDIA, 0x0557), .driver_data: board_ahci_mcp67 }, /* MCP67 */
498 { PCI_VDEVICE(NVIDIA, 0x0558), .driver_data: board_ahci_mcp67 }, /* MCP67 */
499 { PCI_VDEVICE(NVIDIA, 0x0559), .driver_data: board_ahci_mcp67 }, /* MCP67 */
500 { PCI_VDEVICE(NVIDIA, 0x055a), .driver_data: board_ahci_mcp67 }, /* MCP67 */
501 { PCI_VDEVICE(NVIDIA, 0x055b), .driver_data: board_ahci_mcp67 }, /* MCP67 */
502 { PCI_VDEVICE(NVIDIA, 0x0580), .driver_data: board_ahci_mcp_linux }, /* Linux ID */
503 { PCI_VDEVICE(NVIDIA, 0x0581), .driver_data: board_ahci_mcp_linux }, /* Linux ID */
504 { PCI_VDEVICE(NVIDIA, 0x0582), .driver_data: board_ahci_mcp_linux }, /* Linux ID */
505 { PCI_VDEVICE(NVIDIA, 0x0583), .driver_data: board_ahci_mcp_linux }, /* Linux ID */
506 { PCI_VDEVICE(NVIDIA, 0x0584), .driver_data: board_ahci_mcp_linux }, /* Linux ID */
507 { PCI_VDEVICE(NVIDIA, 0x0585), .driver_data: board_ahci_mcp_linux }, /* Linux ID */
508 { PCI_VDEVICE(NVIDIA, 0x0586), .driver_data: board_ahci_mcp_linux }, /* Linux ID */
509 { PCI_VDEVICE(NVIDIA, 0x0587), .driver_data: board_ahci_mcp_linux }, /* Linux ID */
510 { PCI_VDEVICE(NVIDIA, 0x0588), .driver_data: board_ahci_mcp_linux }, /* Linux ID */
511 { PCI_VDEVICE(NVIDIA, 0x0589), .driver_data: board_ahci_mcp_linux }, /* Linux ID */
512 { PCI_VDEVICE(NVIDIA, 0x058a), .driver_data: board_ahci_mcp_linux }, /* Linux ID */
513 { PCI_VDEVICE(NVIDIA, 0x058b), .driver_data: board_ahci_mcp_linux }, /* Linux ID */
514 { PCI_VDEVICE(NVIDIA, 0x058c), .driver_data: board_ahci_mcp_linux }, /* Linux ID */
515 { PCI_VDEVICE(NVIDIA, 0x058d), .driver_data: board_ahci_mcp_linux }, /* Linux ID */
516 { PCI_VDEVICE(NVIDIA, 0x058e), .driver_data: board_ahci_mcp_linux }, /* Linux ID */
517 { PCI_VDEVICE(NVIDIA, 0x058f), .driver_data: board_ahci_mcp_linux }, /* Linux ID */
518 { PCI_VDEVICE(NVIDIA, 0x07f0), .driver_data: board_ahci_mcp73 }, /* MCP73 */
519 { PCI_VDEVICE(NVIDIA, 0x07f1), .driver_data: board_ahci_mcp73 }, /* MCP73 */
520 { PCI_VDEVICE(NVIDIA, 0x07f2), .driver_data: board_ahci_mcp73 }, /* MCP73 */
521 { PCI_VDEVICE(NVIDIA, 0x07f3), .driver_data: board_ahci_mcp73 }, /* MCP73 */
522 { PCI_VDEVICE(NVIDIA, 0x07f4), .driver_data: board_ahci_mcp73 }, /* MCP73 */
523 { PCI_VDEVICE(NVIDIA, 0x07f5), .driver_data: board_ahci_mcp73 }, /* MCP73 */
524 { PCI_VDEVICE(NVIDIA, 0x07f6), .driver_data: board_ahci_mcp73 }, /* MCP73 */
525 { PCI_VDEVICE(NVIDIA, 0x07f7), .driver_data: board_ahci_mcp73 }, /* MCP73 */
526 { PCI_VDEVICE(NVIDIA, 0x07f8), .driver_data: board_ahci_mcp73 }, /* MCP73 */
527 { PCI_VDEVICE(NVIDIA, 0x07f9), .driver_data: board_ahci_mcp73 }, /* MCP73 */
528 { PCI_VDEVICE(NVIDIA, 0x07fa), .driver_data: board_ahci_mcp73 }, /* MCP73 */
529 { PCI_VDEVICE(NVIDIA, 0x07fb), .driver_data: board_ahci_mcp73 }, /* MCP73 */
530 { PCI_VDEVICE(NVIDIA, 0x0ad0), .driver_data: board_ahci_mcp77 }, /* MCP77 */
531 { PCI_VDEVICE(NVIDIA, 0x0ad1), .driver_data: board_ahci_mcp77 }, /* MCP77 */
532 { PCI_VDEVICE(NVIDIA, 0x0ad2), .driver_data: board_ahci_mcp77 }, /* MCP77 */
533 { PCI_VDEVICE(NVIDIA, 0x0ad3), .driver_data: board_ahci_mcp77 }, /* MCP77 */
534 { PCI_VDEVICE(NVIDIA, 0x0ad4), .driver_data: board_ahci_mcp77 }, /* MCP77 */
535 { PCI_VDEVICE(NVIDIA, 0x0ad5), .driver_data: board_ahci_mcp77 }, /* MCP77 */
536 { PCI_VDEVICE(NVIDIA, 0x0ad6), .driver_data: board_ahci_mcp77 }, /* MCP77 */
537 { PCI_VDEVICE(NVIDIA, 0x0ad7), .driver_data: board_ahci_mcp77 }, /* MCP77 */
538 { PCI_VDEVICE(NVIDIA, 0x0ad8), .driver_data: board_ahci_mcp77 }, /* MCP77 */
539 { PCI_VDEVICE(NVIDIA, 0x0ad9), .driver_data: board_ahci_mcp77 }, /* MCP77 */
540 { PCI_VDEVICE(NVIDIA, 0x0ada), .driver_data: board_ahci_mcp77 }, /* MCP77 */
541 { PCI_VDEVICE(NVIDIA, 0x0adb), .driver_data: board_ahci_mcp77 }, /* MCP77 */
542 { PCI_VDEVICE(NVIDIA, 0x0ab4), .driver_data: board_ahci_mcp79 }, /* MCP79 */
543 { PCI_VDEVICE(NVIDIA, 0x0ab5), .driver_data: board_ahci_mcp79 }, /* MCP79 */
544 { PCI_VDEVICE(NVIDIA, 0x0ab6), .driver_data: board_ahci_mcp79 }, /* MCP79 */
545 { PCI_VDEVICE(NVIDIA, 0x0ab7), .driver_data: board_ahci_mcp79 }, /* MCP79 */
546 { PCI_VDEVICE(NVIDIA, 0x0ab8), .driver_data: board_ahci_mcp79 }, /* MCP79 */
547 { PCI_VDEVICE(NVIDIA, 0x0ab9), .driver_data: board_ahci_mcp79 }, /* MCP79 */
548 { PCI_VDEVICE(NVIDIA, 0x0aba), .driver_data: board_ahci_mcp79 }, /* MCP79 */
549 { PCI_VDEVICE(NVIDIA, 0x0abb), .driver_data: board_ahci_mcp79 }, /* MCP79 */
550 { PCI_VDEVICE(NVIDIA, 0x0abc), .driver_data: board_ahci_mcp79 }, /* MCP79 */
551 { PCI_VDEVICE(NVIDIA, 0x0abd), .driver_data: board_ahci_mcp79 }, /* MCP79 */
552 { PCI_VDEVICE(NVIDIA, 0x0abe), .driver_data: board_ahci_mcp79 }, /* MCP79 */
553 { PCI_VDEVICE(NVIDIA, 0x0abf), .driver_data: board_ahci_mcp79 }, /* MCP79 */
554 { PCI_VDEVICE(NVIDIA, 0x0d84), .driver_data: board_ahci_mcp89 }, /* MCP89 */
555 { PCI_VDEVICE(NVIDIA, 0x0d85), .driver_data: board_ahci_mcp89 }, /* MCP89 */
556 { PCI_VDEVICE(NVIDIA, 0x0d86), .driver_data: board_ahci_mcp89 }, /* MCP89 */
557 { PCI_VDEVICE(NVIDIA, 0x0d87), .driver_data: board_ahci_mcp89 }, /* MCP89 */
558 { PCI_VDEVICE(NVIDIA, 0x0d88), .driver_data: board_ahci_mcp89 }, /* MCP89 */
559 { PCI_VDEVICE(NVIDIA, 0x0d89), .driver_data: board_ahci_mcp89 }, /* MCP89 */
560 { PCI_VDEVICE(NVIDIA, 0x0d8a), .driver_data: board_ahci_mcp89 }, /* MCP89 */
561 { PCI_VDEVICE(NVIDIA, 0x0d8b), .driver_data: board_ahci_mcp89 }, /* MCP89 */
562 { PCI_VDEVICE(NVIDIA, 0x0d8c), .driver_data: board_ahci_mcp89 }, /* MCP89 */
563 { PCI_VDEVICE(NVIDIA, 0x0d8d), .driver_data: board_ahci_mcp89 }, /* MCP89 */
564 { PCI_VDEVICE(NVIDIA, 0x0d8e), .driver_data: board_ahci_mcp89 }, /* MCP89 */
565 { PCI_VDEVICE(NVIDIA, 0x0d8f), .driver_data: board_ahci_mcp89 }, /* MCP89 */
566
567 /* SiS */
568 { PCI_VDEVICE(SI, 0x1184), .driver_data: board_ahci }, /* SiS 966 */
569 { PCI_VDEVICE(SI, 0x1185), .driver_data: board_ahci }, /* SiS 968 */
570 { PCI_VDEVICE(SI, 0x0186), .driver_data: board_ahci }, /* SiS 968 */
571
572 /* ST Microelectronics */
573 { PCI_VDEVICE(STMICRO, 0xCC06), .driver_data: board_ahci }, /* ST ConneXt */
574
575 /* Marvell */
576 { PCI_VDEVICE(MARVELL, 0x6145), .driver_data: board_ahci_mv }, /* 6145 */
577 { PCI_VDEVICE(MARVELL, 0x6121), .driver_data: board_ahci_mv }, /* 6121 */
578 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
579 .class = PCI_CLASS_STORAGE_SATA_AHCI,
580 .class_mask = 0xffffff,
581 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
582 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
583 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
584 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
585 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
586 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
587 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
588 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
589 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
590 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
591 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
592 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
593 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
594 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
595 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
596 .driver_data = board_ahci_yes_fbs },
597 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
598 .driver_data = board_ahci_yes_fbs },
599 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
600 .driver_data = board_ahci_yes_fbs },
601 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9215),
602 .driver_data = board_ahci_yes_fbs_atapi_dma },
603 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
604 .driver_data = board_ahci_yes_fbs },
605 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235),
606 .driver_data = board_ahci_no_debounce_delay },
607 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
608 .driver_data = board_ahci_yes_fbs },
609 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
610 .driver_data = board_ahci_yes_fbs },
611
612 /* Promise */
613 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
614 { PCI_VDEVICE(PROMISE, 0x3781), .driver_data: board_ahci }, /* FastTrak TX8660 ahci-mode */
615
616 /* ASMedia */
617 { PCI_VDEVICE(ASMEDIA, 0x0601), .driver_data: board_ahci_43bit_dma }, /* ASM1060 */
618 { PCI_VDEVICE(ASMEDIA, 0x0602), .driver_data: board_ahci_43bit_dma }, /* ASM1060 */
619 { PCI_VDEVICE(ASMEDIA, 0x0611), .driver_data: board_ahci_43bit_dma }, /* ASM1061 */
620 { PCI_VDEVICE(ASMEDIA, 0x0612), .driver_data: board_ahci_43bit_dma }, /* ASM1061/1062 */
621 { PCI_VDEVICE(ASMEDIA, 0x0621), .driver_data: board_ahci_43bit_dma }, /* ASM1061R */
622 { PCI_VDEVICE(ASMEDIA, 0x0622), .driver_data: board_ahci_43bit_dma }, /* ASM1062R */
623 { PCI_VDEVICE(ASMEDIA, 0x0624), .driver_data: board_ahci_43bit_dma }, /* ASM1062+JMB575 */
624 { PCI_VDEVICE(ASMEDIA, 0x1062), .driver_data: board_ahci }, /* ASM1062A */
625 { PCI_VDEVICE(ASMEDIA, 0x1064), .driver_data: board_ahci }, /* ASM1064 */
626 { PCI_VDEVICE(ASMEDIA, 0x1164), .driver_data: board_ahci }, /* ASM1164 */
627 { PCI_VDEVICE(ASMEDIA, 0x1165), .driver_data: board_ahci }, /* ASM1165 */
628 { PCI_VDEVICE(ASMEDIA, 0x1166), .driver_data: board_ahci }, /* ASM1166 */
629
630 /*
631 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
632 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
633 */
634 { PCI_VDEVICE(SAMSUNG, 0x1600), .driver_data: board_ahci_no_msi },
635 { PCI_VDEVICE(SAMSUNG, 0xa800), .driver_data: board_ahci_no_msi },
636
637 /* Enmotus */
638 { PCI_DEVICE(0x1c44, 0x8000), .class: board_ahci },
639
640 /* Loongson */
641 { PCI_VDEVICE(LOONGSON, 0x7a08), .driver_data: board_ahci },
642
643 /* Generic, PCI class code for AHCI */
644 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
645 PCI_CLASS_STORAGE_SATA_AHCI, .class_mask: 0xffffff, .driver_data: board_ahci },
646
647 { } /* terminate list */
648};
649
650static const struct dev_pm_ops ahci_pci_pm_ops = {
651 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
652 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
653 ahci_pci_device_runtime_resume, NULL)
654};
655
656static struct pci_driver ahci_pci_driver = {
657 .name = DRV_NAME,
658 .id_table = ahci_pci_tbl,
659 .probe = ahci_init_one,
660 .remove = ahci_remove_one,
661 .shutdown = ahci_shutdown_one,
662 .driver = {
663 .pm = &ahci_pci_pm_ops,
664 },
665};
666
667#if IS_ENABLED(CONFIG_PATA_MARVELL)
668static int marvell_enable;
669#else
670static int marvell_enable = 1;
671#endif
672module_param(marvell_enable, int, 0644);
673MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
674
675static int mobile_lpm_policy = -1;
676module_param(mobile_lpm_policy, int, 0644);
677MODULE_PARM_DESC(mobile_lpm_policy,
678 "Default LPM policy. Despite its name, this parameter applies "
679 "to all chipsets, including desktop and server chipsets");
680
681static char *ahci_mask_port_map;
682module_param_named(mask_port_map, ahci_mask_port_map, charp, 0444);
683MODULE_PARM_DESC(mask_port_map,
684 "32-bits port map masks to ignore controllers ports. "
685 "Valid values are: "
686 "\"<mask>\" to apply the same mask to all AHCI controller "
687 "devices, and \"<pci_dev>=<mask>,<pci_dev>=<mask>,...\" to "
688 "specify different masks for the controllers specified, "
689 "where <pci_dev> is the PCI ID of an AHCI controller in the "
690 "form \"domain:bus:dev.func\"");
691
692static char *ahci_mask_port_ext;
693module_param_named(mask_port_ext, ahci_mask_port_ext, charp, 0444);
694MODULE_PARM_DESC(mask_port_ext,
695 "32-bits mask to ignore the external/hotplug capability of ports. "
696 "Valid values are: "
697 "\"<mask>\" to apply the same mask to all AHCI controller "
698 "devices, and \"<pci_dev>=<mask>,<pci_dev>=<mask>,...\" to "
699 "specify different masks for the controllers specified, "
700 "where <pci_dev> is the PCI ID of an AHCI controller in the "
701 "form \"domain:bus:dev.func\"");
702
703static u32 ahci_port_mask(struct device *dev, char *mask_s)
704{
705 unsigned int mask;
706
707 if (kstrtouint(s: mask_s, base: 0, res: &mask)) {
708 dev_err(dev, "Invalid port map mask\n");
709 return 0;
710 }
711
712 return mask;
713}
714
715static u32 ahci_get_port_mask(struct device *dev, char *mask_p)
716{
717 char *param, *end, *str, *mask_s;
718 char *name;
719 u32 mask = 0;
720
721 if (!mask_p || !strlen(mask_p))
722 return 0;
723
724 str = kstrdup(s: mask_p, GFP_KERNEL);
725 if (!str)
726 return 0;
727
728 /* Handle single mask case */
729 if (!strchr(str, '=')) {
730 mask = ahci_port_mask(dev, mask_s: str);
731 goto free;
732 }
733
734 /*
735 * Mask list case: parse the parameter to get the mask only if
736 * the device name matches.
737 */
738 param = str;
739 end = param + strlen(param);
740 while (param && param < end && *param) {
741 name = param;
742 param = strchr(name, '=');
743 if (!param)
744 break;
745
746 *param = '\0';
747 param++;
748 if (param >= end)
749 break;
750
751 if (strcmp(dev_name(dev), name) != 0) {
752 param = strchr(param, ',');
753 if (param)
754 param++;
755 continue;
756 }
757
758 mask_s = param;
759 param = strchr(mask_s, ',');
760 if (param) {
761 *param = '\0';
762 param++;
763 }
764
765 mask = ahci_port_mask(dev, mask_s);
766 }
767
768free:
769 kfree(objp: str);
770
771 return mask;
772}
773
774static void ahci_pci_save_initial_config(struct pci_dev *pdev,
775 struct ahci_host_priv *hpriv)
776{
777 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
778 dev_info(&pdev->dev, "JMB361 has only one port\n");
779 hpriv->saved_port_map = 1;
780 }
781
782 /*
783 * Temporary Marvell 6145 hack: PATA port presence
784 * is asserted through the standard AHCI port
785 * presence register, as bit 4 (counting from 0)
786 */
787 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
788 if (pdev->device == 0x6121)
789 hpriv->mask_port_map = 0x3;
790 else
791 hpriv->mask_port_map = 0xf;
792 dev_info(&pdev->dev,
793 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
794 }
795
796 /* Handle port map masks passed as module parameter. */
797 hpriv->mask_port_map =
798 ahci_get_port_mask(dev: &pdev->dev, mask_p: ahci_mask_port_map);
799 hpriv->mask_port_ext =
800 ahci_get_port_mask(dev: &pdev->dev, mask_p: ahci_mask_port_ext);
801
802 ahci_save_initial_config(dev: &pdev->dev, hpriv);
803}
804
805static int ahci_pci_reset_controller(struct ata_host *host)
806{
807 struct pci_dev *pdev = to_pci_dev(host->dev);
808 struct ahci_host_priv *hpriv = host->private_data;
809 int rc;
810
811 rc = ahci_reset_controller(host);
812 if (rc)
813 return rc;
814
815 /*
816 * If platform firmware failed to enable ports, try to enable
817 * them here.
818 */
819 ahci_intel_pcs_quirk(pdev, hpriv);
820
821 return 0;
822}
823
824static void ahci_pci_init_controller(struct ata_host *host)
825{
826 struct ahci_host_priv *hpriv = host->private_data;
827 struct pci_dev *pdev = to_pci_dev(host->dev);
828 void __iomem *port_mmio;
829 u32 tmp;
830 int mv;
831
832 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
833 if (pdev->device == 0x6121)
834 mv = 2;
835 else
836 mv = 4;
837 port_mmio = __ahci_port_base(hpriv, port_no: mv);
838
839 writel(val: 0, addr: port_mmio + PORT_IRQ_MASK);
840
841 /* clear port IRQ */
842 tmp = readl(addr: port_mmio + PORT_IRQ_STAT);
843 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
844 if (tmp)
845 writel(val: tmp, addr: port_mmio + PORT_IRQ_STAT);
846 }
847
848 ahci_init_controller(host);
849}
850
851static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
852 unsigned long deadline)
853{
854 struct ata_port *ap = link->ap;
855 struct ahci_host_priv *hpriv = ap->host->private_data;
856 bool online;
857 int rc;
858
859 hpriv->stop_engine(ap);
860
861 rc = sata_link_hardreset(link, timing: sata_ehc_deb_timing(ehc: &link->eh_context),
862 deadline, online: &online, NULL);
863
864 hpriv->start_engine(ap);
865
866 /* vt8251 doesn't clear BSY on signature FIS reception,
867 * request follow-up softreset.
868 */
869 return online ? -EAGAIN : rc;
870}
871
872static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
873 unsigned long deadline)
874{
875 struct ata_port *ap = link->ap;
876 struct ahci_port_priv *pp = ap->private_data;
877 struct ahci_host_priv *hpriv = ap->host->private_data;
878 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
879 struct ata_taskfile tf;
880 bool online;
881 int rc;
882
883 hpriv->stop_engine(ap);
884
885 /* clear D2H reception area to properly wait for D2H FIS */
886 ata_tf_init(dev: link->device, tf: &tf);
887 tf.status = ATA_BUSY;
888 ata_tf_to_fis(tf: &tf, pmp: 0, is_cmd: 0, fis: d2h_fis);
889
890 rc = sata_link_hardreset(link, timing: sata_ehc_deb_timing(ehc: &link->eh_context),
891 deadline, online: &online, NULL);
892
893 hpriv->start_engine(ap);
894
895 /* The pseudo configuration device on SIMG4726 attached to
896 * ASUS P5W-DH Deluxe doesn't send signature FIS after
897 * hardreset if no device is attached to the first downstream
898 * port && the pseudo device locks up on SRST w/ PMP==0. To
899 * work around this, wait for !BSY only briefly. If BSY isn't
900 * cleared, perform CLO and proceed to IDENTIFY (achieved by
901 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
902 *
903 * Wait for two seconds. Devices attached to downstream port
904 * which can't process the following IDENTIFY after this will
905 * have to be reset again. For most cases, this should
906 * suffice while making probing snappish enough.
907 */
908 if (online) {
909 rc = ata_wait_after_reset(link, deadline: jiffies + 2 * HZ,
910 check_ready: ahci_check_ready);
911 if (rc)
912 ahci_kick_engine(ap);
913 }
914 return rc;
915}
916
917/*
918 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
919 *
920 * It has been observed with some SSDs that the timing of events in the
921 * link synchronization phase can leave the port in a state that can not
922 * be recovered by a SATA-hard-reset alone. The failing signature is
923 * SStatus.DET stuck at 1 ("Device presence detected but Phy
924 * communication not established"). It was found that unloading and
925 * reloading the driver when this problem occurs allows the drive
926 * connection to be recovered (DET advanced to 0x3). The critical
927 * component of reloading the driver is that the port state machines are
928 * reset by bouncing "port enable" in the AHCI PCS configuration
929 * register. So, reproduce that effect by bouncing a port whenever we
930 * see DET==1 after a reset.
931 */
932static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
933 unsigned long deadline)
934{
935 const unsigned int *timing = sata_ehc_deb_timing(ehc: &link->eh_context);
936 struct ata_port *ap = link->ap;
937 struct ahci_port_priv *pp = ap->private_data;
938 struct ahci_host_priv *hpriv = ap->host->private_data;
939 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
940 unsigned long tmo = deadline - jiffies;
941 struct ata_taskfile tf;
942 bool online;
943 int rc, i;
944
945 hpriv->stop_engine(ap);
946
947 for (i = 0; i < 2; i++) {
948 u16 val;
949 u32 sstatus;
950 int port = ap->port_no;
951 struct ata_host *host = ap->host;
952 struct pci_dev *pdev = to_pci_dev(host->dev);
953
954 /* clear D2H reception area to properly wait for D2H FIS */
955 ata_tf_init(dev: link->device, tf: &tf);
956 tf.status = ATA_BUSY;
957 ata_tf_to_fis(tf: &tf, pmp: 0, is_cmd: 0, fis: d2h_fis);
958
959 rc = sata_link_hardreset(link, timing, deadline, online: &online,
960 check_ready: ahci_check_ready);
961
962 if (sata_scr_read(link, reg: SCR_STATUS, val: &sstatus) != 0 ||
963 (sstatus & 0xf) != 1)
964 break;
965
966 ata_link_info(link, "avn bounce port%d\n", port);
967
968 pci_read_config_word(dev: pdev, where: 0x92, val: &val);
969 val &= ~(1 << port);
970 pci_write_config_word(dev: pdev, where: 0x92, val);
971 ata_msleep(ap, msecs: 1000);
972 val |= 1 << port;
973 pci_write_config_word(dev: pdev, where: 0x92, val);
974 deadline += tmo;
975 }
976
977 hpriv->start_engine(ap);
978
979 if (online)
980 *class = ahci_dev_classify(ap);
981
982 return rc;
983}
984
985
986#ifdef CONFIG_PM
987static void ahci_pci_disable_interrupts(struct ata_host *host)
988{
989 struct ahci_host_priv *hpriv = host->private_data;
990 void __iomem *mmio = hpriv->mmio;
991 u32 ctl;
992
993 /* AHCI spec rev1.1 section 8.3.3:
994 * Software must disable interrupts prior to requesting a
995 * transition of the HBA to D3 state.
996 */
997 ctl = readl(addr: mmio + HOST_CTL);
998 ctl &= ~HOST_IRQ_EN;
999 writel(val: ctl, addr: mmio + HOST_CTL);
1000 readl(addr: mmio + HOST_CTL); /* flush */
1001}
1002
1003static int ahci_pci_device_runtime_suspend(struct device *dev)
1004{
1005 struct pci_dev *pdev = to_pci_dev(dev);
1006 struct ata_host *host = pci_get_drvdata(pdev);
1007
1008 ahci_pci_disable_interrupts(host);
1009 return 0;
1010}
1011
1012static int ahci_pci_device_runtime_resume(struct device *dev)
1013{
1014 struct pci_dev *pdev = to_pci_dev(dev);
1015 struct ata_host *host = pci_get_drvdata(pdev);
1016 int rc;
1017
1018 rc = ahci_pci_reset_controller(host);
1019 if (rc)
1020 return rc;
1021 ahci_pci_init_controller(host);
1022 return 0;
1023}
1024
1025#ifdef CONFIG_PM_SLEEP
1026static int ahci_pci_device_suspend(struct device *dev)
1027{
1028 struct pci_dev *pdev = to_pci_dev(dev);
1029 struct ata_host *host = pci_get_drvdata(pdev);
1030 struct ahci_host_priv *hpriv = host->private_data;
1031
1032 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
1033 dev_err(&pdev->dev,
1034 "BIOS update required for suspend/resume\n");
1035 return -EIO;
1036 }
1037
1038 ahci_pci_disable_interrupts(host);
1039 ata_host_suspend(host, PMSG_SUSPEND);
1040 return 0;
1041}
1042
1043static int ahci_pci_device_resume(struct device *dev)
1044{
1045 struct pci_dev *pdev = to_pci_dev(dev);
1046 struct ata_host *host = pci_get_drvdata(pdev);
1047 int rc;
1048
1049 /* Apple BIOS helpfully mangles the registers on resume */
1050 if (is_mcp89_apple(pdev))
1051 ahci_mcp89_apple_enable(pdev);
1052
1053 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1054 rc = ahci_pci_reset_controller(host);
1055 if (rc)
1056 return rc;
1057
1058 ahci_pci_init_controller(host);
1059 }
1060
1061 ata_host_resume(host);
1062
1063 return 0;
1064}
1065#endif
1066
1067#endif /* CONFIG_PM */
1068
1069static int ahci_configure_dma_masks(struct pci_dev *pdev,
1070 struct ahci_host_priv *hpriv)
1071{
1072 int dma_bits;
1073 int rc;
1074
1075 if (hpriv->cap & HOST_CAP_64) {
1076 dma_bits = 64;
1077 if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY)
1078 dma_bits = 43;
1079 } else {
1080 dma_bits = 32;
1081 }
1082
1083 /*
1084 * If the device fixup already set the dma_mask to some non-standard
1085 * value, don't extend it here. This happens on STA2X11, for example.
1086 *
1087 * XXX: manipulating the DMA mask from platform code is completely
1088 * bogus, platform code should use dev->bus_dma_limit instead..
1089 */
1090 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
1091 return 0;
1092
1093 rc = dma_set_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(dma_bits));
1094 if (rc)
1095 dev_err(&pdev->dev, "DMA enable failed\n");
1096 return rc;
1097}
1098
1099static void ahci_pci_print_info(struct ata_host *host)
1100{
1101 struct pci_dev *pdev = to_pci_dev(host->dev);
1102 u16 cc;
1103 const char *scc_s;
1104
1105 pci_read_config_word(dev: pdev, where: 0x0a, val: &cc);
1106 if (cc == PCI_CLASS_STORAGE_IDE)
1107 scc_s = "IDE";
1108 else if (cc == PCI_CLASS_STORAGE_SATA)
1109 scc_s = "SATA";
1110 else if (cc == PCI_CLASS_STORAGE_RAID)
1111 scc_s = "RAID";
1112 else
1113 scc_s = "unknown";
1114
1115 ahci_print_info(host, scc_s);
1116}
1117
1118/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
1119 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
1120 * support PMP and the 4726 either directly exports the device
1121 * attached to the first downstream port or acts as a hardware storage
1122 * controller and emulate a single ATA device (can be RAID 0/1 or some
1123 * other configuration).
1124 *
1125 * When there's no device attached to the first downstream port of the
1126 * 4726, "Config Disk" appears, which is a pseudo ATA device to
1127 * configure the 4726. However, ATA emulation of the device is very
1128 * lame. It doesn't send signature D2H Reg FIS after the initial
1129 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
1130 *
1131 * The following function works around the problem by always using
1132 * hardreset on the port and not depending on receiving signature FIS
1133 * afterward. If signature FIS isn't received soon, ATA class is
1134 * assumed without follow-up softreset.
1135 */
1136static void ahci_p5wdh_workaround(struct ata_host *host)
1137{
1138 static const struct dmi_system_id sysids[] = {
1139 {
1140 .ident = "P5W DH Deluxe",
1141 .matches = {
1142 DMI_MATCH(DMI_SYS_VENDOR,
1143 "ASUSTEK COMPUTER INC"),
1144 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1145 },
1146 },
1147 { }
1148 };
1149 struct pci_dev *pdev = to_pci_dev(host->dev);
1150
1151 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1152 dmi_check_system(list: sysids)) {
1153 struct ata_port *ap = host->ports[1];
1154
1155 dev_info(&pdev->dev,
1156 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1157
1158 ap->ops = &ahci_p5wdh_ops;
1159 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1160 }
1161}
1162
1163/*
1164 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1165 * booting in BIOS compatibility mode. We restore the registers but not ID.
1166 */
1167static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1168{
1169 u32 val;
1170
1171 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1172
1173 pci_read_config_dword(dev: pdev, where: 0xf8, val: &val);
1174 val |= 1 << 0x1b;
1175 /* the following changes the device ID, but appears not to affect function */
1176 /* val = (val & ~0xf0000000) | 0x80000000; */
1177 pci_write_config_dword(dev: pdev, where: 0xf8, val);
1178
1179 pci_read_config_dword(dev: pdev, where: 0x54c, val: &val);
1180 val |= 1 << 0xc;
1181 pci_write_config_dword(dev: pdev, where: 0x54c, val);
1182
1183 pci_read_config_dword(dev: pdev, where: 0x4a4, val: &val);
1184 val &= 0xff;
1185 val |= 0x01060100;
1186 pci_write_config_dword(dev: pdev, where: 0x4a4, val);
1187
1188 pci_read_config_dword(dev: pdev, where: 0x54c, val: &val);
1189 val &= ~(1 << 0xc);
1190 pci_write_config_dword(dev: pdev, where: 0x54c, val);
1191
1192 pci_read_config_dword(dev: pdev, where: 0xf8, val: &val);
1193 val &= ~(1 << 0x1b);
1194 pci_write_config_dword(dev: pdev, where: 0xf8, val);
1195}
1196
1197static bool is_mcp89_apple(struct pci_dev *pdev)
1198{
1199 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1200 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1201 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1202 pdev->subsystem_device == 0xcb89;
1203}
1204
1205/* only some SB600 ahci controllers can do 64bit DMA */
1206static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1207{
1208 static const struct dmi_system_id sysids[] = {
1209 /*
1210 * The oldest version known to be broken is 0901 and
1211 * working is 1501 which was released on 2007-10-26.
1212 * Enable 64bit DMA on 1501 and anything newer.
1213 *
1214 * Please read bko#9412 for more info.
1215 */
1216 {
1217 .ident = "ASUS M2A-VM",
1218 .matches = {
1219 DMI_MATCH(DMI_BOARD_VENDOR,
1220 "ASUSTeK Computer INC."),
1221 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1222 },
1223 .driver_data = "20071026", /* yyyymmdd */
1224 },
1225 /*
1226 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1227 * support 64bit DMA.
1228 *
1229 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1230 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1231 * This spelling mistake was fixed in BIOS version 1.5, so
1232 * 1.5 and later have the Manufacturer as
1233 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1234 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1235 *
1236 * BIOS versions earlier than 1.9 had a Board Product Name
1237 * DMI field of "MS-7376". This was changed to be
1238 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1239 * match on DMI_BOARD_NAME of "MS-7376".
1240 */
1241 {
1242 .ident = "MSI K9A2 Platinum",
1243 .matches = {
1244 DMI_MATCH(DMI_BOARD_VENDOR,
1245 "MICRO-STAR INTER"),
1246 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1247 },
1248 },
1249 /*
1250 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1251 * 64bit DMA.
1252 *
1253 * This board also had the typo mentioned above in the
1254 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1255 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1256 */
1257 {
1258 .ident = "MSI K9AGM2",
1259 .matches = {
1260 DMI_MATCH(DMI_BOARD_VENDOR,
1261 "MICRO-STAR INTER"),
1262 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1263 },
1264 },
1265 /*
1266 * All BIOS versions for the Asus M3A support 64bit DMA.
1267 * (all release versions from 0301 to 1206 were tested)
1268 */
1269 {
1270 .ident = "ASUS M3A",
1271 .matches = {
1272 DMI_MATCH(DMI_BOARD_VENDOR,
1273 "ASUSTeK Computer INC."),
1274 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1275 },
1276 },
1277 { }
1278 };
1279 const struct dmi_system_id *match;
1280 int year, month, date;
1281 char buf[9];
1282
1283 match = dmi_first_match(list: sysids);
1284 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1285 !match)
1286 return false;
1287
1288 if (!match->driver_data)
1289 goto enable_64bit;
1290
1291 dmi_get_date(field: DMI_BIOS_DATE, yearp: &year, monthp: &month, dayp: &date);
1292 snprintf(buf, size: sizeof(buf), fmt: "%04d%02d%02d", year, month, date);
1293
1294 if (strcmp(buf, match->driver_data) >= 0)
1295 goto enable_64bit;
1296 else {
1297 dev_warn(&pdev->dev,
1298 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1299 match->ident);
1300 return false;
1301 }
1302
1303enable_64bit:
1304 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1305 return true;
1306}
1307
1308static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1309{
1310 static const struct dmi_system_id broken_systems[] = {
1311 {
1312 .ident = "HP Compaq nx6310",
1313 .matches = {
1314 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1315 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1316 },
1317 /* PCI slot number of the controller */
1318 .driver_data = (void *)0x1FUL,
1319 },
1320 {
1321 .ident = "HP Compaq 6720s",
1322 .matches = {
1323 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1324 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1325 },
1326 /* PCI slot number of the controller */
1327 .driver_data = (void *)0x1FUL,
1328 },
1329
1330 { } /* terminate list */
1331 };
1332 const struct dmi_system_id *dmi = dmi_first_match(list: broken_systems);
1333
1334 if (dmi) {
1335 unsigned long slot = (unsigned long)dmi->driver_data;
1336 /* apply the quirk only to on-board controllers */
1337 return slot == PCI_SLOT(pdev->devfn);
1338 }
1339
1340 return false;
1341}
1342
1343static bool ahci_broken_suspend(struct pci_dev *pdev)
1344{
1345 static const struct dmi_system_id sysids[] = {
1346 /*
1347 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1348 * to the harddisk doesn't become online after
1349 * resuming from STR. Warn and fail suspend.
1350 *
1351 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1352 *
1353 * Use dates instead of versions to match as HP is
1354 * apparently recycling both product and version
1355 * strings.
1356 *
1357 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1358 */
1359 {
1360 .ident = "dv4",
1361 .matches = {
1362 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1363 DMI_MATCH(DMI_PRODUCT_NAME,
1364 "HP Pavilion dv4 Notebook PC"),
1365 },
1366 .driver_data = "20090105", /* F.30 */
1367 },
1368 {
1369 .ident = "dv5",
1370 .matches = {
1371 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1372 DMI_MATCH(DMI_PRODUCT_NAME,
1373 "HP Pavilion dv5 Notebook PC"),
1374 },
1375 .driver_data = "20090506", /* F.16 */
1376 },
1377 {
1378 .ident = "dv6",
1379 .matches = {
1380 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1381 DMI_MATCH(DMI_PRODUCT_NAME,
1382 "HP Pavilion dv6 Notebook PC"),
1383 },
1384 .driver_data = "20090423", /* F.21 */
1385 },
1386 {
1387 .ident = "HDX18",
1388 .matches = {
1389 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1390 DMI_MATCH(DMI_PRODUCT_NAME,
1391 "HP HDX18 Notebook PC"),
1392 },
1393 .driver_data = "20090430", /* F.23 */
1394 },
1395 /*
1396 * Acer eMachines G725 has the same problem. BIOS
1397 * V1.03 is known to be broken. V3.04 is known to
1398 * work. Between, there are V1.06, V2.06 and V3.03
1399 * that we don't have much idea about. For now,
1400 * assume that anything older than V3.04 is broken.
1401 *
1402 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1403 */
1404 {
1405 .ident = "G725",
1406 .matches = {
1407 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1408 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1409 },
1410 .driver_data = "20091216", /* V3.04 */
1411 },
1412 { } /* terminate list */
1413 };
1414 const struct dmi_system_id *dmi = dmi_first_match(list: sysids);
1415 int year, month, date;
1416 char buf[9];
1417
1418 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1419 return false;
1420
1421 dmi_get_date(field: DMI_BIOS_DATE, yearp: &year, monthp: &month, dayp: &date);
1422 snprintf(buf, size: sizeof(buf), fmt: "%04d%02d%02d", year, month, date);
1423
1424 return strcmp(buf, dmi->driver_data) < 0;
1425}
1426
1427static bool ahci_broken_lpm(struct pci_dev *pdev)
1428{
1429 /*
1430 * Platforms with LPM problems.
1431 * If driver_data is NULL, there is no existing BIOS version with
1432 * functioning LPM.
1433 * If driver_data is non-NULL, then driver_data contains the DMI BIOS
1434 * build date of the first BIOS version with functioning LPM (i.e. older
1435 * BIOS versions have broken LPM).
1436 */
1437 static const struct dmi_system_id sysids[] = {
1438 {
1439 .matches = {
1440 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1441 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1442 },
1443 .driver_data = "20180406", /* 1.31 */
1444 },
1445 {
1446 .matches = {
1447 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1448 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1449 },
1450 .driver_data = "20180420", /* 1.28 */
1451 },
1452 {
1453 .matches = {
1454 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1455 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1456 },
1457 .driver_data = "20180315", /* 1.33 */
1458 },
1459 {
1460 .matches = {
1461 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1462 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1463 },
1464 .driver_data = "20180409", /* 2.35 */
1465 },
1466 {
1467 .matches = {
1468 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
1469 DMI_MATCH(DMI_PRODUCT_NAME, "ASUSPRO D840MB_M840SA"),
1470 },
1471 /* 320 is broken, there is no known good version. */
1472 },
1473 {
1474 /*
1475 * AMD 500 Series Chipset SATA Controller [1022:43eb]
1476 * on this motherboard timeouts on ports 5 and 6 when
1477 * LPM is enabled, at least with WDC WD20EFAX-68FB5N0
1478 * hard drives. LPM with the same drive works fine on
1479 * all other ports on the same controller.
1480 */
1481 .matches = {
1482 DMI_MATCH(DMI_BOARD_VENDOR,
1483 "ASUSTeK COMPUTER INC."),
1484 DMI_MATCH(DMI_BOARD_NAME,
1485 "ROG STRIX B550-F GAMING (WI-FI)"),
1486 },
1487 /* 3621 is broken, there is no known good version. */
1488 },
1489 { } /* terminate list */
1490 };
1491 const struct dmi_system_id *dmi = dmi_first_match(list: sysids);
1492 int year, month, date;
1493 char buf[9];
1494
1495 if (!dmi)
1496 return false;
1497
1498 if (!dmi->driver_data)
1499 return true;
1500
1501 dmi_get_date(field: DMI_BIOS_DATE, yearp: &year, monthp: &month, dayp: &date);
1502 snprintf(buf, size: sizeof(buf), fmt: "%04d%02d%02d", year, month, date);
1503
1504 return strcmp(buf, dmi->driver_data) < 0;
1505}
1506
1507static bool ahci_broken_online(struct pci_dev *pdev)
1508{
1509#define ENCODE_BUSDEVFN(bus, slot, func) \
1510 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1511 static const struct dmi_system_id sysids[] = {
1512 /*
1513 * There are several gigabyte boards which use
1514 * SIMG5723s configured as hardware RAID. Certain
1515 * 5723 firmware revisions shipped there keep the link
1516 * online but fail to answer properly to SRST or
1517 * IDENTIFY when no device is attached downstream
1518 * causing libata to retry quite a few times leading
1519 * to excessive detection delay.
1520 *
1521 * As these firmwares respond to the second reset try
1522 * with invalid device signature, considering unknown
1523 * sig as offline works around the problem acceptably.
1524 */
1525 {
1526 .ident = "EP45-DQ6",
1527 .matches = {
1528 DMI_MATCH(DMI_BOARD_VENDOR,
1529 "Gigabyte Technology Co., Ltd."),
1530 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1531 },
1532 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1533 },
1534 {
1535 .ident = "EP45-DS5",
1536 .matches = {
1537 DMI_MATCH(DMI_BOARD_VENDOR,
1538 "Gigabyte Technology Co., Ltd."),
1539 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1540 },
1541 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1542 },
1543 { } /* terminate list */
1544 };
1545#undef ENCODE_BUSDEVFN
1546 const struct dmi_system_id *dmi = dmi_first_match(list: sysids);
1547 unsigned int val;
1548
1549 if (!dmi)
1550 return false;
1551
1552 val = (unsigned long)dmi->driver_data;
1553
1554 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1555}
1556
1557#ifdef CONFIG_ATA_ACPI
1558static void ahci_gtf_filter_workaround(struct ata_host *host)
1559{
1560 static const struct dmi_system_id sysids[] = {
1561 /*
1562 * Aspire 3810T issues a bunch of SATA enable commands
1563 * via _GTF including an invalid one and one which is
1564 * rejected by the device. Among the successful ones
1565 * is FPDMA non-zero offset enable which when enabled
1566 * only on the drive side leads to NCQ command
1567 * failures. Filter it out.
1568 */
1569 {
1570 .ident = "Aspire 3810T",
1571 .matches = {
1572 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1573 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1574 },
1575 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1576 },
1577 { }
1578 };
1579 const struct dmi_system_id *dmi = dmi_first_match(list: sysids);
1580 unsigned int filter;
1581 int i;
1582
1583 if (!dmi)
1584 return;
1585
1586 filter = (unsigned long)dmi->driver_data;
1587 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1588 filter, dmi->ident);
1589
1590 for (i = 0; i < host->n_ports; i++) {
1591 struct ata_port *ap = host->ports[i];
1592 struct ata_link *link;
1593 struct ata_device *dev;
1594
1595 ata_for_each_link(link, ap, EDGE)
1596 ata_for_each_dev(dev, link, ALL)
1597 dev->gtf_filter |= filter;
1598 }
1599}
1600#else
1601static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1602{}
1603#endif
1604
1605/*
1606 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1607 * as DUMMY, or detected but eventually get a "link down" and never get up
1608 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1609 * port_map may hold a value of 0x00.
1610 *
1611 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1612 * and can significantly reduce the occurrence of the problem.
1613 *
1614 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1615 */
1616static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1617 struct pci_dev *pdev)
1618{
1619 static const struct dmi_system_id sysids[] = {
1620 {
1621 .ident = "Acer Switch Alpha 12",
1622 .matches = {
1623 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1624 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1625 },
1626 },
1627 { }
1628 };
1629
1630 if (dmi_check_system(list: sysids)) {
1631 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1632 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1633 hpriv->port_map = 0x7;
1634 hpriv->cap = 0xC734FF02;
1635 }
1636 }
1637}
1638
1639#ifdef CONFIG_ARM64
1640/*
1641 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1642 * Workaround is to make sure all pending IRQs are served before leaving
1643 * handler.
1644 */
1645static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1646{
1647 struct ata_host *host = dev_instance;
1648 struct ahci_host_priv *hpriv;
1649 unsigned int rc = 0;
1650 void __iomem *mmio;
1651 u32 irq_stat, irq_masked;
1652 unsigned int handled = 1;
1653
1654 hpriv = host->private_data;
1655 mmio = hpriv->mmio;
1656 irq_stat = readl(mmio + HOST_IRQ_STAT);
1657 if (!irq_stat)
1658 return IRQ_NONE;
1659
1660 do {
1661 irq_masked = irq_stat & hpriv->port_map;
1662 spin_lock(&host->lock);
1663 rc = ahci_handle_port_intr(host, irq_masked);
1664 if (!rc)
1665 handled = 0;
1666 writel(irq_stat, mmio + HOST_IRQ_STAT);
1667 irq_stat = readl(mmio + HOST_IRQ_STAT);
1668 spin_unlock(&host->lock);
1669 } while (irq_stat);
1670
1671 return IRQ_RETVAL(handled);
1672}
1673#endif
1674
1675static void ahci_remap_check(struct pci_dev *pdev, int bar,
1676 struct ahci_host_priv *hpriv)
1677{
1678 int i;
1679 u32 cap;
1680
1681 /*
1682 * Check if this device might have remapped nvme devices.
1683 */
1684 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1685 pci_resource_len(pdev, bar) < SZ_512K ||
1686 bar != AHCI_PCI_BAR_STANDARD ||
1687 !(readl(addr: hpriv->mmio + AHCI_VSCAP) & 1))
1688 return;
1689
1690 cap = readq(addr: hpriv->mmio + AHCI_REMAP_CAP);
1691 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1692 if ((cap & (1 << i)) == 0)
1693 continue;
1694 if (readl(addr: hpriv->mmio + ahci_remap_dcc(i))
1695 != PCI_CLASS_STORAGE_EXPRESS)
1696 continue;
1697
1698 /* We've found a remapped device */
1699 hpriv->remapped_nvme++;
1700 }
1701
1702 if (!hpriv->remapped_nvme)
1703 return;
1704
1705 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1706 hpriv->remapped_nvme);
1707 dev_warn(&pdev->dev,
1708 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1709
1710 /*
1711 * Don't rely on the msi-x capability in the remap case,
1712 * share the legacy interrupt across ahci and remapped devices.
1713 */
1714 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1715}
1716
1717static int ahci_get_irq_vector(struct ata_host *host, int port)
1718{
1719 return pci_irq_vector(to_pci_dev(host->dev), nr: port);
1720}
1721
1722static void ahci_init_irq(struct pci_dev *pdev, unsigned int n_ports,
1723 struct ahci_host_priv *hpriv)
1724{
1725 int nvec;
1726
1727 if (hpriv->flags & AHCI_HFLAG_NO_MSI) {
1728 pci_alloc_irq_vectors(dev: pdev, min_vecs: 1, max_vecs: 1, PCI_IRQ_INTX);
1729 return;
1730 }
1731
1732 /*
1733 * If number of MSIs is less than number of ports then Sharing Last
1734 * Message mode could be enforced. In this case assume that advantage
1735 * of multiple MSIs is negated and use single MSI mode instead.
1736 */
1737 if (n_ports > 1) {
1738 nvec = pci_alloc_irq_vectors(dev: pdev, min_vecs: n_ports, INT_MAX,
1739 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1740 if (nvec > 0) {
1741 if (!(readl(addr: hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1742 hpriv->get_irq_vector = ahci_get_irq_vector;
1743 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1744 return;
1745 }
1746
1747 /*
1748 * Fallback to single MSI mode if the controller
1749 * enforced MRSM mode.
1750 */
1751 printk(KERN_INFO
1752 "ahci: MRSM is on, fallback to single MSI\n");
1753 pci_free_irq_vectors(dev: pdev);
1754 }
1755 }
1756
1757 /*
1758 * If the host is not capable of supporting per-port vectors, fall
1759 * back to single MSI before finally attempting single MSI-X or
1760 * a legacy INTx.
1761 */
1762 nvec = pci_alloc_irq_vectors(dev: pdev, min_vecs: 1, max_vecs: 1, PCI_IRQ_MSI);
1763 if (nvec == 1)
1764 return;
1765 pci_alloc_irq_vectors(dev: pdev, min_vecs: 1, max_vecs: 1, PCI_IRQ_MSIX | PCI_IRQ_INTX);
1766}
1767
1768static void ahci_mark_external_port(struct ata_port *ap)
1769{
1770 struct ahci_host_priv *hpriv = ap->host->private_data;
1771 void __iomem *port_mmio = ahci_port_base(ap);
1772 u32 tmp;
1773
1774 /*
1775 * Mark external ports (hotplug-capable, eSATA), unless we were asked to
1776 * ignore this feature.
1777 */
1778 tmp = readl(addr: port_mmio + PORT_CMD);
1779 if (((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) ||
1780 (tmp & PORT_CMD_HPCP)) {
1781 if (hpriv->mask_port_ext & (1U << ap->port_no)) {
1782 ata_port_info(ap,
1783 "Ignoring external/hotplug capability\n");
1784 return;
1785 }
1786 ap->pflags |= ATA_PFLAG_EXTERNAL;
1787 }
1788}
1789
1790static void ahci_update_initial_lpm_policy(struct ata_port *ap)
1791{
1792 struct ahci_host_priv *hpriv = ap->host->private_data;
1793 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1794
1795 /*
1796 * AHCI contains a known incompatibility between LPM and hot-plug
1797 * removal events, see 7.3.1 Hot Plug Removal Detection and Power
1798 * Management Interaction in AHCI 1.3.1. Therefore, do not enable
1799 * LPM if the port advertises itself as an external port.
1800 */
1801 if (ap->pflags & ATA_PFLAG_EXTERNAL) {
1802 ap->flags |= ATA_FLAG_NO_LPM;
1803 ap->target_lpm_policy = ATA_LPM_MAX_POWER;
1804 return;
1805 }
1806
1807 /* If no Partial or no Slumber, we cannot support DIPM. */
1808 if ((ap->host->flags & ATA_HOST_NO_PART) ||
1809 (ap->host->flags & ATA_HOST_NO_SSC)) {
1810 ata_port_dbg(ap, "Host does not support DIPM\n");
1811 ap->flags |= ATA_FLAG_NO_DIPM;
1812 }
1813
1814 /* If no LPM states are supported by the HBA, do not bother with LPM */
1815 if ((ap->host->flags & ATA_HOST_NO_PART) &&
1816 (ap->host->flags & ATA_HOST_NO_SSC) &&
1817 (ap->host->flags & ATA_HOST_NO_DEVSLP)) {
1818 ata_port_dbg(ap,
1819 "No LPM states supported, forcing LPM max_power\n");
1820 ap->flags |= ATA_FLAG_NO_LPM;
1821 ap->target_lpm_policy = ATA_LPM_MAX_POWER;
1822 return;
1823 }
1824
1825 /* user modified policy via module param */
1826 if (mobile_lpm_policy != -1) {
1827 policy = mobile_lpm_policy;
1828 goto update_policy;
1829 }
1830
1831 if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) {
1832 if (hpriv->cap & HOST_CAP_PART)
1833 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1834 else if (hpriv->cap & HOST_CAP_SSC)
1835 policy = ATA_LPM_MIN_POWER;
1836 }
1837
1838update_policy:
1839 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1840 ap->target_lpm_policy = policy;
1841}
1842
1843static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1844{
1845 u16 tmp16;
1846
1847 if (!(hpriv->flags & AHCI_HFLAG_INTEL_PCS_QUIRK))
1848 return;
1849
1850 /*
1851 * port_map is determined from PORTS_IMPL PCI register which is
1852 * implemented as write or write-once register. If the register
1853 * isn't programmed, ahci automatically generates it from number
1854 * of ports, which is good enough for PCS programming. It is
1855 * otherwise expected that platform firmware enables the ports
1856 * before the OS boots.
1857 */
1858 pci_read_config_word(dev: pdev, where: PCS_6, val: &tmp16);
1859 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1860 tmp16 |= hpriv->port_map;
1861 pci_write_config_word(dev: pdev, where: PCS_6, val: tmp16);
1862 }
1863}
1864
1865static ssize_t remapped_nvme_show(struct device *dev,
1866 struct device_attribute *attr,
1867 char *buf)
1868{
1869 struct ata_host *host = dev_get_drvdata(dev);
1870 struct ahci_host_priv *hpriv = host->private_data;
1871
1872 return sysfs_emit(buf, fmt: "%u\n", hpriv->remapped_nvme);
1873}
1874
1875static DEVICE_ATTR_RO(remapped_nvme);
1876
1877static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1878{
1879 unsigned int board_id = ent->driver_data;
1880 struct ata_port_info pi = ahci_port_info[board_id];
1881 const struct ata_port_info *ppi[] = { &pi, NULL };
1882 struct device *dev = &pdev->dev;
1883 struct ahci_host_priv *hpriv;
1884 struct ata_host *host;
1885 int n_ports, i, rc;
1886 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1887
1888 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1889
1890 ata_print_version_once(dev: &pdev->dev, DRV_VERSION);
1891
1892 /* The AHCI driver can only drive the SATA ports, the PATA driver
1893 can drive them all so if both drivers are selected make sure
1894 AHCI stays out of the way */
1895 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1896 return -ENODEV;
1897
1898 /* Apple BIOS on MCP89 prevents us using AHCI */
1899 if (is_mcp89_apple(pdev))
1900 ahci_mcp89_apple_enable(pdev);
1901
1902 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1903 * At the moment, we can only use the AHCI mode. Let the users know
1904 * that for SAS drives they're out of luck.
1905 */
1906 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1907 dev_info(&pdev->dev,
1908 "PDC42819 can only drive SATA devices with this driver\n");
1909
1910 /* Some devices use non-standard BARs */
1911 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1912 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1913 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1914 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1915 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1916 if (pdev->device == 0xa01c)
1917 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1918 if (pdev->device == 0xa084)
1919 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1920 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1921 if (pdev->device == 0x7a08)
1922 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1923 }
1924
1925 /* acquire resources */
1926 rc = pcim_enable_device(pdev);
1927 if (rc)
1928 return rc;
1929
1930 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1931 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1932 u8 map;
1933
1934 /* ICH6s share the same PCI ID for both piix and ahci
1935 * modes. Enabling ahci mode while MAP indicates
1936 * combined mode is a bad idea. Yield to ata_piix.
1937 */
1938 pci_read_config_byte(dev: pdev, where: ICH_MAP, val: &map);
1939 if (map & 0x3) {
1940 dev_info(&pdev->dev,
1941 "controller is in combined mode, can't enable AHCI mode\n");
1942 return -ENODEV;
1943 }
1944 }
1945
1946 /* AHCI controllers often implement SFF compatible interface.
1947 * Grab all PCI BARs just in case.
1948 */
1949 rc = pcim_request_all_regions(pdev, DRV_NAME);
1950 if (rc == -EBUSY)
1951 pcim_pin_device(pdev);
1952 if (rc)
1953 return rc;
1954
1955 hpriv = devm_kzalloc(dev, size: sizeof(*hpriv), GFP_KERNEL);
1956 if (!hpriv)
1957 return -ENOMEM;
1958 hpriv->flags |= (unsigned long)pi.private_data;
1959
1960 /* MCP65 revision A1 and A2 can't do MSI */
1961 if (board_id == board_ahci_mcp65 &&
1962 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1963 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1964
1965 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1966 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1967 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1968
1969 /* only some SB600s can do 64bit DMA */
1970 if (ahci_sb600_enable_64bit(pdev))
1971 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1972
1973 hpriv->mmio = pcim_iomap(pdev, bar: ahci_pci_bar, maxlen: 0);
1974 if (!hpriv->mmio)
1975 return -ENOMEM;
1976
1977 /* detect remapped nvme devices */
1978 ahci_remap_check(pdev, bar: ahci_pci_bar, hpriv);
1979
1980 sysfs_add_file_to_group(kobj: &pdev->dev.kobj,
1981 attr: &dev_attr_remapped_nvme.attr,
1982 NULL);
1983
1984#ifdef CONFIG_ARM64
1985 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1986 pdev->device == 0xa235 &&
1987 pdev->revision < 0x30)
1988 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1989
1990 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1991 hpriv->irq_handler = ahci_thunderx_irq_handler;
1992#endif
1993
1994 /* save initial config */
1995 ahci_pci_save_initial_config(pdev, hpriv);
1996
1997 /* prepare host */
1998 if (hpriv->cap & HOST_CAP_NCQ) {
1999 pi.flags |= ATA_FLAG_NCQ;
2000 /*
2001 * Auto-activate optimization is supposed to be
2002 * supported on all AHCI controllers indicating NCQ
2003 * capability, but it seems to be broken on some
2004 * chipsets including NVIDIAs.
2005 */
2006 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
2007 pi.flags |= ATA_FLAG_FPDMA_AA;
2008
2009 /*
2010 * All AHCI controllers should be forward-compatible
2011 * with the new auxiliary field. This code should be
2012 * conditionalized if any buggy AHCI controllers are
2013 * encountered.
2014 */
2015 pi.flags |= ATA_FLAG_FPDMA_AUX;
2016 }
2017
2018 if (hpriv->cap & HOST_CAP_PMP)
2019 pi.flags |= ATA_FLAG_PMP;
2020
2021 ahci_set_em_messages(hpriv, pi: &pi);
2022
2023 if (ahci_broken_system_poweroff(pdev)) {
2024 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
2025 dev_info(&pdev->dev,
2026 "quirky BIOS, skipping spindown on poweroff\n");
2027 }
2028
2029 if (ahci_broken_lpm(pdev)) {
2030 pi.flags |= ATA_FLAG_NO_LPM;
2031 dev_warn(&pdev->dev,
2032 "BIOS update required for Link Power Management support\n");
2033 }
2034
2035 if (ahci_broken_suspend(pdev)) {
2036 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
2037 dev_warn(&pdev->dev,
2038 "BIOS update required for suspend/resume\n");
2039 }
2040
2041 if (ahci_broken_online(pdev)) {
2042 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
2043 dev_info(&pdev->dev,
2044 "online status unreliable, applying workaround\n");
2045 }
2046
2047
2048 /* Acer SA5-271 workaround modifies private_data */
2049 acer_sa5_271_workaround(hpriv, pdev);
2050
2051 /* CAP.NP sometimes indicate the index of the last enabled
2052 * port, at other times, that of the last possible port, so
2053 * determining the maximum port number requires looking at
2054 * both CAP.NP and port_map.
2055 */
2056 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2057
2058 host = ata_host_alloc_pinfo(dev: &pdev->dev, ppi, n_ports);
2059 if (!host) {
2060 rc = -ENOMEM;
2061 goto err_rm_sysfs_file;
2062 }
2063 host->private_data = hpriv;
2064
2065 ahci_init_irq(pdev, n_ports, hpriv);
2066
2067 hpriv->irq = pci_irq_vector(dev: pdev, nr: 0);
2068
2069 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
2070 host->flags |= ATA_HOST_PARALLEL_SCAN;
2071 else
2072 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
2073
2074 if (!(hpriv->cap & HOST_CAP_PART))
2075 host->flags |= ATA_HOST_NO_PART;
2076
2077 if (!(hpriv->cap & HOST_CAP_SSC))
2078 host->flags |= ATA_HOST_NO_SSC;
2079
2080 if (!(hpriv->cap2 & HOST_CAP2_SDS))
2081 host->flags |= ATA_HOST_NO_DEVSLP;
2082
2083 if (pi.flags & ATA_FLAG_EM)
2084 ahci_reset_em(host);
2085
2086 for (i = 0; i < host->n_ports; i++) {
2087 struct ata_port *ap = host->ports[i];
2088
2089 ata_port_pbar_desc(ap, bar: ahci_pci_bar, offset: -1, name: "abar");
2090 ata_port_pbar_desc(ap, bar: ahci_pci_bar,
2091 offset: 0x100 + ap->port_no * 0x80, name: "port");
2092
2093 /* set enclosure management message type */
2094 if (ap->flags & ATA_FLAG_EM)
2095 ap->em_message_type = hpriv->em_msg_type;
2096
2097 ahci_mark_external_port(ap);
2098
2099 ahci_update_initial_lpm_policy(ap);
2100
2101 /* disabled/not-implemented port */
2102 if (!(hpriv->port_map & (1 << i)))
2103 ap->ops = &ata_dummy_port_ops;
2104 }
2105
2106 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2107 ahci_p5wdh_workaround(host);
2108
2109 /* apply gtf filter quirk */
2110 ahci_gtf_filter_workaround(host);
2111
2112 /* initialize adapter */
2113 rc = ahci_configure_dma_masks(pdev, hpriv);
2114 if (rc)
2115 goto err_rm_sysfs_file;
2116
2117 rc = ahci_pci_reset_controller(host);
2118 if (rc)
2119 goto err_rm_sysfs_file;
2120
2121 ahci_pci_init_controller(host);
2122 ahci_pci_print_info(host);
2123
2124 pci_set_master(dev: pdev);
2125
2126 rc = ahci_host_activate(host, sht: &ahci_sht);
2127 if (rc)
2128 goto err_rm_sysfs_file;
2129
2130 pm_runtime_put_noidle(dev: &pdev->dev);
2131 return 0;
2132
2133err_rm_sysfs_file:
2134 sysfs_remove_file_from_group(kobj: &pdev->dev.kobj,
2135 attr: &dev_attr_remapped_nvme.attr, NULL);
2136 return rc;
2137}
2138
2139static void ahci_shutdown_one(struct pci_dev *pdev)
2140{
2141 ata_pci_shutdown_one(pdev);
2142}
2143
2144static void ahci_remove_one(struct pci_dev *pdev)
2145{
2146 sysfs_remove_file_from_group(kobj: &pdev->dev.kobj,
2147 attr: &dev_attr_remapped_nvme.attr,
2148 NULL);
2149 pm_runtime_get_noresume(dev: &pdev->dev);
2150 ata_pci_remove_one(pdev);
2151}
2152
2153module_pci_driver(ahci_pci_driver);
2154
2155MODULE_AUTHOR("Jeff Garzik");
2156MODULE_DESCRIPTION("AHCI SATA low-level driver");
2157MODULE_LICENSE("GPL");
2158MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2159MODULE_VERSION(DRV_VERSION);
2160