1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright 2001-2003 SuSE Labs.
4 * Distributed under the GNU public license, v2.
5 *
6 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
7 * It also includes support for the AMD 8151 AGP bridge,
8 * although it doesn't actually do much, as all the real
9 * work is done in the northbridge(s).
10 */
11
12#include <linux/module.h>
13#include <linux/pci.h>
14#include <linux/init.h>
15#include <linux/agp_backend.h>
16#include <linux/mmzone.h>
17#include <asm/page.h> /* PAGE_SIZE */
18#include <asm/e820/api.h>
19#include <asm/amd/nb.h>
20#include <asm/gart.h>
21#include "agp.h"
22
23/* NVIDIA K8 registers */
24#define NVIDIA_X86_64_0_APBASE 0x10
25#define NVIDIA_X86_64_1_APBASE1 0x50
26#define NVIDIA_X86_64_1_APLIMIT1 0x54
27#define NVIDIA_X86_64_1_APSIZE 0xa8
28#define NVIDIA_X86_64_1_APBASE2 0xd8
29#define NVIDIA_X86_64_1_APLIMIT2 0xdc
30
31/* ULi K8 registers */
32#define ULI_X86_64_BASE_ADDR 0x10
33#define ULI_X86_64_HTT_FEA_REG 0x50
34#define ULI_X86_64_ENU_SCR_REG 0x54
35
36static struct resource *aperture_resource;
37static bool __initdata agp_try_unsupported = 1;
38static int agp_bridges_found;
39
40static void amd64_tlbflush(struct agp_memory *temp)
41{
42 amd_flush_garts();
43}
44
45static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
46{
47 int i, j, num_entries;
48 long long tmp;
49 int mask_type;
50 struct agp_bridge_data *bridge = mem->bridge;
51 u32 pte;
52
53 num_entries = agp_num_entries();
54
55 if (type != mem->type)
56 return -EINVAL;
57 mask_type = bridge->driver->agp_type_to_mask_type(bridge, type);
58 if (mask_type != 0)
59 return -EINVAL;
60
61
62 /* Make sure we can fit the range in the gatt table. */
63 /* FIXME: could wrap */
64 if (((unsigned long)pg_start + mem->page_count) > num_entries)
65 return -EINVAL;
66
67 j = pg_start;
68
69 /* gatt table should be empty. */
70 while (j < (pg_start + mem->page_count)) {
71 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
72 return -EBUSY;
73 j++;
74 }
75
76 if (!mem->is_flushed) {
77 global_cache_flush();
78 mem->is_flushed = true;
79 }
80
81 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
82 tmp = agp_bridge->driver->mask_memory(agp_bridge,
83 page_to_phys(mem->pages[i]),
84 mask_type);
85
86 BUG_ON(tmp & 0xffffff0000000ffcULL);
87 pte = (tmp & 0x000000ff00000000ULL) >> 28;
88 pte |=(tmp & 0x00000000fffff000ULL);
89 pte |= GPTE_VALID | GPTE_COHERENT;
90
91 writel(val: pte, addr: agp_bridge->gatt_table+j);
92 readl(addr: agp_bridge->gatt_table+j); /* PCI Posting. */
93 }
94 amd64_tlbflush(temp: mem);
95 return 0;
96}
97
98/*
99 * This hack alters the order element according
100 * to the size of a long. It sucks. I totally disown this, even
101 * though it does appear to work for the most part.
102 */
103static struct aper_size_info_32 amd64_aperture_sizes[7] =
104{
105 {32, 8192, 3+(sizeof(long)/8), 0 },
106 {.size: 64, .num_entries: 16384, .page_order: 4+(sizeof(long)/8), .size_value: 1<<1 },
107 {.size: 128, .num_entries: 32768, .page_order: 5+(sizeof(long)/8), .size_value: 1<<2 },
108 {.size: 256, .num_entries: 65536, .page_order: 6+(sizeof(long)/8), .size_value: 1<<1 | 1<<2 },
109 {.size: 512, .num_entries: 131072, .page_order: 7+(sizeof(long)/8), .size_value: 1<<3 },
110 {.size: 1024, .num_entries: 262144, .page_order: 8+(sizeof(long)/8), .size_value: 1<<1 | 1<<3},
111 {.size: 2048, .num_entries: 524288, .page_order: 9+(sizeof(long)/8), .size_value: 1<<2 | 1<<3}
112};
113
114
115/*
116 * Get the current Aperture size from the x86-64.
117 * Note, that there may be multiple x86-64's, but we just return
118 * the value from the first one we find. The set_size functions
119 * keep the rest coherent anyway. Or at least should do.
120 */
121static int amd64_fetch_size(void)
122{
123 struct pci_dev *dev;
124 int i;
125 u32 temp;
126 struct aper_size_info_32 *values;
127
128 dev = node_to_amd_nb(node: 0)->misc;
129 if (dev==NULL)
130 return 0;
131
132 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, val: &temp);
133 temp = (temp & 0xe);
134 values = A_SIZE_32(amd64_aperture_sizes);
135
136 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
137 if (temp == values[i].size_value) {
138 agp_bridge->previous_size =
139 agp_bridge->current_size = (void *) (values + i);
140
141 agp_bridge->aperture_size_idx = i;
142 return values[i].size;
143 }
144 }
145 return 0;
146}
147
148/*
149 * In a multiprocessor x86-64 system, this function gets
150 * called once for each CPU.
151 */
152static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table)
153{
154 u64 aperturebase;
155 u32 tmp;
156 u64 aper_base;
157
158 /* Address to map to */
159 pci_read_config_dword(dev: hammer, AMD64_GARTAPERTUREBASE, val: &tmp);
160 aperturebase = (u64)tmp << 25;
161 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
162
163 enable_gart_translation(dev: hammer, addr: gatt_table);
164
165 return aper_base;
166}
167
168
169static const struct aper_size_info_32 amd_8151_sizes[7] =
170{
171 {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */
172 {.size: 1024, .num_entries: 262144, .page_order: 8, .size_value: 0x00000400 }, /* 1 0 0 0 0 0 */
173 {.size: 512, .num_entries: 131072, .page_order: 7, .size_value: 0x00000600 }, /* 1 1 0 0 0 0 */
174 {.size: 256, .num_entries: 65536, .page_order: 6, .size_value: 0x00000700 }, /* 1 1 1 0 0 0 */
175 {.size: 128, .num_entries: 32768, .page_order: 5, .size_value: 0x00000720 }, /* 1 1 1 1 0 0 */
176 {.size: 64, .num_entries: 16384, .page_order: 4, .size_value: 0x00000730 }, /* 1 1 1 1 1 0 */
177 {.size: 32, .num_entries: 8192, .page_order: 3, .size_value: 0x00000738 } /* 1 1 1 1 1 1 */
178};
179
180static int amd_8151_configure(void)
181{
182 unsigned long gatt_bus = virt_to_phys(address: agp_bridge->gatt_table_real);
183 int i;
184
185 if (!amd_nb_has_feature(AMD_NB_GART))
186 return 0;
187
188 /* Configure AGP regs in each x86-64 host bridge. */
189 for (i = 0; i < amd_nb_num(); i++) {
190 agp_bridge->gart_bus_addr =
191 amd64_configure(hammer: node_to_amd_nb(node: i)->misc, gatt_table: gatt_bus);
192 }
193 amd_flush_garts();
194 return 0;
195}
196
197
198static void amd64_cleanup(void)
199{
200 u32 tmp;
201 int i;
202
203 if (!amd_nb_has_feature(AMD_NB_GART))
204 return;
205
206 for (i = 0; i < amd_nb_num(); i++) {
207 struct pci_dev *dev = node_to_amd_nb(node: i)->misc;
208 /* disable gart translation */
209 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, val: &tmp);
210 tmp &= ~GARTEN;
211 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, val: tmp);
212 }
213}
214
215
216static const struct agp_bridge_driver amd_8151_driver = {
217 .owner = THIS_MODULE,
218 .aperture_sizes = amd_8151_sizes,
219 .size_type = U32_APER_SIZE,
220 .num_aperture_sizes = 7,
221 .needs_scratch_page = true,
222 .configure = amd_8151_configure,
223 .fetch_size = amd64_fetch_size,
224 .cleanup = amd64_cleanup,
225 .tlb_flush = amd64_tlbflush,
226 .mask_memory = agp_generic_mask_memory,
227 .masks = NULL,
228 .agp_enable = agp_generic_enable,
229 .cache_flush = global_cache_flush,
230 .create_gatt_table = agp_generic_create_gatt_table,
231 .free_gatt_table = agp_generic_free_gatt_table,
232 .insert_memory = amd64_insert_memory,
233 .remove_memory = agp_generic_remove_memory,
234 .alloc_by_type = agp_generic_alloc_by_type,
235 .free_by_type = agp_generic_free_by_type,
236 .agp_alloc_page = agp_generic_alloc_page,
237 .agp_alloc_pages = agp_generic_alloc_pages,
238 .agp_destroy_page = agp_generic_destroy_page,
239 .agp_destroy_pages = agp_generic_destroy_pages,
240 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
241};
242
243/* Some basic sanity checks for the aperture. */
244static int agp_aperture_valid(u64 aper, u32 size)
245{
246 if (!aperture_valid(aper_base: aper, aper_size: size, min_size: 32*1024*1024))
247 return 0;
248
249 /* Request the Aperture. This catches cases when someone else
250 already put a mapping in there - happens with some very broken BIOS
251
252 Maybe better to use pci_assign_resource/pci_enable_device instead
253 trusting the bridges? */
254 if (!aperture_resource &&
255 !(aperture_resource = request_mem_region(aper, size, "aperture"))) {
256 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
257 return 0;
258 }
259 return 1;
260}
261
262/*
263 * W*s centric BIOS sometimes only set up the aperture in the AGP
264 * bridge, not the northbridge. On AMD64 this is handled early
265 * in aperture.c, but when IOMMU is not enabled or we run
266 * on a 32bit kernel this needs to be redone.
267 * Unfortunately it is impossible to fix the aperture here because it's too late
268 * to allocate that much memory. But at least error out cleanly instead of
269 * crashing.
270 */
271static int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, u16 cap)
272{
273 u64 aper, nb_aper;
274 int order = 0;
275 u32 nb_order, nb_base;
276 u16 apsize;
277
278 pci_read_config_dword(dev: nb, AMD64_GARTAPERTURECTL, val: &nb_order);
279 nb_order = (nb_order >> 1) & 7;
280 pci_read_config_dword(dev: nb, AMD64_GARTAPERTUREBASE, val: &nb_base);
281 nb_aper = (u64)nb_base << 25;
282
283 /* Northbridge seems to contain crap. Try the AGP bridge. */
284
285 pci_read_config_word(dev: agp, where: cap+0x14, val: &apsize);
286 if (apsize == 0xffff) {
287 if (agp_aperture_valid(aper: nb_aper, size: (32*1024*1024)<<nb_order))
288 return 0;
289 return -1;
290 }
291
292 apsize &= 0xfff;
293 /* Some BIOS use weird encodings not in the AGPv3 table. */
294 if (apsize & 0xff)
295 apsize |= 0xf00;
296 order = 7 - hweight16(apsize);
297
298 aper = pci_bus_address(pdev: agp, AGP_APERTURE_BAR);
299
300 /*
301 * On some sick chips APSIZE is 0. This means it wants 4G
302 * so let double check that order, and lets trust the AMD NB settings
303 */
304 if (order >=0 && aper + (32ULL<<(20 + order)) > 0x100000000ULL) {
305 dev_info(&agp->dev, "aperture size %u MB is not right, using settings from NB\n",
306 32 << order);
307 order = nb_order;
308 }
309
310 if (nb_order >= order) {
311 if (agp_aperture_valid(aper: nb_aper, size: (32*1024*1024)<<nb_order))
312 return 0;
313 }
314
315 dev_info(&agp->dev, "aperture from AGP @ %Lx size %u MB\n",
316 aper, 32 << order);
317 if (order < 0 || !agp_aperture_valid(aper, size: (32*1024*1024)<<order))
318 return -1;
319
320 gart_set_size_and_enable(dev: nb, order);
321 pci_write_config_dword(dev: nb, AMD64_GARTAPERTUREBASE, val: aper >> 25);
322
323 return 0;
324}
325
326static int cache_nbs(struct pci_dev *pdev, u32 cap_ptr)
327{
328 int i;
329
330 if (!amd_nb_num())
331 return -ENODEV;
332
333 if (!amd_nb_has_feature(AMD_NB_GART))
334 return -ENODEV;
335
336 i = 0;
337 for (i = 0; i < amd_nb_num(); i++) {
338 struct pci_dev *dev = node_to_amd_nb(node: i)->misc;
339 if (fix_northbridge(nb: dev, agp: pdev, cap: cap_ptr) < 0) {
340 dev_err(&dev->dev, "no usable aperture found\n");
341#ifdef __x86_64__
342 /* should port this to i386 */
343 dev_err(&dev->dev, "consider rebooting with iommu=memaper=2 to get a good aperture\n");
344#endif
345 return -1;
346 }
347 }
348 return 0;
349}
350
351/* Handle AMD 8151 quirks */
352static void amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
353{
354 char *revstring;
355
356 switch (pdev->revision) {
357 case 0x01: revstring="A0"; break;
358 case 0x02: revstring="A1"; break;
359 case 0x11: revstring="B0"; break;
360 case 0x12: revstring="B1"; break;
361 case 0x13: revstring="B2"; break;
362 case 0x14: revstring="B3"; break;
363 default: revstring="??"; break;
364 }
365
366 dev_info(&pdev->dev, "AMD 8151 AGP Bridge rev %s\n", revstring);
367
368 /*
369 * Work around errata.
370 * Chips before B2 stepping incorrectly reporting v3.5
371 */
372 if (pdev->revision < 0x13) {
373 dev_info(&pdev->dev, "correcting AGP revision (reports 3.5, is really 3.0)\n");
374 bridge->major_version = 3;
375 bridge->minor_version = 0;
376 }
377}
378
379
380static const struct aper_size_info_32 uli_sizes[7] =
381{
382 {256, 65536, 6, 10},
383 {.size: 128, .num_entries: 32768, .page_order: 5, .size_value: 9},
384 {.size: 64, .num_entries: 16384, .page_order: 4, .size_value: 8},
385 {.size: 32, .num_entries: 8192, .page_order: 3, .size_value: 7},
386 {.size: 16, .num_entries: 4096, .page_order: 2, .size_value: 6},
387 {.size: 8, .num_entries: 2048, .page_order: 1, .size_value: 4},
388 {.size: 4, .num_entries: 1024, .page_order: 0, .size_value: 3}
389};
390static int uli_agp_init(struct pci_dev *pdev)
391{
392 u32 httfea,baseaddr,enuscr;
393 struct pci_dev *dev1;
394 int i, ret;
395 unsigned size = amd64_fetch_size();
396
397 dev_info(&pdev->dev, "setting up ULi AGP\n");
398 dev1 = pci_get_slot (bus: pdev->bus,PCI_DEVFN(0,0));
399 if (dev1 == NULL) {
400 dev_info(&pdev->dev, "can't find ULi secondary device\n");
401 return -ENODEV;
402 }
403
404 for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
405 if (uli_sizes[i].size == size)
406 break;
407
408 if (i == ARRAY_SIZE(uli_sizes)) {
409 dev_info(&pdev->dev, "no ULi size found for %d\n", size);
410 ret = -ENODEV;
411 goto put;
412 }
413
414 /* shadow x86-64 registers into ULi registers */
415 pci_read_config_dword (dev: node_to_amd_nb(node: 0)->misc, AMD64_GARTAPERTUREBASE,
416 val: &httfea);
417
418 /* if x86-64 aperture base is beyond 4G, exit here */
419 if ((httfea & 0x7fff) >> (32 - 25)) {
420 ret = -ENODEV;
421 goto put;
422 }
423
424 httfea = (httfea& 0x7fff) << 25;
425
426 pci_read_config_dword(dev: pdev, ULI_X86_64_BASE_ADDR, val: &baseaddr);
427 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
428 baseaddr|= httfea;
429 pci_write_config_dword(dev: pdev, ULI_X86_64_BASE_ADDR, val: baseaddr);
430
431 enuscr= httfea+ (size * 1024 * 1024) - 1;
432 pci_write_config_dword(dev: dev1, ULI_X86_64_HTT_FEA_REG, val: httfea);
433 pci_write_config_dword(dev: dev1, ULI_X86_64_ENU_SCR_REG, val: enuscr);
434 ret = 0;
435put:
436 pci_dev_put(dev: dev1);
437 return ret;
438}
439
440
441static const struct aper_size_info_32 nforce3_sizes[5] =
442{
443 {512, 131072, 7, 0x00000000 },
444 {.size: 256, .num_entries: 65536, .page_order: 6, .size_value: 0x00000008 },
445 {.size: 128, .num_entries: 32768, .page_order: 5, .size_value: 0x0000000C },
446 {.size: 64, .num_entries: 16384, .page_order: 4, .size_value: 0x0000000E },
447 {.size: 32, .num_entries: 8192, .page_order: 3, .size_value: 0x0000000F }
448};
449
450/* Handle shadow device of the Nvidia NForce3 */
451/* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
452static int nforce3_agp_init(struct pci_dev *pdev)
453{
454 u32 tmp, apbase, apbar, aplimit;
455 struct pci_dev *dev1;
456 int i, ret;
457 unsigned size = amd64_fetch_size();
458
459 dev_info(&pdev->dev, "setting up Nforce3 AGP\n");
460
461 dev1 = pci_get_slot(bus: pdev->bus, PCI_DEVFN(11, 0));
462 if (dev1 == NULL) {
463 dev_info(&pdev->dev, "can't find Nforce3 secondary device\n");
464 return -ENODEV;
465 }
466
467 for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
468 if (nforce3_sizes[i].size == size)
469 break;
470
471 if (i == ARRAY_SIZE(nforce3_sizes)) {
472 dev_info(&pdev->dev, "no NForce3 size found for %d\n", size);
473 ret = -ENODEV;
474 goto put;
475 }
476
477 pci_read_config_dword(dev: dev1, NVIDIA_X86_64_1_APSIZE, val: &tmp);
478 tmp &= ~(0xf);
479 tmp |= nforce3_sizes[i].size_value;
480 pci_write_config_dword(dev: dev1, NVIDIA_X86_64_1_APSIZE, val: tmp);
481
482 /* shadow x86-64 registers into NVIDIA registers */
483 pci_read_config_dword (dev: node_to_amd_nb(node: 0)->misc, AMD64_GARTAPERTUREBASE,
484 val: &apbase);
485
486 /* if x86-64 aperture base is beyond 4G, exit here */
487 if ( (apbase & 0x7fff) >> (32 - 25) ) {
488 dev_info(&pdev->dev, "aperture base > 4G\n");
489 ret = -ENODEV;
490 goto put;
491 }
492
493 apbase = (apbase & 0x7fff) << 25;
494
495 pci_read_config_dword(dev: pdev, NVIDIA_X86_64_0_APBASE, val: &apbar);
496 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
497 apbar |= apbase;
498 pci_write_config_dword(dev: pdev, NVIDIA_X86_64_0_APBASE, val: apbar);
499
500 aplimit = apbase + (size * 1024 * 1024) - 1;
501 pci_write_config_dword(dev: dev1, NVIDIA_X86_64_1_APBASE1, val: apbase);
502 pci_write_config_dword(dev: dev1, NVIDIA_X86_64_1_APLIMIT1, val: aplimit);
503 pci_write_config_dword(dev: dev1, NVIDIA_X86_64_1_APBASE2, val: apbase);
504 pci_write_config_dword(dev: dev1, NVIDIA_X86_64_1_APLIMIT2, val: aplimit);
505
506 ret = 0;
507put:
508 pci_dev_put(dev: dev1);
509
510 return ret;
511}
512
513static int agp_amd64_probe(struct pci_dev *pdev,
514 const struct pci_device_id *ent)
515{
516 struct agp_bridge_data *bridge;
517 u8 cap_ptr;
518 int err;
519
520 /* The Highlander principle */
521 if (agp_bridges_found)
522 return -ENODEV;
523
524 cap_ptr = pci_find_capability(dev: pdev, PCI_CAP_ID_AGP);
525 if (!cap_ptr)
526 return -ENODEV;
527
528 /* Could check for AGPv3 here */
529
530 bridge = agp_alloc_bridge();
531 if (!bridge)
532 return -ENOMEM;
533
534 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
535 pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
536 amd8151_init(pdev, bridge);
537 } else {
538 dev_info(&pdev->dev, "AGP bridge [%04x/%04x]\n",
539 pdev->vendor, pdev->device);
540 }
541
542 bridge->driver = &amd_8151_driver;
543 bridge->dev = pdev;
544 bridge->capndx = cap_ptr;
545
546 /* Fill in the mode register */
547 pci_read_config_dword(dev: pdev, where: bridge->capndx+PCI_AGP_STATUS, val: &bridge->mode);
548
549 if (cache_nbs(pdev, cap_ptr) == -1) {
550 agp_put_bridge(bridge);
551 return -ENODEV;
552 }
553
554 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
555 int ret = nforce3_agp_init(pdev);
556 if (ret) {
557 agp_put_bridge(bridge);
558 return ret;
559 }
560 }
561
562 if (pdev->vendor == PCI_VENDOR_ID_AL) {
563 int ret = uli_agp_init(pdev);
564 if (ret) {
565 agp_put_bridge(bridge);
566 return ret;
567 }
568 }
569
570 pci_set_drvdata(pdev, data: bridge);
571 err = agp_add_bridge(bridge);
572 if (err < 0)
573 return err;
574
575 agp_bridges_found++;
576 return 0;
577}
578
579static void agp_amd64_remove(struct pci_dev *pdev)
580{
581 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
582
583 release_mem_region(virt_to_phys(bridge->gatt_table_real),
584 amd64_aperture_sizes[bridge->aperture_size_idx].size);
585 agp_remove_bridge(bridge);
586 agp_put_bridge(bridge);
587
588 agp_bridges_found--;
589}
590
591static int agp_amd64_resume(struct device *dev)
592{
593 struct pci_dev *pdev = to_pci_dev(dev);
594
595 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA)
596 nforce3_agp_init(pdev);
597
598 return amd_8151_configure();
599}
600
601static const struct pci_device_id agp_amd64_pci_table[] = {
602 {
603 .class = (PCI_CLASS_BRIDGE_HOST << 8),
604 .class_mask = ~0,
605 .vendor = PCI_VENDOR_ID_AMD,
606 .device = PCI_DEVICE_ID_AMD_8151_0,
607 .subvendor = PCI_ANY_ID,
608 .subdevice = PCI_ANY_ID,
609 },
610 /* ULi M1689 */
611 {
612 .class = (PCI_CLASS_BRIDGE_HOST << 8),
613 .class_mask = ~0,
614 .vendor = PCI_VENDOR_ID_AL,
615 .device = PCI_DEVICE_ID_AL_M1689,
616 .subvendor = PCI_ANY_ID,
617 .subdevice = PCI_ANY_ID,
618 },
619 /* VIA K8T800Pro */
620 {
621 .class = (PCI_CLASS_BRIDGE_HOST << 8),
622 .class_mask = ~0,
623 .vendor = PCI_VENDOR_ID_VIA,
624 .device = PCI_DEVICE_ID_VIA_K8T800PRO_0,
625 .subvendor = PCI_ANY_ID,
626 .subdevice = PCI_ANY_ID,
627 },
628 /* VIA K8T800 */
629 {
630 .class = (PCI_CLASS_BRIDGE_HOST << 8),
631 .class_mask = ~0,
632 .vendor = PCI_VENDOR_ID_VIA,
633 .device = PCI_DEVICE_ID_VIA_8385_0,
634 .subvendor = PCI_ANY_ID,
635 .subdevice = PCI_ANY_ID,
636 },
637 /* VIA K8M800 / K8N800 */
638 {
639 .class = (PCI_CLASS_BRIDGE_HOST << 8),
640 .class_mask = ~0,
641 .vendor = PCI_VENDOR_ID_VIA,
642 .device = PCI_DEVICE_ID_VIA_8380_0,
643 .subvendor = PCI_ANY_ID,
644 .subdevice = PCI_ANY_ID,
645 },
646 /* VIA K8M890 / K8N890 */
647 {
648 .class = (PCI_CLASS_BRIDGE_HOST << 8),
649 .class_mask = ~0,
650 .vendor = PCI_VENDOR_ID_VIA,
651 .device = PCI_DEVICE_ID_VIA_VT3336,
652 .subvendor = PCI_ANY_ID,
653 .subdevice = PCI_ANY_ID,
654 },
655 /* VIA K8T890 */
656 {
657 .class = (PCI_CLASS_BRIDGE_HOST << 8),
658 .class_mask = ~0,
659 .vendor = PCI_VENDOR_ID_VIA,
660 .device = PCI_DEVICE_ID_VIA_3238_0,
661 .subvendor = PCI_ANY_ID,
662 .subdevice = PCI_ANY_ID,
663 },
664 /* VIA K8T800/K8M800/K8N800 */
665 {
666 .class = (PCI_CLASS_BRIDGE_HOST << 8),
667 .class_mask = ~0,
668 .vendor = PCI_VENDOR_ID_VIA,
669 .device = PCI_DEVICE_ID_VIA_838X_1,
670 .subvendor = PCI_ANY_ID,
671 .subdevice = PCI_ANY_ID,
672 },
673 /* NForce3 */
674 {
675 .class = (PCI_CLASS_BRIDGE_HOST << 8),
676 .class_mask = ~0,
677 .vendor = PCI_VENDOR_ID_NVIDIA,
678 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3,
679 .subvendor = PCI_ANY_ID,
680 .subdevice = PCI_ANY_ID,
681 },
682 {
683 .class = (PCI_CLASS_BRIDGE_HOST << 8),
684 .class_mask = ~0,
685 .vendor = PCI_VENDOR_ID_NVIDIA,
686 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S,
687 .subvendor = PCI_ANY_ID,
688 .subdevice = PCI_ANY_ID,
689 },
690 /* SIS 755 */
691 {
692 .class = (PCI_CLASS_BRIDGE_HOST << 8),
693 .class_mask = ~0,
694 .vendor = PCI_VENDOR_ID_SI,
695 .device = PCI_DEVICE_ID_SI_755,
696 .subvendor = PCI_ANY_ID,
697 .subdevice = PCI_ANY_ID,
698 },
699 /* SIS 760 */
700 {
701 .class = (PCI_CLASS_BRIDGE_HOST << 8),
702 .class_mask = ~0,
703 .vendor = PCI_VENDOR_ID_SI,
704 .device = PCI_DEVICE_ID_SI_760,
705 .subvendor = PCI_ANY_ID,
706 .subdevice = PCI_ANY_ID,
707 },
708 /* ALI/ULI M1695 */
709 {
710 .class = (PCI_CLASS_BRIDGE_HOST << 8),
711 .class_mask = ~0,
712 .vendor = PCI_VENDOR_ID_AL,
713 .device = 0x1695,
714 .subvendor = PCI_ANY_ID,
715 .subdevice = PCI_ANY_ID,
716 },
717
718 { }
719};
720
721MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
722
723static DEFINE_SIMPLE_DEV_PM_OPS(agp_amd64_pm_ops, NULL, agp_amd64_resume);
724
725static struct pci_driver agp_amd64_pci_driver = {
726 .name = "agpgart-amd64",
727 .id_table = agp_amd64_pci_table,
728 .probe = agp_amd64_probe,
729 .remove = agp_amd64_remove,
730 .driver.pm = &agp_amd64_pm_ops,
731};
732
733
734/* Not static due to IOMMU code calling it early. */
735int __init agp_amd64_init(void)
736{
737 struct pci_dev *pdev = NULL;
738 int err = 0;
739
740 if (agp_off)
741 return -EINVAL;
742
743 err = pci_register_driver(&agp_amd64_pci_driver);
744 if (err < 0)
745 return err;
746
747 if (agp_bridges_found == 0) {
748 if (!agp_try_unsupported && !agp_try_unsupported_boot) {
749 printk(KERN_INFO PFX "No supported AGP bridge found.\n");
750#ifdef MODULE
751 printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
752#else
753 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
754#endif
755 pci_unregister_driver(dev: &agp_amd64_pci_driver);
756 return -ENODEV;
757 }
758
759 /* First check that we have at least one AMD64 NB */
760 if (!amd_nb_num()) {
761 pci_unregister_driver(dev: &agp_amd64_pci_driver);
762 return -ENODEV;
763 }
764
765 /* Look for any AGP bridge */
766 for_each_pci_dev(pdev)
767 if (pci_find_capability(dev: pdev, PCI_CAP_ID_AGP))
768 pci_add_dynid(drv: &agp_amd64_pci_driver,
769 vendor: pdev->vendor, device: pdev->device,
770 subvendor: pdev->subsystem_vendor,
771 subdevice: pdev->subsystem_device, class: 0, class_mask: 0, driver_data: 0);
772 if (agp_bridges_found == 0) {
773 pci_unregister_driver(dev: &agp_amd64_pci_driver);
774 err = -ENODEV;
775 }
776 }
777 return err;
778}
779
780static int __init agp_amd64_mod_init(void)
781{
782#ifndef MODULE
783 if (gart_iommu_aperture)
784 return agp_bridges_found ? 0 : -ENODEV;
785#endif
786 return agp_amd64_init();
787}
788
789static void __exit agp_amd64_cleanup(void)
790{
791#ifndef MODULE
792 if (gart_iommu_aperture)
793 return;
794#endif
795 if (aperture_resource)
796 release_resource(new: aperture_resource);
797 pci_unregister_driver(dev: &agp_amd64_pci_driver);
798}
799
800module_init(agp_amd64_mod_init);
801module_exit(agp_amd64_cleanup);
802
803MODULE_AUTHOR("Dave Jones, Andi Kleen");
804module_param(agp_try_unsupported, bool, 0);
805MODULE_DESCRIPTION("GART driver for the AMD Opteron/Athlon64 on-CPU northbridge");
806MODULE_LICENSE("GPL");
807