1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2023 Intel Corporation
4 */
5
6#ifndef __INTEL_PSR_REGS_H__
7#define __INTEL_PSR_REGS_H__
8
9#include "intel_display_reg_defs.h"
10#include "intel_dp_aux_regs.h"
11
12#define _TRANS_EXITLINE_A 0x60018
13#define TRANS_EXITLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_EXITLINE_A)
14#define EXITLINE_ENABLE REG_BIT(31)
15#define EXITLINE_MASK REG_GENMASK(12, 0)
16#define EXITLINE_SHIFT 0
17
18/*
19 * HSW+ eDP PSR registers
20 *
21 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
22 * instance of it
23 */
24#define HSW_SRD_CTL _MMIO(0x64800)
25#define _SRD_CTL_A 0x60800
26#define _SRD_CTL_EDP 0x6f800
27#define EDP_PSR_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_CTL_A)
28#define EDP_PSR_ENABLE REG_BIT(31)
29#define BDW_PSR_SINGLE_FRAME REG_BIT(30)
30#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK REG_BIT(29) /* SW can't modify */
31#define EDP_PSR_LINK_STANDBY REG_BIT(27)
32#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK REG_GENMASK(26, 25)
33#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 0)
34#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 1)
35#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 2)
36#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 3)
37#define EDP_PSR_MAX_SLEEP_TIME_MASK REG_GENMASK(24, 20)
38#define EDP_PSR_MAX_SLEEP_TIME(x) REG_FIELD_PREP(EDP_PSR_MAX_SLEEP_TIME_MASK, (x))
39#define LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK REG_GENMASK(17, 16)
40#define LNL_EDP_PSR_ENTRY_SETUP_FRAMES(x) REG_FIELD_PREP(LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK, (x))
41#define EDP_PSR_SKIP_AUX_EXIT REG_BIT(12)
42#define EDP_PSR_TP_MASK REG_BIT(11)
43#define EDP_PSR_TP_TP1_TP2 REG_FIELD_PREP(EDP_PSR_TP_MASK, 0)
44#define EDP_PSR_TP_TP1_TP3 REG_FIELD_PREP(EDP_PSR_TP_MASK, 1)
45#define EDP_PSR_CRC_ENABLE REG_BIT(10) /* BDW+ */
46#define EDP_PSR_TP2_TP3_TIME_MASK REG_GENMASK(9, 8)
47#define EDP_PSR_TP2_TP3_TIME_500us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 0)
48#define EDP_PSR_TP2_TP3_TIME_100us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 1)
49#define EDP_PSR_TP2_TP3_TIME_2500us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 2)
50#define EDP_PSR_TP2_TP3_TIME_0us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 3)
51#define EDP_PSR_TP4_TIME_MASK REG_GENMASK(7, 6)
52#define EDP_PSR_TP4_TIME_0us REG_FIELD_PREP(EDP_PSR_TP4_TIME_MASK, 3) /* ICL+ */
53#define EDP_PSR_TP1_TIME_MASK REG_GENMASK(5, 4)
54#define EDP_PSR_TP1_TIME_500us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 0)
55#define EDP_PSR_TP1_TIME_100us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 1)
56#define EDP_PSR_TP1_TIME_2500us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 2)
57#define EDP_PSR_TP1_TIME_0us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 3)
58#define EDP_PSR_IDLE_FRAMES_MASK REG_GENMASK(3, 0)
59#define EDP_PSR_IDLE_FRAMES(x) REG_FIELD_PREP(EDP_PSR_IDLE_FRAMES_MASK, (x))
60
61/*
62 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
63 * to transcoder and bits defined for each one as if using no shift (i.e. as if
64 * it was for TRANSCODER_EDP)
65 */
66#define EDP_PSR_IMR _MMIO(0x64834)
67#define EDP_PSR_IIR _MMIO(0x64838)
68#define _PSR_IMR_A 0x60814
69#define _PSR_IIR_A 0x60818
70#define TRANS_PSR_IMR(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IMR_A)
71#define TRANS_PSR_IIR(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A)
72#define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \
73 0 : ((trans) - TRANSCODER_A + 1) * 8)
74#define TGL_PSR_MASK REG_GENMASK(2, 0)
75#define TGL_PSR_ERROR REG_BIT(2)
76#define TGL_PSR_POST_EXIT REG_BIT(1)
77#define TGL_PSR_PRE_ENTRY REG_BIT(0)
78#define EDP_PSR_MASK(trans) (TGL_PSR_MASK << \
79 _EDP_PSR_TRANS_SHIFT(trans))
80#define EDP_PSR_ERROR(trans) (TGL_PSR_ERROR << \
81 _EDP_PSR_TRANS_SHIFT(trans))
82#define EDP_PSR_POST_EXIT(trans) (TGL_PSR_POST_EXIT << \
83 _EDP_PSR_TRANS_SHIFT(trans))
84#define EDP_PSR_PRE_ENTRY(trans) (TGL_PSR_PRE_ENTRY << \
85 _EDP_PSR_TRANS_SHIFT(trans))
86
87#define HSW_SRD_AUX_CTL _MMIO(0x64810)
88#define _SRD_AUX_CTL_A 0x60810
89#define _SRD_AUX_CTL_EDP 0x6f810
90#define EDP_PSR_AUX_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_CTL_A)
91#define EDP_PSR_AUX_CTL_TIME_OUT_MASK DP_AUX_CH_CTL_TIME_OUT_MASK
92#define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
93#define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK DP_AUX_CH_CTL_PRECHARGE_2US_MASK
94#define EDP_PSR_AUX_CTL_ERROR_INTERRUPT REG_BIT(11)
95#define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK
96
97#define HSW_SRD_AUX_DATA(i) _MMIO(0x64814 + (i) * 4) /* 5 registers */
98#define _SRD_AUX_DATA_A 0x60814
99#define _SRD_AUX_DATA_EDP 0x6f814
100#define EDP_PSR_AUX_DATA(dev_priv, tran, i) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */
101
102#define HSW_SRD_STATUS _MMIO(0x64840)
103#define _SRD_STATUS_A 0x60840
104#define _SRD_STATUS_EDP 0x6f840
105#define EDP_PSR_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_STATUS_A)
106#define EDP_PSR_STATUS_STATE_MASK REG_GENMASK(31, 29)
107#define EDP_PSR_STATUS_STATE_IDLE REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 0)
108#define EDP_PSR_STATUS_STATE_SRDONACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 1)
109#define EDP_PSR_STATUS_STATE_SRDENT REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 2)
110#define EDP_PSR_STATUS_STATE_BUFOFF REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 3)
111#define EDP_PSR_STATUS_STATE_BUFON REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 4)
112#define EDP_PSR_STATUS_STATE_AUXACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 5)
113#define EDP_PSR_STATUS_STATE_SRDOFFACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 6)
114#define EDP_PSR_STATUS_LINK_MASK REG_GENMASK(27, 26)
115#define EDP_PSR_STATUS_LINK_FULL_OFF REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 0)
116#define EDP_PSR_STATUS_LINK_FULL_ON REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 1)
117#define EDP_PSR_STATUS_LINK_STANDBY REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 2)
118#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK REG_GENMASK(24, 20)
119#define EDP_PSR_STATUS_COUNT_MASK REG_GENMASK(19, 16)
120#define EDP_PSR_STATUS_AUX_ERROR REG_BIT(15)
121#define EDP_PSR_STATUS_AUX_SENDING REG_BIT(12)
122#define EDP_PSR_STATUS_SENDING_IDLE REG_BIT(9)
123#define EDP_PSR_STATUS_SENDING_TP2_TP3 REG_BIT(8)
124#define EDP_PSR_STATUS_SENDING_TP1 REG_BIT(4)
125#define EDP_PSR_STATUS_IDLE_MASK REG_GENMASK(3, 0)
126
127#define HSW_SRD_PERF_CNT _MMIO(0x64844)
128#define _SRD_PERF_CNT_A 0x60844
129#define _SRD_PERF_CNT_EDP 0x6f844
130#define EDP_PSR_PERF_CNT(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_PERF_CNT_A)
131#define EDP_PSR_PERF_CNT_MASK REG_GENMASK(23, 0)
132
133/* PSR_MASK on SKL+ */
134#define HSW_SRD_DEBUG _MMIO(0x64860)
135#define _SRD_DEBUG_A 0x60860
136#define _SRD_DEBUG_EDP 0x6f860
137#define EDP_PSR_DEBUG(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_DEBUG_A)
138#define EDP_PSR_DEBUG_MASK_MAX_SLEEP REG_BIT(28)
139#define EDP_PSR_DEBUG_MASK_LPSP REG_BIT(27)
140#define EDP_PSR_DEBUG_MASK_MEMUP REG_BIT(26)
141#define EDP_PSR_DEBUG_MASK_HPD REG_BIT(25)
142#define EDP_PSR_DEBUG_MASK_FBC_MODIFY REG_BIT(24)
143#define EDP_PSR_DEBUG_MASK_PRIMARY_FLIP REG_BIT(23) /* hsw */
144#define EDP_PSR_DEBUG_MASK_HDCP_ENABLE REG_BIT(22) /* hsw/bdw */
145#define EDP_PSR_DEBUG_MASK_SPRITE_ENABLE REG_BIT(21) /* hsw */
146#define EDP_PSR_DEBUG_MASK_CURSOR_MOVE REG_BIT(20) /* hsw */
147#define EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT REG_BIT(19) /* hsw */
148#define EDP_PSR_DEBUG_MASK_DPST_PHASE_IN REG_BIT(18) /* hsw */
149#define EDP_PSR_DEBUG_MASK_KVMR_SESSION_EN REG_BIT(17)
150#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE REG_BIT(16) /* hsw-skl */
151#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN REG_BIT(15) /* skl+ */
152#define EDP_PSR_DEBUG_RFB_UPDATE_SENT REG_BIT(2) /* bdw */
153#define EDP_PSR_DEBUG_ENTRY_COMPLETION REG_BIT(1) /* hsw/bdw */
154
155#define _PSR2_CTL_A 0x60900
156#define _PSR2_CTL_EDP 0x6f900
157#define EDP_PSR2_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_CTL_A)
158#define EDP_PSR2_ENABLE REG_BIT(31)
159#define EDP_SU_TRACK_ENABLE REG_BIT(30) /* up to adl-p */
160#define TGL_EDP_PSR2_BLOCK_COUNT_MASK REG_BIT(28)
161#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 REG_FIELD_PREP(TGL_EDP_PSR2_BLOCK_COUNT_MASK, 0)
162#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 REG_FIELD_PREP(TGL_EDP_PSR2_BLOCK_COUNT_MASK, 1)
163#define LNL_EDP_PSR2_SU_REGION_ET_ENABLE REG_BIT(27)
164#define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */
165#define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */
166#define EDP_MAX_SU_DISABLE_TIME_MASK REG_GENMASK(24, 20)
167#define EDP_MAX_SU_DISABLE_TIME(t) REG_FIELD_PREP(EDP_MAX_SU_DISABLE_TIME, (t))
168#define EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(14, 13)
169#define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8
170#define EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(EDP_PSR2_IO_BUFFER_WAKE_MASK, \
171 EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines))
172#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(15, 13)
173#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5
174#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \
175 (lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES)
176#define LNL_EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(18, 13)
177#define LNL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5
178#define LNL_EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(LNL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \
179 (lines) - LNL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES)
180#define EDP_PSR2_FAST_WAKE_MASK REG_GENMASK(12, 11)
181#define EDP_PSR2_FAST_WAKE_MAX_LINES 8
182#define EDP_PSR2_FAST_WAKE(lines) REG_FIELD_PREP(EDP_PSR2_FAST_WAKE_MASK, \
183 EDP_PSR2_FAST_WAKE_MAX_LINES - (lines))
184#define TGL_EDP_PSR2_FAST_WAKE_MASK REG_GENMASK(12, 10)
185#define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5
186#define TGL_EDP_PSR2_FAST_WAKE(lines) REG_FIELD_PREP(TGL_EDP_PSR2_FAST_WAKE_MASK, \
187 (lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES)
188#define EDP_PSR2_TP2_TIME_MASK REG_GENMASK(9, 8)
189#define EDP_PSR2_TP2_TIME_500us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 0)
190#define EDP_PSR2_TP2_TIME_100us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 1)
191#define EDP_PSR2_TP2_TIME_2500us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 2)
192#define EDP_PSR2_TP2_TIME_50us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 3)
193#define EDP_PSR2_FRAME_BEFORE_SU_MASK REG_GENMASK(7, 4)
194#define EDP_PSR2_FRAME_BEFORE_SU(a) REG_FIELD_PREP(EDP_PSR2_FRAME_BEFORE_SU_MASK, (a))
195#define EDP_PSR2_IDLE_FRAMES_MASK REG_GENMASK(3, 0)
196#define EDP_PSR2_IDLE_FRAMES(x) REG_FIELD_PREP(EDP_PSR2_IDLE_FRAMES_MASK, (x))
197
198#define _PSR_EVENT_TRANS_A 0x60848
199#define _PSR_EVENT_TRANS_B 0x61848
200#define _PSR_EVENT_TRANS_C 0x62848
201#define _PSR_EVENT_TRANS_D 0x63848
202#define _PSR_EVENT_TRANS_EDP 0x6f848
203#define PSR_EVENT(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR_EVENT_TRANS_A)
204#define PSR_EVENT_PSR2_WD_TIMER_EXPIRE REG_BIT(17)
205#define PSR_EVENT_PSR2_DISABLED REG_BIT(16)
206#define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN REG_BIT(15)
207#define PSR_EVENT_SU_CRC_FIFO_UNDERRUN REG_BIT(14)
208#define PSR_EVENT_GRAPHICS_RESET REG_BIT(12)
209#define PSR_EVENT_PCH_INTERRUPT REG_BIT(11)
210#define PSR_EVENT_MEMORY_UP REG_BIT(10)
211#define PSR_EVENT_FRONT_BUFFER_MODIFY REG_BIT(9)
212#define PSR_EVENT_WD_TIMER_EXPIRE REG_BIT(8)
213#define PSR_EVENT_PIPE_REGISTERS_UPDATE REG_BIT(6)
214#define PSR_EVENT_REGISTER_UPDATE REG_BIT(5) /* Reserved in ICL+ */
215#define PSR_EVENT_HDCP_ENABLE REG_BIT(4)
216#define PSR_EVENT_KVMR_SESSION_ENABLE REG_BIT(3)
217#define PSR_EVENT_VBI_ENABLE REG_BIT(2)
218#define PSR_EVENT_LPSP_MODE_EXIT REG_BIT(1)
219#define PSR_EVENT_PSR_DISABLE REG_BIT(0)
220
221#define _PSR2_STATUS_A 0x60940
222#define _PSR2_STATUS_EDP 0x6f940
223#define EDP_PSR2_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_STATUS_A)
224#define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28)
225#define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8)
226
227#define _PSR2_SU_STATUS_A 0x60914
228#define _PSR2_SU_STATUS_EDP 0x6f914
229#define _PSR2_SU_STATUS(dev_priv, tran, index) _MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)
230#define PSR2_SU_STATUS(dev_priv, tran, frame) (_PSR2_SU_STATUS(dev_priv, tran, (frame) / 3))
231#define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
232#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
233#define PSR2_SU_STATUS_FRAMES 8
234
235#define _PSR2_MAN_TRK_CTL_A 0x60910
236#define _PSR2_MAN_TRK_CTL_EDP 0x6f910
237#define PSR2_MAN_TRK_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_MAN_TRK_CTL_A)
238#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
239#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
240#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
241#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11)
242#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
243#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
244#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
245#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
246#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16)
247#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
248#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
249#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
250#define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31)
251#define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
252#define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
253
254#define _LNL_SFF_CTL_A 0x60918
255#define _LNL_SFF_CTL_B 0x61918
256#define LNL_SFF_CTL(tran) _MMIO_TRANS(tran, _LNL_SFF_CTL_A, _LNL_SFF_CTL_B)
257#define LNL_SFF_CTL_SF_SINGLE_FULL_FRAME REG_BIT(1)
258
259#define _LNL_CFF_CTL_A 0x6091c
260#define _LNL_CFF_CTL_B 0x6191c
261#define LNL_CFF_CTL(tran) _MMIO_TRANS(tran, _LNL_CFF_CTL_A, _LNL_CFF_CTL_B)
262#define LNL_CFF_CTL_SF_CONTINUOUS_FULL_FRAME REG_BIT(1)
263
264/* PSR2 Early transport */
265#define _PIPE_SRCSZ_ERLY_TPT_A 0x70074
266#define _PIPE_SRCSZ_ERLY_TPT_B 0x71074
267#define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)
268
269#define _PR_ALPM_CTL_A 0x60948
270#define PR_ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PR_ALPM_CTL_A)
271#define PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU BIT(6)
272#define PR_ALPM_CTL_RFB_UPDATE_CONTROL BIT(5)
273#define PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE BIT(4)
274#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK REG_GENMASK(1, 0)
275#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 0)
276#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 1)
277#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 2)
278
279#define _ALPM_CTL_A 0x60950
280#define ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A)
281#define ALPM_CTL_ALPM_ENABLE REG_BIT(31)
282#define ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(30)
283#define ALPM_CTL_LOBF_ENABLE REG_BIT(29)
284#define ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE REG_BIT(28)
285#define ALPM_CTL_KEEP_FEC_ENABLE_FOR_AUX_WAKE_SLEEP REG_BIT(27)
286#define ALPM_CTL_RESTORE_OCCURED REG_BIT(26)
287#define ALPM_CTL_RESTORE_TO_SLEEP REG_BIT(25)
288#define ALPM_CTL_RESTORE_TO_DEEP_SLEEP REG_BIT(24)
289#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK REG_GENMASK(23, 21)
290#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 0)
291#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_128_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 1)
292#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_256_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 2)
293#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_512_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 3)
294#define ALPM_CTL_AUX_WAKE_SLEEP_HOLD_ENABLE REG_BIT(20)
295#define ALPM_CTL_ALPM_ENTRY_CHECK_MASK REG_GENMASK(19, 16)
296#define ALPM_CTL_ALPM_ENTRY_CHECK(val) REG_FIELD_PREP(ALPM_CTL_ALPM_ENTRY_CHECK_MASK, val)
297#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK REG_GENMASK(13, 8)
298#define ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES 5
299#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines) REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, (lines) - ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES)
300#define ALPM_CTL_AUX_LESS_WAKE_TIME_MASK REG_GENMASK(5, 0)
301#define ALPM_CTL_AUX_LESS_WAKE_TIME(val) REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val)
302
303#define _ALPM_CTL2_A 0x60954
304#define ALPM_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)
305#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK REG_GENMASK(28, 24)
306#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val) REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val)
307#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK REG_GENMASK(19, 16)
308#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION(val) REG_FIELD_PREP(ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK, val)
309#define ALPM_CTL2_NUMBER_OF_LTTPR_MASK REG_GENMASK(15, 12)
310#define ALPM_CTL2_NUMBER_OF_LTTPR(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_OF_LTTPR_MASK, val)
311#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK REG_GENMASK(10, 8)
312#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME(val) REG_FIELD_PREP(ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK, val)
313#define ALPM_CTL2_FEC_DECODE_EN_POSITION_AFTER_WAKE_SR REG_BIT(4)
314#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK REG_GENMASK(2, 0)
315#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val)
316
317#define _PORT_ALPM_CTL_A 0x16fa2c
318#define _PORT_ALPM_CTL_B 0x16fc2c
319#define PORT_ALPM_CTL(port) _MMIO_PORT(port, _PORT_ALPM_CTL_A, _PORT_ALPM_CTL_B)
320#define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(31)
321#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(25, 20)
322#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val)
323#define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK REG_GENMASK(19, 16)
324#define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK, val)
325#define PORT_ALPM_CTL_SILENCE_PERIOD_MASK REG_GENMASK(7, 0)
326#define PORT_ALPM_CTL_SILENCE_PERIOD(val) REG_FIELD_PREP(PORT_ALPM_CTL_SILENCE_PERIOD_MASK, val)
327
328#define _PORT_ALPM_LFPS_CTL_A 0x16fa30
329#define _PORT_ALPM_LFPS_CTL_B 0x16fc30
330#define PORT_ALPM_LFPS_CTL(port) _MMIO_PORT(port, _PORT_ALPM_LFPS_CTL_A, _PORT_ALPM_LFPS_CTL_B)
331#define PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY REG_BIT(31)
332#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK REG_GENMASK(27, 24)
333#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN 7
334#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK, (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)
335#define PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(20, 16)
336#define PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val)
337#define PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(12, 8)
338#define PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, val)
339#define PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(4, 0)
340#define PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK, val)
341
342#endif /* __INTEL_PSR_REGS_H__ */
343