1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2024, Intel Corporation.
4 */
5
6#include <linux/debugfs.h>
7
8#include <drm/drm_print.h>
9
10#include "intel_alpm.h"
11#include "intel_crtc.h"
12#include "intel_de.h"
13#include "intel_display_types.h"
14#include "intel_dp.h"
15#include "intel_dp_aux.h"
16#include "intel_psr.h"
17#include "intel_psr_regs.h"
18
19#define SILENCE_PERIOD_MIN_TIME 80
20#define SILENCE_PERIOD_MAX_TIME 180
21#define SILENCE_PERIOD_TIME (SILENCE_PERIOD_MIN_TIME + \
22 (SILENCE_PERIOD_MAX_TIME - \
23 SILENCE_PERIOD_MIN_TIME) / 2)
24
25#define LFPS_CYCLE_COUNT 10
26
27bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)
28{
29 return intel_dp->alpm_dpcd & DP_ALPM_CAP;
30}
31
32bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp)
33{
34 return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP;
35}
36
37bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
38 const struct intel_crtc_state *crtc_state)
39{
40 return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) ||
41 (crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
42}
43
44void intel_alpm_init(struct intel_dp *intel_dp)
45{
46 u8 dpcd;
47
48 if (drm_dp_dpcd_readb(aux: &intel_dp->aux, DP_RECEIVER_ALPM_CAP, valuep: &dpcd) < 0)
49 return;
50
51 intel_dp->alpm_dpcd = dpcd;
52 mutex_init(&intel_dp->alpm_parameters.lock);
53}
54
55static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)
56{
57 return SILENCE_PERIOD_TIME * intel_dp_link_symbol_clock(rate: crtc_state->port_clock) /
58 1000 / 1000;
59}
60
61static int get_lfps_cycle_min_max_time(const struct intel_crtc_state *crtc_state,
62 int *min, int *max)
63{
64 if (crtc_state->port_clock < 540000) {
65 *min = 65 * LFPS_CYCLE_COUNT;
66 *max = 75 * LFPS_CYCLE_COUNT;
67 } else if (crtc_state->port_clock <= 810000) {
68 *min = 140;
69 *max = 800;
70 } else {
71 *min = *max = -1;
72 return -1;
73 }
74
75 return 0;
76}
77
78static int get_lfps_cycle_time(const struct intel_crtc_state *crtc_state)
79{
80 int tlfps_cycle_min, tlfps_cycle_max, ret;
81
82 ret = get_lfps_cycle_min_max_time(crtc_state, min: &tlfps_cycle_min,
83 max: &tlfps_cycle_max);
84 if (ret)
85 return ret;
86
87 return tlfps_cycle_min + (tlfps_cycle_max - tlfps_cycle_min) / 2;
88}
89
90static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
91{
92 int lfps_cycle_time = get_lfps_cycle_time(crtc_state);
93
94 if (lfps_cycle_time < 0)
95 return -1;
96
97 return lfps_cycle_time * crtc_state->port_clock / 1000 / 1000 / (2 * LFPS_CYCLE_COUNT);
98}
99
100/*
101 * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
102 * tSilence, Max+ tPHY Establishment + tCDS) / tline)
103 * For the "PHY P2 to P0" latency see the PHY Power Control page
104 * (PHY P2 to P0) : https://gfxspecs.intel.com/Predator/Home/Index/68965
105 * : 12 us
106 * The tLFPS_Period, Max term is 800ns
107 * The tSilence, Max term is 180ns
108 * The tPHY Establishment (a.k.a. t1) term is 50us
109 * The tCDS term is 1 or 2 times t2
110 * t2 = Number ML_PHY_LOCK * tML_PHY_LOCK
111 * Number ML_PHY_LOCK = ( 7 + CEILING( 6.5us / tML_PHY_LOCK ) + 1)
112 * Rounding up the 6.5us padding to the next ML_PHY_LOCK boundary and
113 * adding the "+ 1" term ensures all ML_PHY_LOCK sequences that start
114 * within the CDS period complete within the CDS period regardless of
115 * entry into the period
116 * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
117 * TPS4 Length = 252 Symbols
118 */
119static int _lnl_compute_aux_less_wake_time(const struct intel_crtc_state *crtc_state)
120{
121 int tphy2_p2_to_p0 = 12 * 1000;
122 int t1 = 50 * 1000;
123 int tps4 = 252;
124 /* port_clock is link rate in 10kbit/s units */
125 int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
126 int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
127 int t2 = num_ml_phy_lock * tml_phy_lock;
128 int tcds = 1 * t2;
129
130 return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +
131 SILENCE_PERIOD_TIME + t1 + tcds, 1000);
132}
133
134static int
135_lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
136 const struct intel_crtc_state *crtc_state)
137{
138 struct intel_display *display = to_intel_display(intel_dp);
139 int aux_less_wake_time, aux_less_wake_lines, silence_period,
140 lfps_half_cycle;
141
142 aux_less_wake_time =
143 _lnl_compute_aux_less_wake_time(crtc_state);
144 aux_less_wake_lines = intel_usecs_to_scanlines(adjusted_mode: &crtc_state->hw.adjusted_mode,
145 usecs: aux_less_wake_time);
146 silence_period = get_silence_period_symbols(crtc_state);
147
148 lfps_half_cycle = get_lfps_half_cycle_clocks(crtc_state);
149 if (lfps_half_cycle < 0)
150 return false;
151
152 if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK ||
153 silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK ||
154 lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK)
155 return false;
156
157 if (display->params.psr_safest_params)
158 aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK;
159
160 intel_dp->alpm_parameters.aux_less_wake_lines = aux_less_wake_lines;
161 intel_dp->alpm_parameters.silence_period_sym_clocks = silence_period;
162 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms = lfps_half_cycle;
163
164 return true;
165}
166
167static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp,
168 const struct intel_crtc_state *crtc_state)
169{
170 struct intel_display *display = to_intel_display(intel_dp);
171 int check_entry_lines;
172
173 if (DISPLAY_VER(display) < 20)
174 return true;
175
176 /* ALPM Entry Check = 2 + CEILING( 5us /tline ) */
177 check_entry_lines = 2 +
178 intel_usecs_to_scanlines(adjusted_mode: &crtc_state->hw.adjusted_mode, usecs: 5);
179
180 if (check_entry_lines > 15)
181 return false;
182
183 if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state))
184 return false;
185
186 if (display->params.psr_safest_params)
187 check_entry_lines = 15;
188
189 intel_dp->alpm_parameters.check_entry_lines = check_entry_lines;
190
191 return true;
192}
193
194/*
195 * IO wake time for DISPLAY_VER < 12 is not directly mentioned in Bspec. There
196 * are 50 us io wake time and 32 us fast wake time. Clearly preharge pulses are
197 * not (improperly) included in 32 us fast wake time. 50 us - 32 us = 18 us.
198 */
199static int skl_io_buffer_wake_time(void)
200{
201 return 18;
202}
203
204static int tgl_io_buffer_wake_time(void)
205{
206 return 10;
207}
208
209static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state)
210{
211 struct intel_display *display = to_intel_display(crtc_state);
212
213 if (DISPLAY_VER(display) >= 12)
214 return tgl_io_buffer_wake_time();
215 else
216 return skl_io_buffer_wake_time();
217}
218
219bool intel_alpm_compute_params(struct intel_dp *intel_dp,
220 const struct intel_crtc_state *crtc_state)
221{
222 struct intel_display *display = to_intel_display(intel_dp);
223 int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time;
224 int tfw_exit_latency = 20; /* eDP spec */
225 int phy_wake = 4; /* eDP spec */
226 int preamble = 8; /* eDP spec */
227 int precharge = intel_dp_aux_fw_sync_len(intel_dp) - preamble;
228 u8 max_wake_lines;
229
230 io_wake_time = max(precharge, io_buffer_wake_time(crtc_state)) +
231 preamble + phy_wake + tfw_exit_latency;
232 fast_wake_time = precharge + preamble + phy_wake +
233 tfw_exit_latency;
234
235 if (DISPLAY_VER(display) >= 20)
236 max_wake_lines = 68;
237 else if (DISPLAY_VER(display) >= 12)
238 max_wake_lines = 12;
239 else
240 max_wake_lines = 8;
241
242 io_wake_lines = intel_usecs_to_scanlines(
243 adjusted_mode: &crtc_state->hw.adjusted_mode, usecs: io_wake_time);
244 fast_wake_lines = intel_usecs_to_scanlines(
245 adjusted_mode: &crtc_state->hw.adjusted_mode, usecs: fast_wake_time);
246
247 if (io_wake_lines > max_wake_lines ||
248 fast_wake_lines > max_wake_lines)
249 return false;
250
251 if (!_lnl_compute_alpm_params(intel_dp, crtc_state))
252 return false;
253
254 if (display->params.psr_safest_params)
255 io_wake_lines = fast_wake_lines = max_wake_lines;
256
257 /* According to Bspec lower limit should be set as 7 lines. */
258 intel_dp->alpm_parameters.io_wake_lines = max(io_wake_lines, 7);
259 intel_dp->alpm_parameters.fast_wake_lines = max(fast_wake_lines, 7);
260
261 return true;
262}
263
264void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
265 struct intel_crtc_state *crtc_state,
266 struct drm_connector_state *conn_state)
267{
268 struct intel_display *display = to_intel_display(intel_dp);
269 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
270 int waketime_in_lines, first_sdp_position;
271 int context_latency, guardband;
272
273 if (intel_dp->alpm_parameters.lobf_disable_debug) {
274 drm_dbg_kms(display->drm, "LOBF is disabled by debug flag\n");
275 return;
276 }
277
278 if (intel_dp->alpm_parameters.sink_alpm_error)
279 return;
280
281 if (!intel_dp_is_edp(intel_dp))
282 return;
283
284 if (DISPLAY_VER(display) < 20)
285 return;
286
287 if (!intel_dp->as_sdp_supported)
288 return;
289
290 if (crtc_state->has_psr)
291 return;
292
293 if (crtc_state->vrr.vmin != crtc_state->vrr.vmax ||
294 crtc_state->vrr.vmin != crtc_state->vrr.flipline)
295 return;
296
297 if (!(intel_alpm_aux_wake_supported(intel_dp) ||
298 intel_alpm_aux_less_wake_supported(intel_dp)))
299 return;
300
301 if (!intel_alpm_compute_params(intel_dp, crtc_state))
302 return;
303
304 context_latency = adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
305 guardband = adjusted_mode->crtc_vtotal -
306 adjusted_mode->crtc_vdisplay - context_latency;
307 first_sdp_position = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
308 if (intel_alpm_aux_less_wake_supported(intel_dp))
309 waketime_in_lines = intel_dp->alpm_parameters.io_wake_lines;
310 else
311 waketime_in_lines = intel_dp->alpm_parameters.aux_less_wake_lines;
312
313 crtc_state->has_lobf = (context_latency + guardband) >
314 (first_sdp_position + waketime_in_lines);
315}
316
317static void lnl_alpm_configure(struct intel_dp *intel_dp,
318 const struct intel_crtc_state *crtc_state)
319{
320 struct intel_display *display = to_intel_display(intel_dp);
321 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
322 u32 alpm_ctl;
323
324 if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
325 !crtc_state->has_lobf))
326 return;
327
328 mutex_lock(lock: &intel_dp->alpm_parameters.lock);
329 /*
330 * Panel Replay on eDP is always using ALPM aux less. I.e. no need to
331 * check panel support at this point.
332 */
333 if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
334 alpm_ctl = ALPM_CTL_ALPM_ENABLE |
335 ALPM_CTL_ALPM_AUX_LESS_ENABLE |
336 ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
337 ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines);
338
339 if (intel_dp->as_sdp_supported) {
340 u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
341
342 if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
343 DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP)
344 pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
345 if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
346 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))
347 pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
348
349 intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
350 val: pr_alpm_ctl);
351 }
352
353 } else {
354 alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
355 ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines);
356 }
357
358 if (crtc_state->has_lobf) {
359 alpm_ctl |= ALPM_CTL_LOBF_ENABLE;
360 drm_dbg_kms(display->drm, "Link off between frames (LOBF) enabled\n");
361 }
362
363 alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines);
364
365 intel_de_write(display, ALPM_CTL(display, cpu_transcoder), val: alpm_ctl);
366 mutex_unlock(lock: &intel_dp->alpm_parameters.lock);
367}
368
369void intel_alpm_configure(struct intel_dp *intel_dp,
370 const struct intel_crtc_state *crtc_state)
371{
372 lnl_alpm_configure(intel_dp, crtc_state);
373 intel_dp->alpm_parameters.transcoder = crtc_state->cpu_transcoder;
374}
375
376void intel_alpm_port_configure(struct intel_dp *intel_dp,
377 const struct intel_crtc_state *crtc_state)
378{
379 struct intel_display *display = to_intel_display(intel_dp);
380 enum port port = dp_to_dig_port(intel_dp)->base.port;
381 u32 alpm_ctl_val = 0, lfps_ctl_val = 0;
382
383 if (DISPLAY_VER(display) < 20)
384 return;
385
386 if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
387 alpm_ctl_val = PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
388 PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
389 PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
390 PORT_ALPM_CTL_SILENCE_PERIOD(
391 intel_dp->alpm_parameters.silence_period_sym_clocks);
392 lfps_ctl_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(LFPS_CYCLE_COUNT) |
393 PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
394 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
395 PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
396 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
397 PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(
398 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms);
399 }
400
401 intel_de_write(display, PORT_ALPM_CTL(port), val: alpm_ctl_val);
402
403 intel_de_write(display, PORT_ALPM_LFPS_CTL(port), val: lfps_ctl_val);
404}
405
406void intel_alpm_pre_plane_update(struct intel_atomic_state *state,
407 struct intel_crtc *crtc)
408{
409 struct intel_display *display = to_intel_display(state);
410 const struct intel_crtc_state *crtc_state =
411 intel_atomic_get_new_crtc_state(state, crtc);
412 const struct intel_crtc_state *old_crtc_state =
413 intel_atomic_get_old_crtc_state(state, crtc);
414 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
415 struct intel_encoder *encoder;
416
417 if (DISPLAY_VER(display) < 20)
418 return;
419
420 if (crtc_state->has_lobf || crtc_state->has_lobf == old_crtc_state->has_lobf)
421 return;
422
423 for_each_intel_encoder_mask(display->drm, encoder,
424 crtc_state->uapi.encoder_mask) {
425 struct intel_dp *intel_dp;
426
427 if (!intel_encoder_is_dp(encoder))
428 continue;
429
430 intel_dp = enc_to_intel_dp(encoder);
431
432 if (!intel_dp_is_edp(intel_dp))
433 continue;
434
435 if (old_crtc_state->has_lobf) {
436 mutex_lock(lock: &intel_dp->alpm_parameters.lock);
437 intel_de_write(display, ALPM_CTL(display, cpu_transcoder), val: 0);
438 drm_dbg_kms(display->drm, "Link off between frames (LOBF) disabled\n");
439 mutex_unlock(lock: &intel_dp->alpm_parameters.lock);
440 }
441 }
442}
443
444void intel_alpm_enable_sink(struct intel_dp *intel_dp,
445 const struct intel_crtc_state *crtc_state)
446{
447 u8 val;
448
449 if (!intel_psr_needs_alpm(intel_dp, crtc_state) && !crtc_state->has_lobf)
450 return;
451
452 val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE;
453
454 if (crtc_state->has_panel_replay || (crtc_state->has_lobf &&
455 intel_alpm_aux_less_wake_supported(intel_dp)))
456 val |= DP_ALPM_MODE_AUX_LESS;
457
458 drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, value: val);
459}
460
461void intel_alpm_post_plane_update(struct intel_atomic_state *state,
462 struct intel_crtc *crtc)
463{
464 struct intel_display *display = to_intel_display(state);
465 const struct intel_crtc_state *crtc_state =
466 intel_atomic_get_new_crtc_state(state, crtc);
467 const struct intel_crtc_state *old_crtc_state =
468 intel_atomic_get_old_crtc_state(state, crtc);
469 struct intel_encoder *encoder;
470
471 if (crtc_state->has_psr || !crtc_state->has_lobf ||
472 crtc_state->has_lobf == old_crtc_state->has_lobf)
473 return;
474
475 for_each_intel_encoder_mask(display->drm, encoder,
476 crtc_state->uapi.encoder_mask) {
477 struct intel_dp *intel_dp;
478
479 if (!intel_encoder_is_dp(encoder))
480 continue;
481
482 intel_dp = enc_to_intel_dp(encoder);
483
484 if (intel_dp_is_edp(intel_dp)) {
485 intel_alpm_enable_sink(intel_dp, crtc_state);
486 intel_alpm_configure(intel_dp, crtc_state);
487 }
488 }
489}
490
491static int i915_edp_lobf_info_show(struct seq_file *m, void *data)
492{
493 struct intel_connector *connector = m->private;
494 struct intel_display *display = to_intel_display(connector);
495 struct drm_crtc *crtc;
496 struct intel_crtc_state *crtc_state;
497 enum transcoder cpu_transcoder;
498 u32 alpm_ctl;
499 int ret;
500
501 ret = drm_modeset_lock_single_interruptible(lock: &display->drm->mode_config.connection_mutex);
502 if (ret)
503 return ret;
504
505 crtc = connector->base.state->crtc;
506 if (connector->base.status != connector_status_connected || !crtc) {
507 ret = -ENODEV;
508 goto out;
509 }
510
511 crtc_state = to_intel_crtc_state(crtc->state);
512 cpu_transcoder = crtc_state->cpu_transcoder;
513 alpm_ctl = intel_de_read(display, ALPM_CTL(display, cpu_transcoder));
514 seq_printf(m, fmt: "LOBF status: %s\n", str_enabled_disabled(v: alpm_ctl & ALPM_CTL_LOBF_ENABLE));
515 seq_printf(m, fmt: "Aux-wake alpm status: %s\n",
516 str_enabled_disabled(v: !(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE)));
517 seq_printf(m, fmt: "Aux-less alpm status: %s\n",
518 str_enabled_disabled(v: alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE));
519out:
520 drm_modeset_unlock(lock: &display->drm->mode_config.connection_mutex);
521
522 return ret;
523}
524
525DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_info);
526
527static int
528i915_edp_lobf_debug_get(void *data, u64 *val)
529{
530 struct intel_connector *connector = data;
531 struct intel_dp *intel_dp = enc_to_intel_dp(encoder: connector->encoder);
532
533 *val = intel_dp->alpm_parameters.lobf_disable_debug;
534
535 return 0;
536}
537
538static int
539i915_edp_lobf_debug_set(void *data, u64 val)
540{
541 struct intel_connector *connector = data;
542 struct intel_dp *intel_dp = enc_to_intel_dp(encoder: connector->encoder);
543
544 intel_dp->alpm_parameters.lobf_disable_debug = val;
545
546 return 0;
547}
548
549DEFINE_SIMPLE_ATTRIBUTE(i915_edp_lobf_debug_fops,
550 i915_edp_lobf_debug_get, i915_edp_lobf_debug_set,
551 "%llu\n");
552
553void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)
554{
555 struct intel_display *display = to_intel_display(connector);
556 struct dentry *root = connector->base.debugfs_entry;
557
558 if (DISPLAY_VER(display) < 20 ||
559 connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
560 return;
561
562 debugfs_create_file("i915_edp_lobf_debug", 0644, root,
563 connector, &i915_edp_lobf_debug_fops);
564
565 debugfs_create_file("i915_edp_lobf_info", 0444, root,
566 connector, &i915_edp_lobf_info_fops);
567}
568
569void intel_alpm_disable(struct intel_dp *intel_dp)
570{
571 struct intel_display *display = to_intel_display(intel_dp);
572 enum transcoder cpu_transcoder = intel_dp->alpm_parameters.transcoder;
573
574 if (DISPLAY_VER(display) < 20 || !intel_dp->alpm_dpcd)
575 return;
576
577 mutex_lock(lock: &intel_dp->alpm_parameters.lock);
578
579 intel_de_rmw(display, ALPM_CTL(display, cpu_transcoder),
580 ALPM_CTL_ALPM_ENABLE | ALPM_CTL_LOBF_ENABLE |
581 ALPM_CTL_ALPM_AUX_LESS_ENABLE, set: 0);
582
583 intel_de_rmw(display,
584 PORT_ALPM_CTL(cpu_transcoder),
585 PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE, set: 0);
586
587 drm_dbg_kms(display->drm, "Disabling ALPM\n");
588 mutex_unlock(lock: &intel_dp->alpm_parameters.lock);
589}
590
591bool intel_alpm_get_error(struct intel_dp *intel_dp)
592{
593 struct intel_display *display = to_intel_display(intel_dp);
594 struct drm_dp_aux *aux = &intel_dp->aux;
595 u8 val;
596 int r;
597
598 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, valuep: &val);
599 if (r != 1) {
600 drm_err(display->drm, "Error reading ALPM status\n");
601 return true;
602 }
603
604 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) {
605 drm_dbg_kms(display->drm, "ALPM lock timeout error\n");
606
607 /* Clearing error */
608 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, value: val);
609 return true;
610 }
611
612 return false;
613}
614