1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2024 Intel Corporation
4 */
5
6#ifndef __INTEL_VRR_REGS_H__
7#define __INTEL_VRR_REGS_H__
8
9#include "intel_display_reg_defs.h"
10
11#define _TRANS_VRR_CTL_A 0x60420
12#define _TRANS_VRR_CTL_B 0x61420
13#define _TRANS_VRR_CTL_C 0x62420
14#define _TRANS_VRR_CTL_D 0x63420
15#define TRANS_VRR_CTL(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_CTL_A)
16#define VRR_CTL_VRR_ENABLE REG_BIT(31)
17#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
18#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
19#define VRR_CTL_CMRR_ENABLE REG_BIT(27)
20#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
21#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
22#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
23#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
24#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
25
26#define _TRANS_VRR_VMAX_A 0x60424
27#define _TRANS_VRR_VMAX_B 0x61424
28#define _TRANS_VRR_VMAX_C 0x62424
29#define _TRANS_VRR_VMAX_D 0x63424
30#define TRANS_VRR_VMAX(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMAX_A)
31#define VRR_VMAX_MASK REG_GENMASK(19, 0)
32
33#define _TRANS_VRR_VMIN_A 0x60434
34#define _TRANS_VRR_VMIN_B 0x61434
35#define _TRANS_VRR_VMIN_C 0x62434
36#define _TRANS_VRR_VMIN_D 0x63434
37#define TRANS_VRR_VMIN(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMIN_A)
38#define VRR_VMIN_MASK REG_GENMASK(15, 0)
39
40#define _TRANS_VRR_VMAXSHIFT_A 0x60428
41#define _TRANS_VRR_VMAXSHIFT_B 0x61428
42#define _TRANS_VRR_VMAXSHIFT_C 0x62428
43#define _TRANS_VRR_VMAXSHIFT_D 0x63428
44#define TRANS_VRR_VMAXSHIFT(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMAXSHIFT_A)
45#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
46#define VRR_VMAXSHIFT_DEC REG_BIT(16)
47#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
48
49#define _TRANS_VRR_STATUS_A 0x6042c
50#define _TRANS_VRR_STATUS_B 0x6142c
51#define _TRANS_VRR_STATUS_C 0x6242c
52#define _TRANS_VRR_STATUS_D 0x6342c
53#define TRANS_VRR_STATUS(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_STATUS_A)
54#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
55#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
56#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
57#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
58#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
59#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
60#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
61#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
62#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
63#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
64#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
65#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
66#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
67#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
68
69#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
70#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
71#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
72#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
73#define TRANS_VRR_VTOTAL_PREV(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VTOTAL_PREV_A)
74#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
75#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
76#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
77#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
78
79#define _TRANS_VRR_FLIPLINE_A 0x60438
80#define _TRANS_VRR_FLIPLINE_B 0x61438
81#define _TRANS_VRR_FLIPLINE_C 0x62438
82#define _TRANS_VRR_FLIPLINE_D 0x63438
83#define TRANS_VRR_FLIPLINE(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_FLIPLINE_A)
84#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
85
86#define _TRANS_VRR_STATUS2_A 0x6043c
87#define _TRANS_VRR_STATUS2_B 0x6143c
88#define _TRANS_VRR_STATUS2_C 0x6243c
89#define _TRANS_VRR_STATUS2_D 0x6343c
90#define TRANS_VRR_STATUS2(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_STATUS2_A)
91#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
92
93#define _TRANS_PUSH_A 0x60a70
94#define _TRANS_PUSH_B 0x61a70
95#define _TRANS_PUSH_C 0x62a70
96#define _TRANS_PUSH_D 0x63a70
97#define TRANS_PUSH(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_PUSH_A)
98#define TRANS_PUSH_EN REG_BIT(31)
99#define TRANS_PUSH_SEND REG_BIT(30)
100
101#define _TRANS_VRR_VSYNC_A 0x60078
102#define TRANS_VRR_VSYNC(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VSYNC_A)
103#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
104#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
105#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
106#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
107
108/* Common register for HDMI EMP and DP AS SDP */
109#define _EMP_AS_SDP_TL_A 0x60204
110#define EMP_AS_SDP_TL(display, trans) _MMIO_TRANS2((display), (trans), _EMP_AS_SDP_TL_A)
111#define EMP_AS_SDP_DB_TL_MASK REG_GENMASK(12, 0)
112#define EMP_AS_SDP_DB_TL(db_transmit_line) REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, (db_transmit_line))
113
114#define _TRANS_CMRR_M_LO_A 0x604F0
115#define TRANS_CMRR_M_LO(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_M_LO_A)
116
117#define _TRANS_CMRR_M_HI_A 0x604F4
118#define TRANS_CMRR_M_HI(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_M_HI_A)
119
120#define _TRANS_CMRR_N_LO_A 0x604F8
121#define TRANS_CMRR_N_LO(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_N_LO_A)
122
123#define _TRANS_CMRR_N_HI_A 0x604FC
124#define TRANS_CMRR_N_HI(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_N_HI_A)
125
126#endif /* __INTEL_VRR_REGS__ */
127