skl_watermark.h source code [Linux/drivers/gpu/drm/i915/display/skl_watermark.h]

1	/ SPDX-License-Identifier: MIT /
2	/*
3	* Copyright © 2022 Intel Corporation
4	*/
5
6	#ifndef __SKL_WATERMARK_H__
7	#define __SKL_WATERMARK_H__
8
9	#include <linux/types.h>
10
11	enum plane_id;
12	struct intel_atomic_state;
13	struct intel_crtc;
14	struct intel_crtc_state;
15	struct intel_dbuf_state;
16	struct intel_display;
17	struct intel_plane;
18	struct intel_plane_state;
19	struct skl_ddb_entry;
20	struct skl_pipe_wm;
21	struct skl_wm_level;
22
23	u8 intel_enabled_dbuf_slices_mask(struct intel_display *display);
24
25	void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
26	void intel_sagv_post_plane_update(struct intel_atomic_state *state);
27	bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
28	bool intel_has_sagv(struct intel_display *display);
29
30	u32 skl_ddb_dbuf_slice_mask(struct intel_display *display,
31	const struct skl_ddb_entry *entry);
32
33	bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
34	const struct skl_ddb_entry *entries,
35	int num_entries, int ignore_idx);
36
37	void intel_wm_state_verify(struct intel_atomic_state *state,
38	struct intel_crtc *crtc);
39
40	void skl_wm_crtc_disable_noatomic(struct intel_crtc *crtc);
41	void skl_wm_plane_disable_noatomic(struct intel_crtc *crtc,
42	struct intel_plane *plane);
43
44	void skl_watermark_ipc_init(struct intel_display *display);
45	void skl_watermark_ipc_update(struct intel_display *display);
46	bool skl_watermark_ipc_enabled(struct intel_display *display);
47	void skl_watermark_debugfs_register(struct intel_display *display);
48
49	unsigned int skl_watermark_max_latency(struct intel_display *display,
50	int initial_wm_level);
51	void skl_wm_init(struct intel_display *display);
52
53	const struct skl_wm_level skl_plane_wm_level(const* struct skl_pipe_wm *pipe_wm,
54	enum plane_id plane_id,
55	int level);
56	const struct skl_wm_level skl_plane_trans_wm(const* struct skl_pipe_wm *pipe_wm,
57	enum plane_id plane_id);
58	unsigned int skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
59	struct intel_plane plane, int* width,
60	int height, int cpp);
61
62	struct intel_dbuf_state *
63	intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
64
65	int intel_dbuf_num_enabled_slices(const struct intel_dbuf_state *dbuf_state);
66	int intel_dbuf_num_active_pipes(const struct intel_dbuf_state *dbuf_state);
67
68	int intel_dbuf_init(struct intel_display *display);
69	int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
70	int ratio);
71
72	void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
73	void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
74	void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,
75	int ratio, bool joined_mbus);
76	void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state);
77	void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
78	void intel_program_dpkgc_latency(struct intel_atomic_state *state);
79
80	bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state);
81
82	#endif /* __SKL_WATERMARK_H__ */
83
84

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