1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
6#ifndef __INTEL_DISPLAY_CORE_H__
7#define __INTEL_DISPLAY_CORE_H__
8
9#include <linux/list.h>
10#include <linux/llist.h>
11#include <linux/mutex.h>
12#include <linux/types.h>
13#include <linux/wait.h>
14#include <linux/workqueue.h>
15
16#include <drm/drm_connector.h>
17#include <drm/drm_modeset_lock.h>
18
19#include "intel_cdclk.h"
20#include "intel_display_device.h"
21#include "intel_display_limits.h"
22#include "intel_display_params.h"
23#include "intel_display_power.h"
24#include "intel_dmc_wl.h"
25#include "intel_dpll_mgr.h"
26#include "intel_fbc.h"
27#include "intel_global_state.h"
28#include "intel_gmbus.h"
29#include "intel_opregion.h"
30#include "intel_pch.h"
31#include "intel_wm_types.h"
32
33struct drm_property;
34struct drm_property_blob;
35struct i915_audio_component;
36struct i915_hdcp_arbiter;
37struct intel_atomic_state;
38struct intel_audio_funcs;
39struct intel_cdclk_funcs;
40struct intel_cdclk_vals;
41struct intel_color_funcs;
42struct intel_crtc;
43struct intel_crtc_state;
44struct intel_dmc;
45struct intel_dpll_global_funcs;
46struct intel_dpll_mgr;
47struct intel_fbdev;
48struct intel_fdi_funcs;
49struct intel_hotplug_funcs;
50struct intel_initial_plane_config;
51struct intel_opregion;
52struct intel_overlay;
53struct task_struct;
54
55/* Amount of SAGV/QGV points, BSpec precisely defines this */
56#define I915_NUM_QGV_POINTS 8
57
58/* Amount of PSF GV points, BSpec precisely defines this */
59#define I915_NUM_PSF_GV_POINTS 3
60
61struct intel_display_funcs {
62 /*
63 * Returns the active state of the crtc, and if the crtc is active,
64 * fills out the pipe-config with the hw state.
65 */
66 bool (*get_pipe_config)(struct intel_crtc *,
67 struct intel_crtc_state *);
68 void (*get_initial_plane_config)(struct intel_crtc *,
69 struct intel_initial_plane_config *);
70 bool (*fixup_initial_plane_config)(struct intel_crtc *crtc,
71 const struct intel_initial_plane_config *plane_config);
72 void (*crtc_enable)(struct intel_atomic_state *state,
73 struct intel_crtc *crtc);
74 void (*crtc_disable)(struct intel_atomic_state *state,
75 struct intel_crtc *crtc);
76 void (*commit_modeset_enables)(struct intel_atomic_state *state);
77};
78
79/* functions used for watermark calcs for display. */
80struct intel_wm_funcs {
81 /* update_wm is for legacy wm management */
82 void (*update_wm)(struct intel_display *display);
83 int (*compute_watermarks)(struct intel_atomic_state *state,
84 struct intel_crtc *crtc);
85 void (*initial_watermarks)(struct intel_atomic_state *state,
86 struct intel_crtc *crtc);
87 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
88 struct intel_crtc *crtc);
89 void (*optimize_watermarks)(struct intel_atomic_state *state,
90 struct intel_crtc *crtc);
91 int (*compute_global_watermarks)(struct intel_atomic_state *state);
92 void (*get_hw_state)(struct intel_display *display);
93 void (*sanitize)(struct intel_display *display);
94};
95
96struct intel_audio_state {
97 struct intel_encoder *encoder;
98 u8 eld[MAX_ELD_BYTES];
99};
100
101struct intel_audio {
102 /* hda/i915 audio component */
103 struct i915_audio_component *component;
104 bool component_registered;
105 /* mutex for audio/video sync */
106 struct mutex mutex;
107 int power_refcount;
108 u32 freq_cntrl;
109
110 /* current audio state for the audio component hooks */
111 struct intel_audio_state state[I915_MAX_TRANSCODERS];
112
113 /* necessary resource sharing with HDMI LPE audio driver. */
114 struct {
115 struct platform_device *platdev;
116 int irq;
117 } lpe;
118};
119
120/*
121 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes
122 * intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per
123 * dpll, because on some platforms plls share registers.
124 */
125struct intel_dpll_global {
126 struct mutex lock;
127
128 int num_dpll;
129 struct intel_dpll dplls[I915_NUM_PLLS];
130 const struct intel_dpll_mgr *mgr;
131
132 struct {
133 int nssc;
134 int ssc;
135 } ref_clks;
136
137 /*
138 * Bitmask of PLLs using the PCH SSC, indexed using enum intel_dpll_id.
139 */
140 u8 pch_ssc_use;
141};
142
143struct intel_frontbuffer_tracking {
144 spinlock_t lock;
145
146 /*
147 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
148 * scheduled flips.
149 */
150 unsigned busy_bits;
151 unsigned flip_bits;
152};
153
154struct intel_hotplug {
155 struct delayed_work hotplug_work;
156
157 const u32 *hpd, *pch_hpd;
158
159 struct {
160 unsigned long last_jiffies;
161 int count;
162 int blocked_count;
163 enum {
164 HPD_ENABLED = 0,
165 HPD_DISABLED = 1,
166 HPD_MARK_DISABLED = 2
167 } state;
168 } stats[HPD_NUM_PINS];
169 u32 event_bits;
170 u32 retry_bits;
171 struct delayed_work reenable_work;
172
173 u32 long_hpd_pin_mask;
174 u32 short_hpd_pin_mask;
175 struct work_struct dig_port_work;
176
177 struct work_struct poll_init_work;
178 bool poll_enabled;
179
180 /*
181 * Queuing of hotplug_work, reenable_work and poll_init_work is
182 * enabled. Protected by intel_display::irq::lock.
183 */
184 bool detection_work_enabled;
185
186 unsigned int hpd_storm_threshold;
187 /* Whether or not to count short HPD IRQs in HPD storms */
188 u8 hpd_short_storm_enabled;
189
190 /* Last state reported by oob_hotplug_event for each encoder */
191 unsigned long oob_hotplug_last_state;
192
193 /*
194 * if we get a HPD irq from DP and a HPD irq from non-DP
195 * the non-DP HPD could block the workqueue on a mode config
196 * mutex getting, that userspace may have taken. However
197 * userspace is waiting on the DP workqueue to run which is
198 * blocked behind the non-DP one.
199 */
200 struct workqueue_struct *dp_wq;
201
202 /*
203 * Flag to track if long HPDs need not to be processed
204 *
205 * Some panels generate long HPDs while keep connected to the port.
206 * This can cause issues with CI tests results. In CI systems we
207 * don't expect to disconnect the panels and could ignore the long
208 * HPDs generated from the faulty panels. This flag can be used as
209 * cue to ignore the long HPDs and can be set / unset using debugfs.
210 */
211 bool ignore_long_hpd;
212};
213
214struct intel_vbt_data {
215 /* bdb version */
216 u16 version;
217
218 /* Feature bits */
219 unsigned int int_tv_support:1;
220 unsigned int int_crt_support:1;
221 unsigned int lvds_use_ssc:1;
222 unsigned int int_lvds_support:1;
223 unsigned int display_clock_mode:1;
224 unsigned int fdi_rx_polarity_inverted:1;
225 int lvds_ssc_freq;
226 enum drm_panel_orientation orientation;
227
228 bool override_afc_startup;
229 u8 override_afc_startup_val;
230
231 int crt_ddc_pin;
232
233 struct list_head display_devices;
234 struct list_head bdb_blocks;
235
236 struct sdvo_device_mapping {
237 u8 initialized;
238 u8 dvo_port;
239 u8 target_addr;
240 u8 dvo_wiring;
241 u8 i2c_pin;
242 u8 ddc_pin;
243 } sdvo_mappings[2];
244};
245
246struct intel_wm {
247 /*
248 * Raw watermark latency values:
249 * in 0.1us units for WM0,
250 * in 0.5us units for WM1+.
251 */
252 /* primary */
253 u16 pri_latency[5];
254 /* sprite */
255 u16 spr_latency[5];
256 /* cursor */
257 u16 cur_latency[5];
258 /*
259 * Raw watermark memory latency values
260 * for SKL for all 8 levels
261 * in 1us units.
262 */
263 u16 skl_latency[8];
264
265 /* current hardware state */
266 union {
267 struct ilk_wm_values hw;
268 struct vlv_wm_values vlv;
269 struct g4x_wm_values g4x;
270 };
271
272 u8 num_levels;
273
274 /*
275 * Should be held around atomic WM register writing; also
276 * protects * intel_crtc->wm.active and
277 * crtc_state->wm.need_postvbl_update.
278 */
279 struct mutex wm_mutex;
280
281 bool ipc_enabled;
282};
283
284struct intel_display {
285 /* drm device backpointer */
286 struct drm_device *drm;
287
288 /* Platform (and subplatform, if any) identification */
289 struct intel_display_platforms platform;
290
291 /* Intel PCH: where the south display engine lives */
292 enum intel_pch pch_type;
293
294 /* Display functions */
295 struct {
296 /* Top level crtc-ish functions */
297 const struct intel_display_funcs *display;
298
299 /* Display CDCLK functions */
300 const struct intel_cdclk_funcs *cdclk;
301
302 /* Display pll funcs */
303 const struct intel_dpll_global_funcs *dpll;
304
305 /* irq display functions */
306 const struct intel_hotplug_funcs *hotplug;
307
308 /* pm display functions */
309 const struct intel_wm_funcs *wm;
310
311 /* fdi display functions */
312 const struct intel_fdi_funcs *fdi;
313
314 /* Display internal color functions */
315 const struct intel_color_funcs *color;
316
317 /* Display internal audio functions */
318 const struct intel_audio_funcs *audio;
319 } funcs;
320
321 struct {
322 bool any_task_allowed;
323 struct task_struct *allowed_task;
324 } access;
325
326 struct {
327 /* backlight registers and fields in struct intel_panel */
328 struct mutex lock;
329 } backlight;
330
331 struct {
332 struct intel_global_obj obj;
333
334 struct intel_bw_info {
335 /* for each QGV point */
336 unsigned int deratedbw[I915_NUM_QGV_POINTS];
337 /* for each PSF GV point */
338 unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
339 /* Peak BW for each QGV point */
340 unsigned int peakbw[I915_NUM_QGV_POINTS];
341 u8 num_qgv_points;
342 u8 num_psf_gv_points;
343 u8 num_planes;
344 } max[6];
345 } bw;
346
347 struct {
348 /* The current hardware cdclk configuration */
349 struct intel_cdclk_config hw;
350
351 /* cdclk, divider, and ratio table from bspec */
352 const struct intel_cdclk_vals *table;
353
354 struct intel_global_obj obj;
355
356 unsigned int max_cdclk_freq;
357 unsigned int max_dotclk_freq;
358 unsigned int skl_preferred_vco_freq;
359 } cdclk;
360
361 struct {
362 struct drm_property_blob *glk_linear_degamma_lut;
363 } color;
364
365 struct {
366 /* The current hardware dbuf configuration */
367 u8 enabled_slices;
368
369 struct intel_global_obj obj;
370 } dbuf;
371
372 struct {
373 /*
374 * dkl.phy_lock protects against concurrent access of the
375 * Dekel TypeC PHYs.
376 */
377 spinlock_t phy_lock;
378 } dkl;
379
380 struct {
381 struct intel_dmc *dmc;
382 intel_wakeref_t wakeref;
383 } dmc;
384
385 struct {
386 /* VLV/CHV/BXT/GLK DSI MMIO register base address */
387 u32 mmio_base;
388 } dsi;
389
390 struct {
391 /* list of fbdev register on this device */
392 struct intel_fbdev *fbdev;
393 } fbdev;
394
395 struct {
396 unsigned int pll_freq;
397 u32 rx_config;
398 } fdi;
399
400 struct {
401 struct list_head obj_list;
402 } global;
403
404 struct {
405 /*
406 * Base address of where the gmbus and gpio blocks are located
407 * (either on PCH or on SoC for platforms without PCH).
408 */
409 u32 mmio_base;
410
411 /*
412 * gmbus.mutex protects against concurrent usage of the single
413 * hw gmbus controller on different i2c buses.
414 */
415 struct mutex mutex;
416
417 struct intel_gmbus *bus[GMBUS_NUM_PINS];
418
419 wait_queue_head_t wait_queue;
420 } gmbus;
421
422 struct {
423 struct i915_hdcp_arbiter *arbiter;
424 bool comp_added;
425
426 /*
427 * HDCP message struct for allocation of memory which can be
428 * reused when sending message to gsc cs.
429 * this is only populated post Meteorlake
430 */
431 struct intel_hdcp_gsc_context *gsc_context;
432 /* Mutex to protect the above hdcp related values. */
433 struct mutex hdcp_mutex;
434 } hdcp;
435
436 struct {
437 /*
438 * HTI (aka HDPORT) state read during initial hw readout. Most
439 * platforms don't have HTI, so this will just stay 0. Those
440 * that do will use this later to figure out which PLLs and PHYs
441 * are unavailable for driver usage.
442 */
443 u32 state;
444 } hti;
445
446 struct {
447 /* Access with DISPLAY_INFO() */
448 const struct intel_display_device_info *__device_info;
449
450 /* Access with DISPLAY_RUNTIME_INFO() */
451 struct intel_display_runtime_info __runtime_info;
452 } info;
453
454 struct {
455 bool false_color;
456 } ips;
457
458 struct {
459 /* protects the irq masks */
460 spinlock_t lock;
461
462 /*
463 * Most platforms treat the display irq block as an always-on
464 * power domain. vlv/chv can disable it at runtime and need
465 * special care to avoid writing any of the display block
466 * registers outside of the power domain. We defer setting up
467 * the display irqs in this case to the runtime pm.
468 */
469 bool vlv_display_irqs_enabled;
470
471 /* For i915gm/i945gm vblank irq workaround */
472 u8 vblank_enabled;
473
474 int vblank_enable_count;
475
476 struct work_struct vblank_notify_work;
477
478 u32 de_irq_mask[I915_MAX_PIPES];
479 u32 pipestat_irq_mask[I915_MAX_PIPES];
480 } irq;
481
482 struct {
483 /* protected by wm.wm_mutex */
484 u16 linetime[I915_MAX_PIPES];
485 bool disable[I915_MAX_PIPES];
486 } pkgc;
487
488 struct {
489 wait_queue_head_t waitqueue;
490
491 /* mutex to protect pmdemand programming sequence */
492 struct mutex lock;
493
494 struct intel_global_obj obj;
495 } pmdemand;
496
497 struct {
498 struct i915_power_domains domains;
499
500 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
501 u32 chv_phy_control;
502
503 /* perform PHY state sanity checks? */
504 bool chv_phy_assert[2];
505 } power;
506
507 struct {
508 u32 mmio_base;
509
510 /* protects panel power sequencer state */
511 struct mutex mutex;
512 } pps;
513
514 struct {
515 struct drm_property *broadcast_rgb;
516 struct drm_property *force_audio;
517 } properties;
518
519 struct {
520 unsigned long mask;
521 } quirks;
522
523 struct {
524 /* restore state for suspend/resume and display reset */
525 struct drm_atomic_state *modeset_state;
526 struct drm_modeset_acquire_ctx reset_ctx;
527 /* modeset stuck tracking for reset */
528 atomic_t pending_fb_pin;
529 u32 saveDSPARB;
530 u32 saveSWF0[16];
531 u32 saveSWF1[16];
532 u32 saveSWF3[3];
533 u16 saveGCDGMBUS;
534 } restore;
535
536 struct {
537 enum {
538 I915_SAGV_UNKNOWN = 0,
539 I915_SAGV_DISABLED,
540 I915_SAGV_ENABLED,
541 I915_SAGV_NOT_CONTROLLED
542 } status;
543
544 u32 block_time_us;
545 } sagv;
546
547 struct {
548 /* LPT/WPT IOSF sideband protection */
549 struct mutex lock;
550 } sbi;
551
552 struct {
553 /*
554 * DG2: Mask of PHYs that were not calibrated by the firmware
555 * and should not be used.
556 */
557 u8 phy_failed_calibration;
558 } snps;
559
560 struct {
561 /*
562 * Shadows for CHV DPLL_MD regs to keep the state
563 * checker somewhat working in the presence hardware
564 * crappiness (can't read out DPLL_MD for pipes B & C).
565 */
566 u32 chv_dpll_md[I915_MAX_PIPES];
567 u32 bxt_phy_grc;
568 } state;
569
570 struct {
571 /* ordered wq for modesets */
572 struct workqueue_struct *modeset;
573
574 /* unbound hipri wq for page flips/plane updates */
575 struct workqueue_struct *flip;
576
577 /* hipri wq for commit cleanups */
578 struct workqueue_struct *cleanup;
579
580 /* unordered workqueue for all display unordered work */
581 struct workqueue_struct *unordered;
582 } wq;
583
584 /* Grouping using named structs. Keep sorted. */
585 struct drm_dp_tunnel_mgr *dp_tunnel_mgr;
586 struct intel_audio audio;
587 struct intel_dpll_global dpll;
588 struct intel_fbc *fbc[I915_MAX_FBCS];
589 struct intel_frontbuffer_tracking fb_tracking;
590 struct intel_hotplug hotplug;
591 struct intel_opregion *opregion;
592 struct intel_overlay *overlay;
593 struct intel_display_params params;
594 struct intel_vbt_data vbt;
595 struct intel_dmc_wl wl;
596 struct intel_wm wm;
597
598 struct work_struct psr_dc5_dc6_wa_work;
599};
600
601#endif /* __INTEL_DISPLAY_CORE_H__ */
602