1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
28#include "i915_reg_defs.h"
29#include "display/intel_display_reg_defs.h"
30
31/**
32 * DOC: The i915 register macro definition style guide
33 *
34 * Follow the style described here for new macros, and while changing existing
35 * macros. Do **not** mass change existing definitions just to update the style.
36 *
37 * File Layout
38 * ~~~~~~~~~~~
39 *
40 * Keep helper macros near the top. For example, _PIPE() and friends.
41 *
42 * Prefix macros that generally should not be used outside of this file with
43 * underscore '_'. For example, _PIPE() and friends, single instances of
44 * registers that are defined solely for the use by function-like macros.
45 *
46 * Avoid using the underscore prefixed macros outside of this file. There are
47 * exceptions, but keep them to a minimum.
48 *
49 * There are two basic types of register definitions: Single registers and
50 * register groups. Register groups are registers which have two or more
51 * instances, for example one per pipe, port, transcoder, etc. Register groups
52 * should be defined using function-like macros.
53 *
54 * For single registers, define the register offset first, followed by register
55 * contents.
56 *
57 * For register groups, define the register instance offsets first, prefixed
58 * with underscore, followed by a function-like macro choosing the right
59 * instance based on the parameter, followed by register contents.
60 *
61 * Define the register contents (i.e. bit and bit field macros) from most
62 * significant to least significant bit. Indent the register content macros
63 * using two extra spaces between ``#define`` and the macro name.
64 *
65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
67 * shifted in place, so they can be directly OR'd together. For convenience,
68 * function-like macros may be used to define bit fields, but do note that the
69 * macros may be needed to read as well as write the register contents.
70 *
71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
72 *
73 * Group the register and its contents together without blank lines, separate
74 * from other registers and their contents with one blank line.
75 *
76 * Indent macro values from macro names using TABs. Align values vertically. Use
77 * braces in macro values as needed to avoid unintended precedence after macro
78 * substitution. Use spaces in macro values according to kernel coding
79 * style. Use lower case in hexadecimal values.
80 *
81 * Naming
82 * ~~~~~~
83 *
84 * Try to name registers according to the specs. If the register name changes in
85 * the specs from platform to another, stick to the original name.
86 *
87 * Try to reuse existing register macro definitions. Only add new macros for
88 * new register offsets, or when the register contents have changed enough to
89 * warrant a full redefinition.
90 *
91 * When a register macro changes for a new platform, prefix the new macro using
92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
93 * prefix signifies the start platform/generation using the register.
94 *
95 * When a bit (field) macro changes or gets added for a new platform, while
96 * retaining the existing register macro, add a platform acronym or generation
97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
98 *
99 * Examples
100 * ~~~~~~~~
101 *
102 * (Note that the values in the example are indented using spaces instead of
103 * TABs to avoid misalignment in generated documentation. Use TABs in the
104 * definitions.)::
105 *
106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
109 * #define FOO_ENABLE REG_BIT(31)
110 * #define FOO_MODE_MASK REG_GENMASK(19, 16)
111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
114 *
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
117 */
118
119#define GU_CNTL_PROTECTED _MMIO(0x10100C)
120#define DEPRESENT REG_BIT(9)
121
122#define GU_CNTL _MMIO(0x101010)
123#define LMEM_INIT REG_BIT(7)
124#define DRIVERFLR REG_BIT(31)
125#define GU_DEBUG _MMIO(0x101018)
126#define DRIVERFLR_STATUS REG_BIT(31)
127
128#define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
129#define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
130#define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
131#define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
132#define GEN6_STOLEN_RESERVED_1M (0 << 4)
133#define GEN6_STOLEN_RESERVED_512K (1 << 4)
134#define GEN6_STOLEN_RESERVED_256K (2 << 4)
135#define GEN6_STOLEN_RESERVED_128K (3 << 4)
136#define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
137#define GEN7_STOLEN_RESERVED_1M (0 << 5)
138#define GEN7_STOLEN_RESERVED_256K (1 << 5)
139#define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
140#define GEN8_STOLEN_RESERVED_1M (0 << 7)
141#define GEN8_STOLEN_RESERVED_2M (1 << 7)
142#define GEN8_STOLEN_RESERVED_4M (2 << 7)
143#define GEN8_STOLEN_RESERVED_8M (3 << 7)
144#define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
145#define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
146
147/*
148 * Reset registers
149 */
150#define DEBUG_RESET_I830 _MMIO(0x6070)
151#define DEBUG_RESET_FULL (1 << 7)
152#define DEBUG_RESET_RENDER (1 << 8)
153#define DEBUG_RESET_DISPLAY (1 << 9)
154
155/*
156 * IOSF sideband
157 */
158#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
159#define IOSF_DEVFN_SHIFT 24
160#define IOSF_OPCODE_SHIFT 16
161#define IOSF_PORT_SHIFT 8
162#define IOSF_BYTE_ENABLES_SHIFT 4
163#define IOSF_BAR_SHIFT 1
164#define IOSF_SB_BUSY (1 << 0)
165#define IOSF_PORT_BUNIT 0x03
166#define IOSF_PORT_PUNIT 0x04
167#define IOSF_PORT_NC 0x11
168#define IOSF_PORT_DPIO 0x12
169#define IOSF_PORT_GPIO_NC 0x13
170#define IOSF_PORT_CCK 0x14
171#define IOSF_PORT_DPIO_2 0x1a
172#define IOSF_PORT_FLISDSI 0x1b
173#define IOSF_PORT_GPIO_SC 0x48
174#define IOSF_PORT_GPIO_SUS 0xa8
175#define IOSF_PORT_CCU 0xa9
176#define CHV_IOSF_PORT_GPIO_N 0x13
177#define CHV_IOSF_PORT_GPIO_SE 0x48
178#define CHV_IOSF_PORT_GPIO_E 0xa8
179#define CHV_IOSF_PORT_GPIO_SW 0xb2
180#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
181#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
182
183/* DPIO registers */
184#define DPIO_DEVFN 0
185
186/*
187 * Fence registers
188 * [0-7] @ 0x2000 gen2,gen3
189 * [8-15] @ 0x3000 945,g33,pnv
190 *
191 * [0-15] @ 0x3000 gen4,gen5
192 *
193 * [0-15] @ 0x100000 gen6,vlv,chv
194 * [0-31] @ 0x100000 gen7+
195 */
196#define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
197#define I830_FENCE_START_MASK 0x07f80000
198#define I830_FENCE_TILING_Y_SHIFT 12
199#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
200#define I830_FENCE_PITCH_SHIFT 4
201#define I830_FENCE_REG_VALID (1 << 0)
202#define I915_FENCE_MAX_PITCH_VAL 4
203#define I830_FENCE_MAX_PITCH_VAL 6
204#define I830_FENCE_MAX_SIZE_VAL (1 << 8)
205
206#define I915_FENCE_START_MASK 0x0ff00000
207#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
208
209#define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
210#define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
211#define I965_FENCE_PITCH_SHIFT 2
212#define I965_FENCE_TILING_Y_SHIFT 1
213#define I965_FENCE_REG_VALID (1 << 0)
214#define I965_FENCE_MAX_PITCH_VAL 0x0400
215
216#define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
217#define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
218#define GEN6_FENCE_PITCH_SHIFT 32
219#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
220
221
222/* control register for cpu gtt access */
223#define TILECTL _MMIO(0x101000)
224#define TILECTL_SWZCTL (1 << 0)
225#define TILECTL_TLBPF (1 << 1)
226#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
227#define TILECTL_BACKSNOOP_DIS (1 << 3)
228
229/*
230 * Instruction and interrupt control regs
231 */
232#define PGTBL_CTL _MMIO(0x02020)
233#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
234#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
235#define PGTBL_ER _MMIO(0x02024)
236#define PRB0_BASE (0x2030 - 0x30)
237#define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
238#define PRB2_BASE (0x2050 - 0x30) /* gen3 */
239#define SRB0_BASE (0x2100 - 0x30) /* gen2 */
240#define SRB1_BASE (0x2110 - 0x30) /* gen2 */
241#define SRB2_BASE (0x2120 - 0x30) /* 830 */
242#define SRB3_BASE (0x2130 - 0x30) /* 830 */
243#define RENDER_RING_BASE 0x02000
244#define BSD_RING_BASE 0x04000
245#define GEN6_BSD_RING_BASE 0x12000
246#define GEN8_BSD2_RING_BASE 0x1c000
247#define GEN11_BSD_RING_BASE 0x1c0000
248#define GEN11_BSD2_RING_BASE 0x1c4000
249#define GEN11_BSD3_RING_BASE 0x1d0000
250#define GEN11_BSD4_RING_BASE 0x1d4000
251#define XEHP_BSD5_RING_BASE 0x1e0000
252#define XEHP_BSD6_RING_BASE 0x1e4000
253#define XEHP_BSD7_RING_BASE 0x1f0000
254#define XEHP_BSD8_RING_BASE 0x1f4000
255#define VEBOX_RING_BASE 0x1a000
256#define GEN11_VEBOX_RING_BASE 0x1c8000
257#define GEN11_VEBOX2_RING_BASE 0x1d8000
258#define XEHP_VEBOX3_RING_BASE 0x1e8000
259#define XEHP_VEBOX4_RING_BASE 0x1f8000
260#define MTL_GSC_RING_BASE 0x11a000
261#define GEN12_COMPUTE0_RING_BASE 0x1a000
262#define GEN12_COMPUTE1_RING_BASE 0x1c000
263#define GEN12_COMPUTE2_RING_BASE 0x1e000
264#define GEN12_COMPUTE3_RING_BASE 0x26000
265#define BLT_RING_BASE 0x22000
266#define XEHPC_BCS1_RING_BASE 0x3e0000
267#define XEHPC_BCS2_RING_BASE 0x3e2000
268#define XEHPC_BCS3_RING_BASE 0x3e4000
269#define XEHPC_BCS4_RING_BASE 0x3e6000
270#define XEHPC_BCS5_RING_BASE 0x3e8000
271#define XEHPC_BCS6_RING_BASE 0x3ea000
272#define XEHPC_BCS7_RING_BASE 0x3ec000
273#define XEHPC_BCS8_RING_BASE 0x3ee000
274#define DG1_GSC_HECI1_BASE 0x00258000
275#define DG1_GSC_HECI2_BASE 0x00259000
276#define DG2_GSC_HECI1_BASE 0x00373000
277#define DG2_GSC_HECI2_BASE 0x00374000
278#define MTL_GSC_HECI1_BASE 0x00116000
279#define MTL_GSC_HECI2_BASE 0x00117000
280
281#define HECI_H_CSR(base) _MMIO((base) + 0x4)
282#define HECI_H_CSR_IE REG_BIT(0)
283#define HECI_H_CSR_IS REG_BIT(1)
284#define HECI_H_CSR_IG REG_BIT(2)
285#define HECI_H_CSR_RDY REG_BIT(3)
286#define HECI_H_CSR_RST REG_BIT(4)
287
288#define HECI_H_GS1(base) _MMIO((base) + 0xc4c)
289#define HECI_H_GS1_ER_PREP REG_BIT(0)
290
291/*
292 * The FWSTS register values are FW defined and can be different between
293 * HECI1 and HECI2
294 */
295#define HECI_FWSTS1 0xc40
296#define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0)
297#define HECI1_FWSTS1_CURRENT_STATE_RESET 0
298#define HECI1_FWSTS1_PROXY_STATE_NORMAL 5
299#define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9)
300#define HECI_FWSTS2 0xc48
301#define HECI_FWSTS3 0xc60
302#define HECI_FWSTS4 0xc64
303#define HECI_FWSTS5 0xc68
304#define HECI1_FWSTS5_HUC_AUTH_DONE (1 << 19)
305#define HECI_FWSTS6 0xc6c
306
307/* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */
308#define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \
309 HECI_FWSTS1, \
310 HECI_FWSTS2, \
311 HECI_FWSTS3, \
312 HECI_FWSTS4, \
313 HECI_FWSTS5, \
314 HECI_FWSTS6))
315
316#define HSW_GTT_CACHE_EN _MMIO(0x4024)
317#define GTT_CACHE_EN_ALL 0xF0007FFF
318#define GEN7_WR_WATERMARK _MMIO(0x4028)
319#define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
320#define ARB_MODE _MMIO(0x4030)
321#define ARB_MODE_SWIZZLE_SNB (1 << 4)
322#define ARB_MODE_SWIZZLE_IVB (1 << 5)
323#define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
324#define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
325/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
326#define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
327#define GEN7_LRA_LIMITS_REG_NUM 13
328#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
329#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
330
331#define GEN7_ERR_INT _MMIO(0x44040)
332#define ERR_INT_POISON (1 << 31)
333#define ERR_INT_INVALID_GTT_PTE (1 << 29)
334#define ERR_INT_INVALID_PTE_DATA (1 << 28)
335#define ERR_INT_SPRITE_C_FAULT (1 << 23)
336#define ERR_INT_PRIMARY_C_FAULT (1 << 22)
337#define ERR_INT_CURSOR_C_FAULT (1 << 21)
338#define ERR_INT_SPRITE_B_FAULT (1 << 20)
339#define ERR_INT_PRIMARY_B_FAULT (1 << 19)
340#define ERR_INT_CURSOR_B_FAULT (1 << 18)
341#define ERR_INT_SPRITE_A_FAULT (1 << 17)
342#define ERR_INT_PRIMARY_A_FAULT (1 << 16)
343#define ERR_INT_CURSOR_A_FAULT (1 << 15)
344#define ERR_INT_MMIO_UNCLAIMED (1 << 13)
345#define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
346#define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
347#define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
348#define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
349#define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
350#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
351#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
352#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
353
354#define FPGA_DBG _MMIO(0x42300)
355#define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
356
357#define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
358#define CLAIM_ER_CLR REG_BIT(31)
359#define CLAIM_ER_OVERFLOW REG_BIT(16)
360#define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0)
361
362#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
363#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
364#define SCPD0 _MMIO(0x209c) /* 915+ only */
365#define SCPD_FBC_IGNORE_3D (1 << 6)
366#define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5)
367#define GEN2_IER _MMIO(0x20a0)
368#define GEN2_IIR _MMIO(0x20a4)
369#define GEN2_IMR _MMIO(0x20a8)
370#define GEN2_ISR _MMIO(0x20ac)
371
372#define GEN2_IRQ_REGS I915_IRQ_REGS(GEN2_IMR, \
373 GEN2_IER, \
374 GEN2_IIR)
375
376#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
377#define GINT_DIS (1 << 22)
378#define GCFG_DIS (1 << 8)
379#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
380#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
381#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
382#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
383#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
384#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
385#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
386#define VLV_PCBR_ADDR_SHIFT 12
387
388#define EIR _MMIO(0x20b0)
389#define EMR _MMIO(0x20b4)
390#define ESR _MMIO(0x20b8)
391#define GM45_ERROR_PAGE_TABLE (1 << 5)
392#define GM45_ERROR_MEM_PRIV (1 << 4)
393#define I915_ERROR_PAGE_TABLE (1 << 4)
394#define GM45_ERROR_CP_PRIV (1 << 3)
395#define I915_ERROR_MEMORY_REFRESH (1 << 1)
396#define I915_ERROR_INSTRUCTION (1 << 0)
397
398#define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR)
399
400#define INSTPM _MMIO(0x20c0)
401#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
402#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
403 will not assert AGPBUSY# and will only
404 be delivered when out of C3. */
405#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
406#define INSTPM_TLB_INVALIDATE (1 << 9)
407#define INSTPM_SYNC_FLUSH (1 << 5)
408#define MEM_MODE _MMIO(0x20cc)
409#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
410#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
411#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
412#define FW_BLC _MMIO(0x20d8)
413#define FW_BLC2 _MMIO(0x20dc)
414#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
415#define FW_BLC_SELF_EN_MASK REG_BIT(31)
416#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
417#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
418#define MM_BURST_LENGTH 0x00700000
419#define MM_FIFO_WATERMARK 0x0001F000
420#define LM_BURST_LENGTH 0x00000700
421#define LM_FIFO_WATERMARK 0x0000001F
422#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
423
424/*
425 * Make render/texture TLB fetches lower priority than associated data
426 * fetches. This is not turned on by default.
427 */
428#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
429
430/* Isoch request wait on GTT enable (Display A/B/C streams).
431 * Make isoch requests stall on the TLB update. May cause
432 * display underruns (test mode only)
433 */
434#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
435
436/* Block grant count for isoch requests when block count is
437 * set to a finite value.
438 */
439#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
440#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
441#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
442#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
443#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
444
445/* Enable render writes to complete in C2/C3/C4 power states.
446 * If this isn't enabled, render writes are prevented in low
447 * power states. That seems bad to me.
448 */
449#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
450
451/* This acknowledges an async flip immediately instead
452 * of waiting for 2TLB fetches.
453 */
454#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
455
456/* Enables non-sequential data reads through arbiter
457 */
458#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
459
460/* Disable FSB snooping of cacheable write cycles from binner/render
461 * command stream
462 */
463#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
464
465/* Arbiter time slice for non-isoch streams */
466#define MI_ARB_TIME_SLICE_MASK (7 << 5)
467#define MI_ARB_TIME_SLICE_1 (0 << 5)
468#define MI_ARB_TIME_SLICE_2 (1 << 5)
469#define MI_ARB_TIME_SLICE_4 (2 << 5)
470#define MI_ARB_TIME_SLICE_6 (3 << 5)
471#define MI_ARB_TIME_SLICE_8 (4 << 5)
472#define MI_ARB_TIME_SLICE_10 (5 << 5)
473#define MI_ARB_TIME_SLICE_14 (6 << 5)
474#define MI_ARB_TIME_SLICE_16 (7 << 5)
475
476/* Low priority grace period page size */
477#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
478#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
479
480/* Disable display A/B trickle feed */
481#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
482
483/* Set display plane priority */
484#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
485#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
486
487#define MI_STATE _MMIO(0x20e4) /* gen2 only */
488#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
489#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
490
491/* On modern GEN architectures interrupt control consists of two sets
492 * of registers. The first set pertains to the ring generating the
493 * interrupt. The second control is for the functional block generating the
494 * interrupt. These are PM, GT, DE, etc.
495 *
496 * Luckily *knocks on wood* all the ring interrupt bits match up with the
497 * GT interrupt bits, so we don't need to duplicate the defines.
498 *
499 * These defines should cover us well from SNB->HSW with minor exceptions
500 * it can also work on ILK.
501 */
502#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
503#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
504#define GT_BLT_USER_INTERRUPT (1 << 22)
505#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
506#define GT_BSD_USER_INTERRUPT (1 << 12)
507#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
508#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */
509#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
510#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
511#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
512#define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
513#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
514#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
515#define GT_RENDER_USER_INTERRUPT (1 << 0)
516
517#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
518#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
519
520#define GT_PARITY_ERROR(dev_priv) \
521 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
522 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
523
524/* These are all the "old" interrupts */
525#define ILK_BSD_USER_INTERRUPT (1 << 5)
526
527#define I915_PM_INTERRUPT (1 << 31)
528#define I915_ISP_INTERRUPT (1 << 22)
529#define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
530#define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
531#define I915_MIPIC_INTERRUPT (1 << 19)
532#define I915_MIPIA_INTERRUPT (1 << 18)
533#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
534#define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
535#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
536#define I915_MASTER_ERROR_INTERRUPT (1 << 15)
537#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
538#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
539#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
540#define I915_HWB_OOM_INTERRUPT (1 << 13)
541#define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
542#define I915_SYNC_STATUS_INTERRUPT (1 << 12)
543#define I915_MISC_INTERRUPT (1 << 11)
544#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
545#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
546#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
547#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
548#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
549#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
550#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
551#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
552#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
553#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
554#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
555#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
556#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
557#define I915_DEBUG_INTERRUPT (1 << 2)
558#define I915_WINVALID_INTERRUPT (1 << 1)
559#define I915_USER_INTERRUPT (1 << 1)
560#define I915_ASLE_INTERRUPT (1 << 0)
561#define I915_BSD_USER_INTERRUPT (1 << 25)
562
563#define GEN6_BSD_RNCID _MMIO(0x12198)
564
565#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
566#define GEN7_FF_SCHED_MASK 0x0077070
567#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
568#define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
569#define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
570#define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
571#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
572#define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */
573#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
574#define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)
575#define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)
576#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
577#define GEN7_FF_VS_SCHED_HW (0x0 << 12)
578#define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)
579#define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)
580#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
581#define GEN7_FF_DS_SCHED_HW (0x0 << 4)
582
583#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
584#define ILK_FBCQ_DIS REG_BIT(22)
585#define ILK_PABSTRETCH_DIS REG_BIT(21)
586#define ILK_SABSTRETCH_DIS REG_BIT(20)
587#define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20)
588#define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
589#define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
590#define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
591#define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
592#define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18)
593#define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
594#define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
595#define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
596#define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
597
598#define DPLL_TEST _MMIO(0x606c)
599#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
600#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
601#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
602#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
603#define DPLLB_TEST_N_BYPASS (1 << 19)
604#define DPLLB_TEST_M_BYPASS (1 << 18)
605#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
606#define DPLLA_TEST_N_BYPASS (1 << 3)
607#define DPLLA_TEST_M_BYPASS (1 << 2)
608#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
609
610#define D_STATE _MMIO(0x6104)
611#define DSTATE_GFX_RESET_I830 (1 << 6)
612#define DSTATE_PLL_D3_OFF (1 << 3)
613#define DSTATE_GFX_CLOCK_GATING (1 << 1)
614#define DSTATE_DOT_CLOCK_GATING (1 << 0)
615
616#define DSPCLK_GATE_D _MMIO(0x6200)
617#define VLV_DSPCLK_GATE_D _MMIO(VLV_DISPLAY_BASE + 0x6200)
618# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
619# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
620# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
621# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
622# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
623# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
624# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
625# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
626# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
627# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
628# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
629# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
630# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
631# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
632# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
633# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
634# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
635# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
636# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
637# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
638# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
639# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
640# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
641# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
642# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
643# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
644# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
645# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
646# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
647/*
648 * This bit must be set on the 830 to prevent hangs when turning off the
649 * overlay scaler.
650 */
651# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
652# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
653# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
654# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
655# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
656
657#define RENCLK_GATE_D1 _MMIO(0x6204)
658# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
659# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
660# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
661# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
662# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
663# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
664# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
665# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
666# define MAG_CLOCK_GATE_DISABLE (1 << 5)
667/* This bit must be unset on 855,865 */
668# define MECI_CLOCK_GATE_DISABLE (1 << 4)
669# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
670# define MEC_CLOCK_GATE_DISABLE (1 << 2)
671# define MECO_CLOCK_GATE_DISABLE (1 << 1)
672/* This bit must be set on 855,865. */
673# define SV_CLOCK_GATE_DISABLE (1 << 0)
674# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
675# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
676# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
677# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
678# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
679# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
680# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
681# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
682# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
683# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
684# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
685# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
686# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
687# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
688# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
689# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
690# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
691
692# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
693/* This bit must always be set on 965G/965GM */
694# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
695# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
696# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
697# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
698# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
699# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
700/* This bit must always be set on 965G */
701# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
702# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
703# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
704# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
705# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
706# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
707# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
708# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
709# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
710# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
711# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
712# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
713# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
714# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
715# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
716# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
717# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
718# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
719# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
720
721#define RENCLK_GATE_D2 _MMIO(0x6208)
722#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
723#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
724#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
725
726#define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
727#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
728
729#define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
730#define DEUC _MMIO(0x6214) /* CRL only */
731
732#define BXT_RP_STATE_CAP _MMIO(0x138170)
733#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
734
735#define MTL_RP_STATE_CAP _MMIO(0x138000)
736#define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
737#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
738#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
739
740#define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c)
741#define MTL_MPE_FREQUENCY _MMIO(0x13802c)
742#define MTL_RPE_MASK REG_GENMASK(8, 0)
743
744#define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
745#define GT0_PERF_LIMIT_REASONS_MASK 0xde3
746#define PROCHOT_MASK REG_BIT(0)
747#define THERMAL_LIMIT_MASK REG_BIT(1)
748#define RATL_MASK REG_BIT(5)
749#define VR_THERMALERT_MASK REG_BIT(6)
750#define VR_TDC_MASK REG_BIT(7)
751#define POWER_LIMIT_4_MASK REG_BIT(8)
752#define POWER_LIMIT_1_MASK REG_BIT(10)
753#define POWER_LIMIT_2_MASK REG_BIT(11)
754#define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
755#define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030)
756
757#define CHV_CLK_CTL1 _MMIO(0x101100)
758#define VLV_CLK_CTL2 _MMIO(0x101104)
759#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
760
761/*
762 * GEN9 clock gating regs
763 */
764#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
765#define DARBF_GATING_DIS REG_BIT(27)
766#define MTL_PIPEDMC_GATING_DIS(pipe) REG_BIT(15 - (pipe))
767#define PWM2_GATING_DIS REG_BIT(14)
768#define PWM1_GATING_DIS REG_BIT(13)
769
770#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
771#define TGL_VRH_GATING_DIS REG_BIT(31)
772#define DPT_GATING_DIS REG_BIT(22)
773
774#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
775#define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
776#define PIPEB_HLINE_INT_EN REG_BIT(28)
777#define PIPEB_VBLANK_INT_EN REG_BIT(27)
778#define SPRITED_FLIP_DONE_INT_EN REG_BIT(26)
779#define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25)
780#define PLANEB_FLIP_DONE_INT_EN REG_BIT(24)
781#define PIPE_PSR_INT_EN REG_BIT(22)
782#define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21)
783#define PIPEA_HLINE_INT_EN REG_BIT(20)
784#define PIPEA_VBLANK_INT_EN REG_BIT(19)
785#define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18)
786#define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17)
787#define PLANEA_FLIPDONE_INT_EN REG_BIT(16)
788#define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13)
789#define PIPEC_HLINE_INT_EN REG_BIT(12)
790#define PIPEC_VBLANK_INT_EN REG_BIT(11)
791#define SPRITEF_FLIPDONE_INT_EN REG_BIT(10)
792#define SPRITEE_FLIPDONE_INT_EN REG_BIT(9)
793#define PLANEC_FLIPDONE_INT_EN REG_BIT(8)
794
795#define PCH_3DCGDIS0 _MMIO(0x46020)
796# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
797# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
798
799#define PCH_3DCGDIS1 _MMIO(0x46024)
800# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
801
802/* Display Internal Timeout Register */
803#define RM_TIMEOUT _MMIO(0x42060)
804#define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)
805#define MMIO_TIMEOUT_US(us) ((us) << 0)
806
807/* interrupts */
808#define DE_MASTER_IRQ_CONTROL (1 << 31)
809#define DE_SPRITEB_FLIP_DONE (1 << 29)
810#define DE_SPRITEA_FLIP_DONE (1 << 28)
811#define DE_PLANEB_FLIP_DONE (1 << 27)
812#define DE_PLANEA_FLIP_DONE (1 << 26)
813#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
814#define DE_PCU_EVENT (1 << 25)
815#define DE_GTT_FAULT (1 << 24)
816#define DE_POISON (1 << 23)
817#define DE_PERFORM_COUNTER (1 << 22)
818#define DE_PCH_EVENT (1 << 21)
819#define DE_AUX_CHANNEL_A (1 << 20)
820#define DE_DP_A_HOTPLUG (1 << 19)
821#define DE_GSE (1 << 18)
822#define DE_PIPEB_VBLANK (1 << 15)
823#define DE_PIPEB_EVEN_FIELD (1 << 14)
824#define DE_PIPEB_ODD_FIELD (1 << 13)
825#define DE_PIPEB_LINE_COMPARE (1 << 12)
826#define DE_PIPEB_VSYNC (1 << 11)
827#define DE_PIPEB_CRC_DONE (1 << 10)
828#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
829#define DE_PIPEA_VBLANK (1 << 7)
830#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
831#define DE_PIPEA_EVEN_FIELD (1 << 6)
832#define DE_PIPEA_ODD_FIELD (1 << 5)
833#define DE_PIPEA_LINE_COMPARE (1 << 4)
834#define DE_PIPEA_VSYNC (1 << 3)
835#define DE_PIPEA_CRC_DONE (1 << 2)
836#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
837#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
838#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
839
840#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
841#define MASTER_INTERRUPT_ENABLE (1 << 31)
842
843#define DEISR _MMIO(0x44000)
844#define DEIMR _MMIO(0x44004)
845#define DEIIR _MMIO(0x44008)
846#define DEIER _MMIO(0x4400c)
847
848#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \
849 DEIER, \
850 DEIIR)
851
852#define GTISR _MMIO(0x44010)
853#define GTIMR _MMIO(0x44014)
854#define GTIIR _MMIO(0x44018)
855#define GTIER _MMIO(0x4401c)
856
857#define GT_IRQ_REGS I915_IRQ_REGS(GTIMR, \
858 GTIER, \
859 GTIIR)
860
861#define GEN8_MASTER_IRQ _MMIO(0x44200)
862#define GEN8_MASTER_IRQ_CONTROL (1 << 31)
863#define GEN8_PCU_IRQ (1 << 30)
864#define GEN8_DE_PCH_IRQ (1 << 23)
865#define GEN8_DE_MISC_IRQ (1 << 22)
866#define GEN8_DE_PORT_IRQ (1 << 20)
867#define GEN8_DE_PIPE_C_IRQ (1 << 18)
868#define GEN8_DE_PIPE_B_IRQ (1 << 17)
869#define GEN8_DE_PIPE_A_IRQ (1 << 16)
870#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
871#define GEN8_GT_VECS_IRQ (1 << 6)
872#define GEN8_GT_GUC_IRQ (1 << 5)
873#define GEN8_GT_PM_IRQ (1 << 4)
874#define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
875#define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
876#define GEN8_GT_BCS_IRQ (1 << 1)
877#define GEN8_GT_RCS_IRQ (1 << 0)
878
879#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
880#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
881#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
882#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
883
884#define GEN8_GT_IRQ_REGS(which) I915_IRQ_REGS(GEN8_GT_IMR(which), \
885 GEN8_GT_IER(which), \
886 GEN8_GT_IIR(which))
887
888#define GEN8_RCS_IRQ_SHIFT 0
889#define GEN8_BCS_IRQ_SHIFT 16
890#define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */
891#define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */
892#define GEN8_VECS_IRQ_SHIFT 0
893#define GEN8_WD_IRQ_SHIFT 16
894
895#define GEN8_PCU_ISR _MMIO(0x444e0)
896#define GEN8_PCU_IMR _MMIO(0x444e4)
897#define GEN8_PCU_IIR _MMIO(0x444e8)
898#define GEN8_PCU_IER _MMIO(0x444ec)
899
900#define GEN8_PCU_IRQ_REGS I915_IRQ_REGS(GEN8_PCU_IMR, \
901 GEN8_PCU_IER, \
902 GEN8_PCU_IIR)
903
904#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
905#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
906#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
907#define GEN11_GU_MISC_IER _MMIO(0x444fc)
908#define GEN11_GU_MISC_GSE (1 << 27)
909
910#define GEN11_GU_MISC_IRQ_REGS I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
911 GEN11_GU_MISC_IER, \
912 GEN11_GU_MISC_IIR)
913
914#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
915#define GEN11_MASTER_IRQ (1 << 31)
916#define GEN11_PCU_IRQ (1 << 30)
917#define GEN11_GU_MISC_IRQ (1 << 29)
918#define GEN11_DISPLAY_IRQ (1 << 16)
919#define GEN11_GT_DW_IRQ(x) (1 << (x))
920#define GEN11_GT_DW1_IRQ (1 << 1)
921#define GEN11_GT_DW0_IRQ (1 << 0)
922
923#define DG1_MSTR_TILE_INTR _MMIO(0x190008)
924#define DG1_MSTR_IRQ REG_BIT(31)
925#define DG1_MSTR_TILE(t) REG_BIT(t)
926
927#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
928/* Required on all Ironlake and Sandybridge according to the B-Spec. */
929#define ILK_ELPIN_409_SELECT REG_BIT(25)
930#define ILK_DPARB_GATE REG_BIT(22)
931#define ILK_VSDPFD_FULL REG_BIT(21)
932
933#define ILK_DSPCLK_GATE_D _MMIO(0x42020)
934#define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28)
935#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9)
936#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE REG_BIT(8)
937#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE REG_BIT(7)
938#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE REG_BIT(5)
939
940#define IVB_CHICKEN3 _MMIO(0x4200c)
941#define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5)
942#define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2)
943
944#define CHICKEN_PAR1_1 _MMIO(0x42080)
945#define IGNORE_KVMR_PIPE_A REG_BIT(23)
946#define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
947#define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16)
948#define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15)
949#define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */
950#define FORCE_ARB_IDLE_PLANES REG_BIT(14)
951#define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3)
952#define IGNORE_PSR2_HW_TRACKING REG_BIT(1)
953
954#define CHICKEN_PAR2_1 _MMIO(0x42090)
955#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
956
957#define _CHICKEN_PIPESL_1_A 0x420b0
958#define _CHICKEN_PIPESL_1_B 0x420b4
959#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
960#define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27)
961#define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
962#define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
963#define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
964#define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
965#define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25)
966#define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
967#define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
968#define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
969#define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
970#define HSW_FBCQ_DIS REG_BIT(22)
971#define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
972#define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */
973#define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0)
974#define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
975#define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
976#define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
977#define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
978#define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */
979
980#define DISP_ARB_CTL _MMIO(0x45000)
981#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
982#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
983#define DISP_FBC_WM_DIS REG_BIT(15)
984
985#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
986#define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
987#define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
988#define _LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25)
989#define _LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24)
990#define _LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23)
991#define LATENCY_REPORTING_REMOVED(pipe) _PICK((pipe), \
992 _LATENCY_REPORTING_REMOVED_PIPE_A, \
993 _LATENCY_REPORTING_REMOVED_PIPE_B, \
994 _LATENCY_REPORTING_REMOVED_PIPE_C, \
995 _LATENCY_REPORTING_REMOVED_PIPE_D)
996#define ICL_DELAY_PMRSP REG_BIT(22)
997#define DISABLE_FLR_SRC REG_BIT(15)
998#define MASK_WAKEMEM REG_BIT(13)
999#define DDI_CLOCK_REG_ACCESS REG_BIT(7)
1000
1001#define GMD_ID_DISPLAY _MMIO(0x510a0)
1002#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
1003#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
1004#define GMD_ID_STEP REG_GENMASK(5, 0)
1005
1006/* PCH */
1007
1008#define SDEISR _MMIO(0xc4000)
1009#define SDEIMR _MMIO(0xc4004)
1010#define SDEIIR _MMIO(0xc4008)
1011#define SDEIER _MMIO(0xc400c)
1012
1013/* Icelake PPS_DATA and _ECC DIP Registers.
1014 * These are available for transcoders B,C and eDP.
1015 * Adding the _A so as to reuse the _MMIO_TRANS2
1016 * definition, with which it offsets to the right location.
1017 */
1018
1019#define _TRANSA_CHICKEN1 0xf0060
1020#define _TRANSB_CHICKEN1 0xf1060
1021#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
1022#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
1023#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
1024
1025#define _TRANSA_CHICKEN2 0xf0064
1026#define _TRANSB_CHICKEN2 0xf1064
1027#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
1028#define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31)
1029#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29)
1030#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
1031#define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
1032#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26)
1033#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25)
1034
1035#define SOUTH_CHICKEN1 _MMIO(0xc2000)
1036#define FDIA_PHASE_SYNC_SHIFT_OVR 19
1037#define FDIA_PHASE_SYNC_SHIFT_EN 18
1038#define INVERT_DDIE_HPD REG_BIT(28)
1039#define INVERT_DDID_HPD_MTP REG_BIT(27)
1040#define INVERT_TC4_HPD REG_BIT(26)
1041#define INVERT_TC3_HPD REG_BIT(25)
1042#define INVERT_TC2_HPD REG_BIT(24)
1043#define INVERT_TC1_HPD REG_BIT(23)
1044#define INVERT_DDID_HPD (1 << 18)
1045#define INVERT_DDIC_HPD (1 << 17)
1046#define INVERT_DDIB_HPD (1 << 16)
1047#define INVERT_DDIA_HPD (1 << 15)
1048#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
1049#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
1050#define FDI_BC_BIFURCATION_SELECT (1 << 12)
1051#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
1052#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
1053#define SBCLK_RUN_REFCLK_DIS (1 << 7)
1054#define ICP_SECOND_PPS_IO_SELECT REG_BIT(2)
1055#define SPT_PWM_GRANULARITY (1 << 0)
1056#define SOUTH_CHICKEN2 _MMIO(0xc2004)
1057#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
1058#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
1059#define LPT_PWM_GRANULARITY (1 << 5)
1060#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
1061
1062#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
1063#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
1064#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
1065#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
1066#define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
1067#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
1068#define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
1069#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
1070
1071#define VLV_PMWGICZ _MMIO(0x1300a4)
1072
1073#define HSW_EDRAM_CAP _MMIO(0x120010)
1074#define EDRAM_ENABLED 0x1
1075#define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
1076#define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
1077#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
1078
1079#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
1080#define GEN6_PCODE_READY (1 << 31)
1081#define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
1082#define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
1083#define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
1084#define GEN6_PCODE_ERROR_MASK 0xFF
1085#define GEN6_PCODE_SUCCESS 0x0
1086#define GEN6_PCODE_ILLEGAL_CMD 0x1
1087#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
1088#define GEN6_PCODE_TIMEOUT 0x3
1089#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
1090#define GEN7_PCODE_TIMEOUT 0x2
1091#define GEN7_PCODE_ILLEGAL_DATA 0x3
1092#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
1093#define GEN11_PCODE_LOCKED 0x6
1094#define GEN11_PCODE_REJECTED 0x11
1095#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
1096#define GEN6_PCODE_WRITE_RC6VIDS 0x4
1097#define GEN6_PCODE_READ_RC6VIDS 0x5
1098#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
1099#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
1100#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
1101#define GEN9_PCODE_READ_MEM_LATENCY 0x6
1102#define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24)
1103#define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16)
1104#define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8)
1105#define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
1106#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
1107#define SKL_PCODE_CDCLK_CONTROL 0x7
1108#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
1109#define SKL_CDCLK_READY_FOR_CHANGE 0x1
1110#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
1111#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
1112#define GEN6_READ_OC_PARAMS 0xc
1113#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
1114#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
1115#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
1116#define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
1117#define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D
1118#define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0)
1119#define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK
1120#define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27)
1121#define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31)
1122#define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16)
1123#define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28)
1124#define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
1125#define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
1126#define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
1127#define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
1128 ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
1129 (DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
1130 (DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
1131#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
1132#define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
1133#define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
1134#define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
1135#define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
1136#define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
1137#define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
1138#define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
1139#define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
1140#define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
1141#define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
1142#define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
1143#define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
1144#define GEN6_PCODE_READ_D_COMP 0x10
1145#define GEN6_PCODE_WRITE_D_COMP 0x11
1146#define ICL_PCODE_EXIT_TCCOLD 0x12
1147#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
1148#define DISPLAY_IPS_CONTROL 0x19
1149#define TGL_PCODE_TCCOLD 0x26
1150#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
1151#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
1152#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
1153 /* See also IPS_CTL */
1154#define IPS_PCODE_CONTROL (1 << 30)
1155#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
1156#define GEN9_PCODE_SAGV_CONTROL 0x21
1157#define GEN9_SAGV_DISABLE 0x0
1158#define GEN9_SAGV_IS_DISABLED 0x1
1159#define GEN9_SAGV_ENABLE 0x3
1160#define DG1_PCODE_STATUS 0x7E
1161#define DG1_UNCORE_GET_INIT_STATUS 0x0
1162#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
1163#define PCODE_POWER_SETUP 0x7C
1164#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
1165#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
1166#define POWER_SETUP_I1_WATTS REG_BIT(31)
1167#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
1168#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
1169#define POWER_SETUP_SUBCOMMAND_G8_ENABLE 0x6
1170#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
1171#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
1172/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
1173#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
1174#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
1175/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
1176/* XEHP_PCODE_FREQUENCY_CONFIG param2 */
1177#define PCODE_MBOX_DOMAIN_NONE 0x0
1178#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
1179#define GEN6_PCODE_DATA _MMIO(0x138128)
1180#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
1181#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
1182#define GEN6_PCODE_DATA1 _MMIO(0x13812C)
1183
1184#define MTL_PCODE_STOLEN_ACCESS _MMIO(0x138914)
1185#define STOLEN_ACCESS_ALLOWED 0x1
1186
1187/* IVYBRIDGE DPF */
1188#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
1189#define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
1190#define GEN7_PARITY_ERROR_VALID (1 << 13)
1191#define GEN7_L3CDERRST1_BANK_MASK (3 << 11)
1192#define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8)
1193#define GEN7_PARITY_ERROR_ROW(reg) \
1194 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
1195#define GEN7_PARITY_ERROR_BANK(reg) \
1196 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
1197#define GEN7_PARITY_ERROR_SUBBANK(reg) \
1198 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
1199#define GEN7_L3CDERRST1_ENABLE (1 << 7)
1200
1201/* These are the 4 32-bit write offset registers for each stream
1202 * output buffer. It determines the offset from the
1203 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
1204 */
1205#define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
1206
1207#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
1208#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
1209#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
1210#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
1211#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
1212
1213#define GGC _MMIO(0x108040)
1214#define GMS_MASK REG_GENMASK(15, 8)
1215#define GGMS_MASK REG_GENMASK(7, 6)
1216
1217#define GEN6_GSMBASE _MMIO(0x108100)
1218#define GEN6_DSMBASE _MMIO(0x1080C0)
1219#define GEN6_BDSM_MASK REG_GENMASK64(31, 20)
1220#define GEN11_BDSM_MASK REG_GENMASK64(63, 20)
1221
1222#define XEHP_CLOCK_GATE_DIS _MMIO(0x101014)
1223#define SGSI_SIDECLK_DIS REG_BIT(17)
1224#define SGGI_DIS REG_BIT(15)
1225#define SGR_DIS REG_BIT(13)
1226
1227#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
1228#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
1229#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
1230#define SPI_STATIC_REGIONS _MMIO(0x102090)
1231#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
1232#define OROM_OFFSET _MMIO(0x1020c0)
1233#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
1234
1235#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
1236#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
1237#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
1238#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
1239
1240#define MTL_MEDIA_GSI_BASE 0x380000
1241
1242#endif /* _I915_REG_H_ */
1243