1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2020 Intel Corporation
4 *
5 * DisplayPort support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code).
6 */
7
8#include <linux/string_helpers.h>
9
10#include <drm/drm_print.h>
11
12#include "g4x_dp.h"
13#include "i915_reg.h"
14#include "i915_utils.h"
15#include "intel_audio.h"
16#include "intel_backlight.h"
17#include "intel_connector.h"
18#include "intel_crtc.h"
19#include "intel_de.h"
20#include "intel_display_power.h"
21#include "intel_display_regs.h"
22#include "intel_display_types.h"
23#include "intel_dp.h"
24#include "intel_dp_aux.h"
25#include "intel_dp_link_training.h"
26#include "intel_dp_test.h"
27#include "intel_dpio_phy.h"
28#include "intel_encoder.h"
29#include "intel_fifo_underrun.h"
30#include "intel_hdmi.h"
31#include "intel_hotplug.h"
32#include "intel_pch_display.h"
33#include "intel_pps.h"
34
35static const struct dpll g4x_dpll[] = {
36 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, },
37 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2, },
38};
39
40static const struct dpll pch_dpll[] = {
41 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9, },
42 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8, },
43};
44
45static const struct dpll vlv_dpll[] = {
46 { .dot = 162000, .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81, },
47 { .dot = 270000, .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27, },
48};
49
50static const struct dpll chv_dpll[] = {
51 /* m2 is .22 binary fixed point */
52 { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
53 { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
54};
55
56const struct dpll *vlv_get_dpll(struct intel_display *display)
57{
58 return display->platform.cherryview ? &chv_dpll[0] : &vlv_dpll[0];
59}
60
61static void g4x_dp_set_clock(struct intel_encoder *encoder,
62 struct intel_crtc_state *pipe_config)
63{
64 struct intel_display *display = to_intel_display(encoder);
65 const struct dpll *divisor = NULL;
66 int i, count = 0;
67
68 if (display->platform.g4x) {
69 divisor = g4x_dpll;
70 count = ARRAY_SIZE(g4x_dpll);
71 } else if (HAS_PCH_SPLIT(display)) {
72 divisor = pch_dpll;
73 count = ARRAY_SIZE(pch_dpll);
74 } else if (display->platform.cherryview) {
75 divisor = chv_dpll;
76 count = ARRAY_SIZE(chv_dpll);
77 } else if (display->platform.valleyview) {
78 divisor = vlv_dpll;
79 count = ARRAY_SIZE(vlv_dpll);
80 }
81
82 if (divisor && count) {
83 for (i = 0; i < count; i++) {
84 if (pipe_config->port_clock == divisor[i].dot) {
85 pipe_config->dpll = divisor[i];
86 pipe_config->clock_set = true;
87 break;
88 }
89 }
90 }
91}
92
93static void intel_dp_prepare(struct intel_encoder *encoder,
94 const struct intel_crtc_state *pipe_config)
95{
96 struct intel_display *display = to_intel_display(encoder);
97 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
98 enum port port = encoder->port;
99 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
100 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
101
102 intel_dp_set_link_params(intel_dp,
103 link_rate: pipe_config->port_clock,
104 lane_count: pipe_config->lane_count);
105
106 /*
107 * There are four kinds of DP registers:
108 * IBX PCH
109 * SNB CPU
110 * IVB CPU
111 * CPT PCH
112 *
113 * IBX PCH and CPU are the same for almost everything,
114 * except that the CPU DP PLL is configured in this
115 * register
116 *
117 * CPT PCH is quite different, having many bits moved
118 * to the TRANS_DP_CTL register instead. That
119 * configuration happens (oddly) in ilk_pch_enable
120 */
121
122 /* Preserve the BIOS-computed detected bit. This is
123 * supposed to be read-only.
124 */
125 intel_dp->DP = intel_de_read(display, reg: intel_dp->output_reg) & DP_DETECTED;
126
127 /* Handle DP bits in common between all three register formats */
128 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
129 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
130
131 /* Split out the IBX/CPU vs CPT settings */
132
133 if (display->platform.ivybridge && port == PORT_A) {
134 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
135 intel_dp->DP |= DP_SYNC_HS_HIGH;
136 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
137 intel_dp->DP |= DP_SYNC_VS_HIGH;
138 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
139
140 if (drm_dp_enhanced_frame_cap(dpcd: intel_dp->dpcd))
141 intel_dp->DP |= DP_ENHANCED_FRAMING;
142
143 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
144 } else if (HAS_PCH_CPT(display) && port != PORT_A) {
145 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
146
147 intel_de_rmw(display, TRANS_DP_CTL(crtc->pipe),
148 TRANS_DP_ENH_FRAMING,
149 set: pipe_config->enhanced_framing ?
150 TRANS_DP_ENH_FRAMING : 0);
151 } else {
152 if (display->platform.g4x && pipe_config->limited_color_range)
153 intel_dp->DP |= DP_COLOR_RANGE_16_235;
154
155 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
156 intel_dp->DP |= DP_SYNC_HS_HIGH;
157 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
158 intel_dp->DP |= DP_SYNC_VS_HIGH;
159 intel_dp->DP |= DP_LINK_TRAIN_OFF;
160
161 if (pipe_config->enhanced_framing)
162 intel_dp->DP |= DP_ENHANCED_FRAMING;
163
164 if (display->platform.cherryview)
165 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
166 else
167 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
168 }
169}
170
171static void assert_dp_port(struct intel_dp *intel_dp, bool state)
172{
173 struct intel_display *display = to_intel_display(intel_dp);
174 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
175 bool cur_state = intel_de_read(display, reg: intel_dp->output_reg) & DP_PORT_EN;
176
177 INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
178 "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
179 dig_port->base.base.base.id, dig_port->base.base.name,
180 str_on_off(state), str_on_off(cur_state));
181}
182#define assert_dp_port_disabled(d) assert_dp_port((d), false)
183
184static void assert_edp_pll(struct intel_display *display, bool state)
185{
186 bool cur_state = intel_de_read(display, DP_A) & EDP_PLL_ENABLE;
187
188 INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
189 "eDP PLL state assertion failure (expected %s, current %s)\n",
190 str_on_off(state), str_on_off(cur_state));
191}
192#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
193#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
194
195static void ilk_edp_pll_on(struct intel_dp *intel_dp,
196 const struct intel_crtc_state *pipe_config)
197{
198 struct intel_display *display = to_intel_display(intel_dp);
199 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
200
201 assert_transcoder_disabled(display, pipe_config->cpu_transcoder);
202 assert_dp_port_disabled(intel_dp);
203 assert_edp_pll_disabled(display);
204
205 drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n",
206 pipe_config->port_clock);
207
208 intel_dp->DP &= ~EDP_PLL_FREQ_MASK;
209
210 if (pipe_config->port_clock == 162000)
211 intel_dp->DP |= EDP_PLL_FREQ_162MHZ;
212 else
213 intel_dp->DP |= EDP_PLL_FREQ_270MHZ;
214
215 intel_de_write(display, DP_A, val: intel_dp->DP);
216 intel_de_posting_read(display, DP_A);
217 udelay(usec: 500);
218
219 /*
220 * [DevILK] Work around required when enabling DP PLL
221 * while a pipe is enabled going to FDI:
222 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
223 * 2. Program DP PLL enable
224 */
225 if (display->platform.ironlake)
226 intel_wait_for_vblank_if_active(display, pipe: !crtc->pipe);
227
228 intel_dp->DP |= EDP_PLL_ENABLE;
229
230 intel_de_write(display, DP_A, val: intel_dp->DP);
231 intel_de_posting_read(display, DP_A);
232 udelay(usec: 200);
233}
234
235static void ilk_edp_pll_off(struct intel_dp *intel_dp,
236 const struct intel_crtc_state *old_crtc_state)
237{
238 struct intel_display *display = to_intel_display(intel_dp);
239
240 assert_transcoder_disabled(display, old_crtc_state->cpu_transcoder);
241 assert_dp_port_disabled(intel_dp);
242 assert_edp_pll_enabled(display);
243
244 drm_dbg_kms(display->drm, "disabling eDP PLL\n");
245
246 intel_dp->DP &= ~EDP_PLL_ENABLE;
247
248 intel_de_write(display, DP_A, val: intel_dp->DP);
249 intel_de_posting_read(display, DP_A);
250 udelay(usec: 200);
251}
252
253static bool cpt_dp_port_selected(struct intel_display *display,
254 enum port port, enum pipe *pipe)
255{
256 enum pipe p;
257
258 for_each_pipe(display, p) {
259 u32 val = intel_de_read(display, TRANS_DP_CTL(p));
260
261 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
262 *pipe = p;
263 return true;
264 }
265 }
266
267 drm_dbg_kms(display->drm, "No pipe for DP port %c found\n",
268 port_name(port));
269
270 /* must initialize pipe to something for the asserts */
271 *pipe = PIPE_A;
272
273 return false;
274}
275
276bool g4x_dp_port_enabled(struct intel_display *display,
277 i915_reg_t dp_reg, enum port port,
278 enum pipe *pipe)
279{
280 bool ret;
281 u32 val;
282
283 val = intel_de_read(display, reg: dp_reg);
284
285 ret = val & DP_PORT_EN;
286
287 /* asserts want to know the pipe even if the port is disabled */
288 if (display->platform.ivybridge && port == PORT_A)
289 *pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_IVB, val);
290 else if (HAS_PCH_CPT(display) && port != PORT_A)
291 ret &= cpt_dp_port_selected(display, port, pipe);
292 else if (display->platform.cherryview)
293 *pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_CHV, val);
294 else
295 *pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK, val);
296
297 return ret;
298}
299
300static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
301 enum pipe *pipe)
302{
303 struct intel_display *display = to_intel_display(encoder);
304 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
305 intel_wakeref_t wakeref;
306 bool ret;
307
308 wakeref = intel_display_power_get_if_enabled(display,
309 domain: encoder->power_domain);
310 if (!wakeref)
311 return false;
312
313 ret = g4x_dp_port_enabled(display, dp_reg: intel_dp->output_reg,
314 port: encoder->port, pipe);
315
316 intel_display_power_put(display, domain: encoder->power_domain, wakeref);
317
318 return ret;
319}
320
321static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state)
322{
323 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
324
325 if (crtc_state->has_pch_encoder) {
326 intel_pch_transcoder_get_m1_n1(crtc, m_n: &crtc_state->dp_m_n);
327 intel_pch_transcoder_get_m2_n2(crtc, m_n: &crtc_state->dp_m2_n2);
328 } else {
329 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder: crtc_state->cpu_transcoder,
330 m_n: &crtc_state->dp_m_n);
331 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder: crtc_state->cpu_transcoder,
332 m_n: &crtc_state->dp_m2_n2);
333 }
334}
335
336static void intel_dp_get_config(struct intel_encoder *encoder,
337 struct intel_crtc_state *pipe_config)
338{
339 struct intel_display *display = to_intel_display(encoder);
340 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
341 u32 tmp, flags = 0;
342 enum port port = encoder->port;
343 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
344
345 if (encoder->type == INTEL_OUTPUT_EDP)
346 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
347 else
348 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
349
350 tmp = intel_de_read(display, reg: intel_dp->output_reg);
351
352 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
353
354 if (HAS_PCH_CPT(display) && port != PORT_A) {
355 u32 trans_dp = intel_de_read(display,
356 TRANS_DP_CTL(crtc->pipe));
357
358 if (trans_dp & TRANS_DP_ENH_FRAMING)
359 pipe_config->enhanced_framing = true;
360
361 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
362 flags |= DRM_MODE_FLAG_PHSYNC;
363 else
364 flags |= DRM_MODE_FLAG_NHSYNC;
365
366 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
367 flags |= DRM_MODE_FLAG_PVSYNC;
368 else
369 flags |= DRM_MODE_FLAG_NVSYNC;
370 } else {
371 if (tmp & DP_ENHANCED_FRAMING)
372 pipe_config->enhanced_framing = true;
373
374 if (tmp & DP_SYNC_HS_HIGH)
375 flags |= DRM_MODE_FLAG_PHSYNC;
376 else
377 flags |= DRM_MODE_FLAG_NHSYNC;
378
379 if (tmp & DP_SYNC_VS_HIGH)
380 flags |= DRM_MODE_FLAG_PVSYNC;
381 else
382 flags |= DRM_MODE_FLAG_NVSYNC;
383 }
384
385 pipe_config->hw.adjusted_mode.flags |= flags;
386
387 if (display->platform.g4x && tmp & DP_COLOR_RANGE_16_235)
388 pipe_config->limited_color_range = true;
389
390 pipe_config->lane_count = REG_FIELD_GET(DP_PORT_WIDTH_MASK, tmp) + 1;
391
392 g4x_dp_get_m_n(crtc_state: pipe_config);
393
394 if (port == PORT_A) {
395 if ((intel_de_read(display, DP_A) & EDP_PLL_FREQ_MASK) == EDP_PLL_FREQ_162MHZ)
396 pipe_config->port_clock = 162000;
397 else
398 pipe_config->port_clock = 270000;
399 }
400
401 pipe_config->hw.adjusted_mode.crtc_clock =
402 intel_dotclock_calculate(link_freq: pipe_config->port_clock,
403 m_n: &pipe_config->dp_m_n);
404
405 if (intel_dp_is_edp(intel_dp))
406 intel_edp_fixup_vbt_bpp(encoder, pipe_bpp: pipe_config->pipe_bpp);
407
408 intel_audio_codec_get_config(encoder, crtc_state: pipe_config);
409}
410
411static void
412intel_dp_link_down(struct intel_encoder *encoder,
413 const struct intel_crtc_state *old_crtc_state)
414{
415 struct intel_display *display = to_intel_display(encoder);
416 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
417 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
418 enum port port = encoder->port;
419
420 if (drm_WARN_ON(display->drm,
421 (intel_de_read(display, intel_dp->output_reg) &
422 DP_PORT_EN) == 0))
423 return;
424
425 drm_dbg_kms(display->drm, "\n");
426
427 intel_dp->DP &= ~DP_PORT_EN;
428 intel_de_write(display, reg: intel_dp->output_reg, val: intel_dp->DP);
429 intel_de_posting_read(display, reg: intel_dp->output_reg);
430
431 /*
432 * HW workaround for IBX, we need to move the port
433 * to transcoder A after disabling it to allow the
434 * matching HDMI port to be enabled on transcoder A.
435 */
436 if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B && port != PORT_A) {
437 /*
438 * We get CPU/PCH FIFO underruns on the other pipe when
439 * doing the workaround. Sweep them under the rug.
440 */
441 intel_set_cpu_fifo_underrun_reporting(display, pipe: PIPE_A, enable: false);
442 intel_set_pch_fifo_underrun_reporting(display, pch_transcoder: PIPE_A, enable: false);
443
444 /* always enable with pattern 1 (as per spec) */
445 intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
446 intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
447 DP_LINK_TRAIN_PAT_1;
448 intel_de_write(display, reg: intel_dp->output_reg, val: intel_dp->DP);
449 intel_de_posting_read(display, reg: intel_dp->output_reg);
450
451 intel_dp->DP &= ~DP_PORT_EN;
452 intel_de_write(display, reg: intel_dp->output_reg, val: intel_dp->DP);
453 intel_de_posting_read(display, reg: intel_dp->output_reg);
454
455 intel_wait_for_vblank_if_active(display, pipe: PIPE_A);
456 intel_set_cpu_fifo_underrun_reporting(display, pipe: PIPE_A, enable: true);
457 intel_set_pch_fifo_underrun_reporting(display, pch_transcoder: PIPE_A, enable: true);
458 }
459
460 msleep(msecs: intel_dp->pps.panel_power_down_delay);
461
462 if (display->platform.valleyview || display->platform.cherryview)
463 vlv_pps_port_disable(encoder, crtc_state: old_crtc_state);
464}
465
466static void g4x_dp_audio_enable(struct intel_encoder *encoder,
467 const struct intel_crtc_state *crtc_state,
468 const struct drm_connector_state *conn_state)
469{
470 struct intel_display *display = to_intel_display(encoder);
471 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
472
473 if (!crtc_state->has_audio)
474 return;
475
476 /* Enable audio presence detect */
477 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
478 intel_de_write(display, reg: intel_dp->output_reg, val: intel_dp->DP);
479
480 intel_audio_codec_enable(encoder, crtc_state, conn_state);
481}
482
483static void g4x_dp_audio_disable(struct intel_encoder *encoder,
484 const struct intel_crtc_state *old_crtc_state,
485 const struct drm_connector_state *old_conn_state)
486{
487 struct intel_display *display = to_intel_display(encoder);
488 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
489
490 if (!old_crtc_state->has_audio)
491 return;
492
493 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
494
495 /* Disable audio presence detect */
496 intel_dp->DP &= ~DP_AUDIO_OUTPUT_ENABLE;
497 intel_de_write(display, reg: intel_dp->output_reg, val: intel_dp->DP);
498}
499
500static void intel_disable_dp(struct intel_atomic_state *state,
501 struct intel_encoder *encoder,
502 const struct intel_crtc_state *old_crtc_state,
503 const struct drm_connector_state *old_conn_state)
504{
505 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
506
507 intel_dp->link.active = false;
508
509 /*
510 * Make sure the panel is off before trying to change the mode.
511 * But also ensure that we have vdd while we switch off the panel.
512 */
513 intel_pps_vdd_on(intel_dp);
514 intel_edp_backlight_off(conn_state: old_conn_state);
515 intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
516 intel_pps_off(intel_dp);
517}
518
519static void g4x_disable_dp(struct intel_atomic_state *state,
520 struct intel_encoder *encoder,
521 const struct intel_crtc_state *old_crtc_state,
522 const struct drm_connector_state *old_conn_state)
523{
524 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
525}
526
527static void vlv_disable_dp(struct intel_atomic_state *state,
528 struct intel_encoder *encoder,
529 const struct intel_crtc_state *old_crtc_state,
530 const struct drm_connector_state *old_conn_state)
531{
532 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
533}
534
535static void g4x_post_disable_dp(struct intel_atomic_state *state,
536 struct intel_encoder *encoder,
537 const struct intel_crtc_state *old_crtc_state,
538 const struct drm_connector_state *old_conn_state)
539{
540 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
541 enum port port = encoder->port;
542
543 /*
544 * Bspec does not list a specific disable sequence for g4x DP.
545 * Follow the ilk+ sequence (disable pipe before the port) for
546 * g4x DP as it does not suffer from underruns like the normal
547 * g4x modeset sequence (disable pipe after the port).
548 */
549 intel_dp_link_down(encoder, old_crtc_state);
550
551 /* Only ilk+ has port A */
552 if (port == PORT_A)
553 ilk_edp_pll_off(intel_dp, old_crtc_state);
554}
555
556static void vlv_post_disable_dp(struct intel_atomic_state *state,
557 struct intel_encoder *encoder,
558 const struct intel_crtc_state *old_crtc_state,
559 const struct drm_connector_state *old_conn_state)
560{
561 intel_dp_link_down(encoder, old_crtc_state);
562}
563
564static void chv_post_disable_dp(struct intel_atomic_state *state,
565 struct intel_encoder *encoder,
566 const struct intel_crtc_state *old_crtc_state,
567 const struct drm_connector_state *old_conn_state)
568{
569 intel_dp_link_down(encoder, old_crtc_state);
570
571 /* Assert data lane reset */
572 chv_data_lane_soft_reset(encoder, crtc_state: old_crtc_state, reset: true);
573}
574
575static void
576cpt_set_link_train(struct intel_dp *intel_dp,
577 const struct intel_crtc_state *crtc_state,
578 u8 dp_train_pat)
579{
580 struct intel_display *display = to_intel_display(intel_dp);
581
582 intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
583
584 switch (intel_dp_training_pattern_symbol(pattern: dp_train_pat)) {
585 case DP_TRAINING_PATTERN_DISABLE:
586 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
587 break;
588 case DP_TRAINING_PATTERN_1:
589 intel_dp->DP |= DP_LINK_TRAIN_PAT_1_CPT;
590 break;
591 case DP_TRAINING_PATTERN_2:
592 intel_dp->DP |= DP_LINK_TRAIN_PAT_2_CPT;
593 break;
594 default:
595 MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
596 return;
597 }
598
599 intel_de_write(display, reg: intel_dp->output_reg, val: intel_dp->DP);
600 intel_de_posting_read(display, reg: intel_dp->output_reg);
601}
602
603static void
604cpt_set_idle_link_train(struct intel_dp *intel_dp,
605 const struct intel_crtc_state *crtc_state)
606{
607 struct intel_display *display = to_intel_display(intel_dp);
608
609 intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
610 intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
611
612 intel_de_write(display, reg: intel_dp->output_reg, val: intel_dp->DP);
613 intel_de_posting_read(display, reg: intel_dp->output_reg);
614}
615
616static void
617g4x_set_link_train(struct intel_dp *intel_dp,
618 const struct intel_crtc_state *crtc_state,
619 u8 dp_train_pat)
620{
621 struct intel_display *display = to_intel_display(intel_dp);
622
623 intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
624
625 switch (intel_dp_training_pattern_symbol(pattern: dp_train_pat)) {
626 case DP_TRAINING_PATTERN_DISABLE:
627 intel_dp->DP |= DP_LINK_TRAIN_OFF;
628 break;
629 case DP_TRAINING_PATTERN_1:
630 intel_dp->DP |= DP_LINK_TRAIN_PAT_1;
631 break;
632 case DP_TRAINING_PATTERN_2:
633 intel_dp->DP |= DP_LINK_TRAIN_PAT_2;
634 break;
635 default:
636 MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
637 return;
638 }
639
640 intel_de_write(display, reg: intel_dp->output_reg, val: intel_dp->DP);
641 intel_de_posting_read(display, reg: intel_dp->output_reg);
642}
643
644static void
645g4x_set_idle_link_train(struct intel_dp *intel_dp,
646 const struct intel_crtc_state *crtc_state)
647{
648 struct intel_display *display = to_intel_display(intel_dp);
649
650 intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
651 intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
652
653 intel_de_write(display, reg: intel_dp->output_reg, val: intel_dp->DP);
654 intel_de_posting_read(display, reg: intel_dp->output_reg);
655}
656
657static void intel_dp_enable_port(struct intel_dp *intel_dp,
658 const struct intel_crtc_state *crtc_state)
659{
660 struct intel_display *display = to_intel_display(intel_dp);
661
662 /* enable with pattern 1 (as per spec) */
663
664 intel_dp_program_link_training_pattern(intel_dp, crtc_state,
665 dp_phy: DP_PHY_DPRX, DP_TRAINING_PATTERN_1);
666
667 /*
668 * Magic for VLV/CHV. We _must_ first set up the register
669 * without actually enabling the port, and then do another
670 * write to enable the port. Otherwise link training will
671 * fail when the power sequencer is freshly used for this port.
672 */
673 intel_dp->DP |= DP_PORT_EN;
674
675 intel_de_write(display, reg: intel_dp->output_reg, val: intel_dp->DP);
676 intel_de_posting_read(display, reg: intel_dp->output_reg);
677}
678
679static void intel_enable_dp(struct intel_atomic_state *state,
680 struct intel_encoder *encoder,
681 const struct intel_crtc_state *pipe_config,
682 const struct drm_connector_state *conn_state)
683{
684 struct intel_display *display = to_intel_display(state);
685 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
686 u32 dp_reg = intel_de_read(display, reg: intel_dp->output_reg);
687 intel_wakeref_t wakeref;
688
689 if (drm_WARN_ON(display->drm, dp_reg & DP_PORT_EN))
690 return;
691
692 with_intel_pps_lock(intel_dp, wakeref) {
693 if (display->platform.valleyview || display->platform.cherryview)
694 vlv_pps_port_enable_unlocked(encoder, crtc_state: pipe_config);
695
696 intel_dp_enable_port(intel_dp, crtc_state: pipe_config);
697
698 intel_pps_vdd_on_unlocked(intel_dp);
699 intel_pps_on_unlocked(intel_dp);
700 intel_pps_vdd_off_unlocked(intel_dp, sync: true);
701 }
702
703 if (display->platform.valleyview || display->platform.cherryview) {
704 unsigned int lane_mask = 0x0;
705
706 if (display->platform.cherryview)
707 lane_mask = intel_dp_unused_lane_mask(lane_count: pipe_config->lane_count);
708
709 vlv_wait_port_ready(encoder, expected_mask: lane_mask);
710 }
711
712 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
713 intel_dp_configure_protocol_converter(intel_dp, crtc_state: pipe_config);
714 intel_dp_check_frl_training(intel_dp);
715 intel_dp_pcon_dsc_configure(intel_dp, crtc_state: pipe_config);
716 intel_dp_start_link_train(state, intel_dp, crtc_state: pipe_config);
717 intel_dp_stop_link_train(intel_dp, crtc_state: pipe_config);
718}
719
720static void g4x_enable_dp(struct intel_atomic_state *state,
721 struct intel_encoder *encoder,
722 const struct intel_crtc_state *pipe_config,
723 const struct drm_connector_state *conn_state)
724{
725 intel_enable_dp(state, encoder, pipe_config, conn_state);
726 intel_edp_backlight_on(crtc_state: pipe_config, conn_state);
727}
728
729static void vlv_enable_dp(struct intel_atomic_state *state,
730 struct intel_encoder *encoder,
731 const struct intel_crtc_state *pipe_config,
732 const struct drm_connector_state *conn_state)
733{
734 intel_edp_backlight_on(crtc_state: pipe_config, conn_state);
735}
736
737static void g4x_pre_enable_dp(struct intel_atomic_state *state,
738 struct intel_encoder *encoder,
739 const struct intel_crtc_state *pipe_config,
740 const struct drm_connector_state *conn_state)
741{
742 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
743 enum port port = encoder->port;
744
745 intel_dp_prepare(encoder, pipe_config);
746
747 /* Only ilk+ has port A */
748 if (port == PORT_A)
749 ilk_edp_pll_on(intel_dp, pipe_config);
750}
751
752static void vlv_pre_enable_dp(struct intel_atomic_state *state,
753 struct intel_encoder *encoder,
754 const struct intel_crtc_state *pipe_config,
755 const struct drm_connector_state *conn_state)
756{
757 vlv_phy_pre_encoder_enable(encoder, crtc_state: pipe_config);
758
759 intel_enable_dp(state, encoder, pipe_config, conn_state);
760}
761
762static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
763 struct intel_encoder *encoder,
764 const struct intel_crtc_state *pipe_config,
765 const struct drm_connector_state *conn_state)
766{
767 intel_dp_prepare(encoder, pipe_config);
768
769 vlv_phy_pre_pll_enable(encoder, crtc_state: pipe_config);
770}
771
772static void chv_pre_enable_dp(struct intel_atomic_state *state,
773 struct intel_encoder *encoder,
774 const struct intel_crtc_state *pipe_config,
775 const struct drm_connector_state *conn_state)
776{
777 chv_phy_pre_encoder_enable(encoder, crtc_state: pipe_config);
778
779 intel_enable_dp(state, encoder, pipe_config, conn_state);
780
781 /* Second common lane will stay alive on its own now */
782 chv_phy_release_cl2_override(encoder);
783}
784
785static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
786 struct intel_encoder *encoder,
787 const struct intel_crtc_state *pipe_config,
788 const struct drm_connector_state *conn_state)
789{
790 intel_dp_prepare(encoder, pipe_config);
791
792 chv_phy_pre_pll_enable(encoder, crtc_state: pipe_config);
793}
794
795static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
796 struct intel_encoder *encoder,
797 const struct intel_crtc_state *old_crtc_state,
798 const struct drm_connector_state *old_conn_state)
799{
800 chv_phy_post_pll_disable(encoder, old_crtc_state);
801}
802
803static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,
804 const struct intel_crtc_state *crtc_state)
805{
806 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
807}
808
809static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,
810 const struct intel_crtc_state *crtc_state)
811{
812 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
813}
814
815static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)
816{
817 return DP_TRAIN_PRE_EMPH_LEVEL_2;
818}
819
820static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
821{
822 return DP_TRAIN_PRE_EMPH_LEVEL_3;
823}
824
825static void vlv_set_signal_levels(struct intel_encoder *encoder,
826 const struct intel_crtc_state *crtc_state)
827{
828 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
829 unsigned long demph_reg_value, preemph_reg_value,
830 uniqtranscale_reg_value;
831 u8 train_set = intel_dp->train_set[0];
832
833 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
834 case DP_TRAIN_PRE_EMPH_LEVEL_0:
835 preemph_reg_value = 0x0004000;
836 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
837 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
838 demph_reg_value = 0x2B405555;
839 uniqtranscale_reg_value = 0x552AB83A;
840 break;
841 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
842 demph_reg_value = 0x2B404040;
843 uniqtranscale_reg_value = 0x5548B83A;
844 break;
845 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
846 demph_reg_value = 0x2B245555;
847 uniqtranscale_reg_value = 0x5560B83A;
848 break;
849 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
850 demph_reg_value = 0x2B405555;
851 uniqtranscale_reg_value = 0x5598DA3A;
852 break;
853 default:
854 return;
855 }
856 break;
857 case DP_TRAIN_PRE_EMPH_LEVEL_1:
858 preemph_reg_value = 0x0002000;
859 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
860 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
861 demph_reg_value = 0x2B404040;
862 uniqtranscale_reg_value = 0x5552B83A;
863 break;
864 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
865 demph_reg_value = 0x2B404848;
866 uniqtranscale_reg_value = 0x5580B83A;
867 break;
868 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
869 demph_reg_value = 0x2B404040;
870 uniqtranscale_reg_value = 0x55ADDA3A;
871 break;
872 default:
873 return;
874 }
875 break;
876 case DP_TRAIN_PRE_EMPH_LEVEL_2:
877 preemph_reg_value = 0x0000000;
878 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
879 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
880 demph_reg_value = 0x2B305555;
881 uniqtranscale_reg_value = 0x5570B83A;
882 break;
883 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
884 demph_reg_value = 0x2B2B4040;
885 uniqtranscale_reg_value = 0x55ADDA3A;
886 break;
887 default:
888 return;
889 }
890 break;
891 case DP_TRAIN_PRE_EMPH_LEVEL_3:
892 preemph_reg_value = 0x0006000;
893 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
894 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
895 demph_reg_value = 0x1B405555;
896 uniqtranscale_reg_value = 0x55ADDA3A;
897 break;
898 default:
899 return;
900 }
901 break;
902 default:
903 return;
904 }
905
906 vlv_set_phy_signal_level(encoder, crtc_state,
907 demph_reg_value, preemph_reg_value,
908 uniqtranscale_reg_value, tx3_demph: 0);
909}
910
911static void chv_set_signal_levels(struct intel_encoder *encoder,
912 const struct intel_crtc_state *crtc_state)
913{
914 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
915 u32 deemph_reg_value, margin_reg_value;
916 bool uniq_trans_scale = false;
917 u8 train_set = intel_dp->train_set[0];
918
919 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
920 case DP_TRAIN_PRE_EMPH_LEVEL_0:
921 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
922 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
923 deemph_reg_value = 128;
924 margin_reg_value = 52;
925 break;
926 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
927 deemph_reg_value = 128;
928 margin_reg_value = 77;
929 break;
930 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
931 deemph_reg_value = 128;
932 margin_reg_value = 102;
933 break;
934 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
935 deemph_reg_value = 128;
936 margin_reg_value = 154;
937 uniq_trans_scale = true;
938 break;
939 default:
940 return;
941 }
942 break;
943 case DP_TRAIN_PRE_EMPH_LEVEL_1:
944 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
945 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
946 deemph_reg_value = 85;
947 margin_reg_value = 78;
948 break;
949 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
950 deemph_reg_value = 85;
951 margin_reg_value = 116;
952 break;
953 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
954 deemph_reg_value = 85;
955 margin_reg_value = 154;
956 break;
957 default:
958 return;
959 }
960 break;
961 case DP_TRAIN_PRE_EMPH_LEVEL_2:
962 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
963 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
964 deemph_reg_value = 64;
965 margin_reg_value = 104;
966 break;
967 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
968 deemph_reg_value = 64;
969 margin_reg_value = 154;
970 break;
971 default:
972 return;
973 }
974 break;
975 case DP_TRAIN_PRE_EMPH_LEVEL_3:
976 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
977 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
978 deemph_reg_value = 43;
979 margin_reg_value = 154;
980 break;
981 default:
982 return;
983 }
984 break;
985 default:
986 return;
987 }
988
989 chv_set_phy_signal_level(encoder, crtc_state,
990 deemph_reg_value, margin_reg_value,
991 uniq_trans_scale);
992}
993
994static u32 g4x_signal_levels(u8 train_set)
995{
996 u32 signal_levels = 0;
997
998 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
999 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
1000 default:
1001 signal_levels |= DP_VOLTAGE_0_4;
1002 break;
1003 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
1004 signal_levels |= DP_VOLTAGE_0_6;
1005 break;
1006 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
1007 signal_levels |= DP_VOLTAGE_0_8;
1008 break;
1009 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1010 signal_levels |= DP_VOLTAGE_1_2;
1011 break;
1012 }
1013 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1014 case DP_TRAIN_PRE_EMPH_LEVEL_0:
1015 default:
1016 signal_levels |= DP_PRE_EMPHASIS_0;
1017 break;
1018 case DP_TRAIN_PRE_EMPH_LEVEL_1:
1019 signal_levels |= DP_PRE_EMPHASIS_3_5;
1020 break;
1021 case DP_TRAIN_PRE_EMPH_LEVEL_2:
1022 signal_levels |= DP_PRE_EMPHASIS_6;
1023 break;
1024 case DP_TRAIN_PRE_EMPH_LEVEL_3:
1025 signal_levels |= DP_PRE_EMPHASIS_9_5;
1026 break;
1027 }
1028 return signal_levels;
1029}
1030
1031static void
1032g4x_set_signal_levels(struct intel_encoder *encoder,
1033 const struct intel_crtc_state *crtc_state)
1034{
1035 struct intel_display *display = to_intel_display(encoder);
1036 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1037 u8 train_set = intel_dp->train_set[0];
1038 u32 signal_levels;
1039
1040 signal_levels = g4x_signal_levels(train_set);
1041
1042 drm_dbg_kms(display->drm, "Using signal levels %08x\n",
1043 signal_levels);
1044
1045 intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
1046 intel_dp->DP |= signal_levels;
1047
1048 intel_de_write(display, reg: intel_dp->output_reg, val: intel_dp->DP);
1049 intel_de_posting_read(display, reg: intel_dp->output_reg);
1050}
1051
1052/* SNB CPU eDP voltage swing and pre-emphasis control */
1053static u32 snb_cpu_edp_signal_levels(u8 train_set)
1054{
1055 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1056 DP_TRAIN_PRE_EMPHASIS_MASK);
1057
1058 switch (signal_levels) {
1059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1060 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1061 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1062 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1063 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1064 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1065 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1066 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1067 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1068 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1069 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1070 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1071 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1072 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1073 default:
1074 MISSING_CASE(signal_levels);
1075 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1076 }
1077}
1078
1079static void
1080snb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,
1081 const struct intel_crtc_state *crtc_state)
1082{
1083 struct intel_display *display = to_intel_display(encoder);
1084 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1085 u8 train_set = intel_dp->train_set[0];
1086 u32 signal_levels;
1087
1088 signal_levels = snb_cpu_edp_signal_levels(train_set);
1089
1090 drm_dbg_kms(display->drm, "Using signal levels %08x\n",
1091 signal_levels);
1092
1093 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1094 intel_dp->DP |= signal_levels;
1095
1096 intel_de_write(display, reg: intel_dp->output_reg, val: intel_dp->DP);
1097 intel_de_posting_read(display, reg: intel_dp->output_reg);
1098}
1099
1100/* IVB CPU eDP voltage swing and pre-emphasis control */
1101static u32 ivb_cpu_edp_signal_levels(u8 train_set)
1102{
1103 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1104 DP_TRAIN_PRE_EMPHASIS_MASK);
1105
1106 switch (signal_levels) {
1107 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1108 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1109 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1110 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1111 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1112 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1113 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1114
1115 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1116 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1117 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1118 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1119
1120 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1121 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1122 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1123 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1124
1125 default:
1126 MISSING_CASE(signal_levels);
1127 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1128 }
1129}
1130
1131static void
1132ivb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,
1133 const struct intel_crtc_state *crtc_state)
1134{
1135 struct intel_display *display = to_intel_display(encoder);
1136 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1137 u8 train_set = intel_dp->train_set[0];
1138 u32 signal_levels;
1139
1140 signal_levels = ivb_cpu_edp_signal_levels(train_set);
1141
1142 drm_dbg_kms(display->drm, "Using signal levels %08x\n",
1143 signal_levels);
1144
1145 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1146 intel_dp->DP |= signal_levels;
1147
1148 intel_de_write(display, reg: intel_dp->output_reg, val: intel_dp->DP);
1149 intel_de_posting_read(display, reg: intel_dp->output_reg);
1150}
1151
1152/*
1153 * If display is now connected check links status,
1154 * there has been known issues of link loss triggering
1155 * long pulse.
1156 *
1157 * Some sinks (eg. ASUS PB287Q) seem to perform some
1158 * weird HPD ping pong during modesets. So we can apparently
1159 * end up with HPD going low during a modeset, and then
1160 * going back up soon after. And once that happens we must
1161 * retrain the link to get a picture. That's in case no
1162 * userspace component reacted to intermittent HPD dip.
1163 */
1164static enum intel_hotplug_state
1165intel_dp_hotplug(struct intel_encoder *encoder,
1166 struct intel_connector *connector)
1167{
1168 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1169 enum intel_hotplug_state state;
1170
1171 if (intel_dp_test_phy(intel_dp))
1172 return INTEL_HOTPLUG_UNCHANGED;
1173
1174 state = intel_encoder_hotplug(encoder, connector);
1175
1176 intel_dp_check_link_state(intel_dp);
1177
1178 /*
1179 * Keeping it consistent with intel_ddi_hotplug() and
1180 * intel_hdmi_hotplug().
1181 */
1182 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
1183 state = INTEL_HOTPLUG_RETRY;
1184
1185 return state;
1186}
1187
1188static bool ibx_digital_port_connected(struct intel_encoder *encoder)
1189{
1190 struct intel_display *display = to_intel_display(encoder);
1191 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];
1192
1193 return intel_de_read(display, SDEISR) & bit;
1194}
1195
1196static bool g4x_digital_port_connected(struct intel_encoder *encoder)
1197{
1198 struct intel_display *display = to_intel_display(encoder);
1199 u32 bit;
1200
1201 switch (encoder->hpd_pin) {
1202 case HPD_PORT_B:
1203 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
1204 break;
1205 case HPD_PORT_C:
1206 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
1207 break;
1208 case HPD_PORT_D:
1209 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
1210 break;
1211 default:
1212 MISSING_CASE(encoder->hpd_pin);
1213 return false;
1214 }
1215
1216 return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit;
1217}
1218
1219static bool ilk_digital_port_connected(struct intel_encoder *encoder)
1220{
1221 struct intel_display *display = to_intel_display(encoder);
1222 u32 bit = display->hotplug.hpd[encoder->hpd_pin];
1223
1224 return intel_de_read(display, DEISR) & bit;
1225}
1226
1227static int g4x_dp_compute_config(struct intel_encoder *encoder,
1228 struct intel_crtc_state *crtc_state,
1229 struct drm_connector_state *conn_state)
1230{
1231 struct intel_display *display = to_intel_display(encoder);
1232 int ret;
1233
1234 if (HAS_PCH_SPLIT(display) && encoder->port != PORT_A)
1235 crtc_state->has_pch_encoder = true;
1236
1237 ret = intel_dp_compute_config(encoder, pipe_config: crtc_state, conn_state);
1238 if (ret)
1239 return ret;
1240
1241 g4x_dp_set_clock(encoder, pipe_config: crtc_state);
1242
1243 return 0;
1244}
1245
1246static void g4x_dp_suspend_complete(struct intel_encoder *encoder)
1247{
1248 /*
1249 * TODO: Move this to intel_dp_encoder_suspend(),
1250 * once modeset locking around that is removed.
1251 */
1252 intel_encoder_link_check_flush_work(encoder);
1253}
1254
1255static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1256{
1257 intel_dp_encoder_flush_work(encoder);
1258
1259 drm_encoder_cleanup(encoder);
1260 kfree(objp: enc_to_dig_port(to_intel_encoder(encoder)));
1261}
1262
1263static void intel_dp_encoder_reset(struct drm_encoder *encoder)
1264{
1265 struct intel_display *display = to_intel_display(encoder->dev);
1266 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
1267
1268 intel_dp->DP = intel_de_read(display, reg: intel_dp->output_reg);
1269
1270 intel_dp->reset_link_params = true;
1271 intel_dp_invalidate_source_oui(intel_dp);
1272
1273 if (display->platform.valleyview || display->platform.cherryview)
1274 vlv_pps_pipe_reset(intel_dp);
1275
1276 intel_pps_encoder_reset(intel_dp);
1277}
1278
1279static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1280 .reset = intel_dp_encoder_reset,
1281 .destroy = intel_dp_encoder_destroy,
1282};
1283
1284bool g4x_dp_init(struct intel_display *display,
1285 i915_reg_t output_reg, enum port port)
1286{
1287 const struct intel_bios_encoder_data *devdata;
1288 struct intel_digital_port *dig_port;
1289 struct intel_encoder *intel_encoder;
1290 struct drm_encoder *encoder;
1291 struct intel_connector *intel_connector;
1292
1293 if (!assert_port_valid(display, port))
1294 return false;
1295
1296 devdata = intel_bios_encoder_data_lookup(display, port);
1297
1298 /* FIXME bail? */
1299 if (!devdata)
1300 drm_dbg_kms(display->drm, "No VBT child device for DP-%c\n",
1301 port_name(port));
1302
1303 dig_port = intel_dig_port_alloc();
1304 if (!dig_port)
1305 return false;
1306
1307 intel_connector = intel_connector_alloc();
1308 if (!intel_connector)
1309 goto err_connector_alloc;
1310
1311 intel_encoder = &dig_port->base;
1312 encoder = &intel_encoder->base;
1313
1314 intel_encoder->devdata = devdata;
1315
1316 if (drm_encoder_init(dev: display->drm, encoder: &intel_encoder->base,
1317 funcs: &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
1318 name: "DP %c", port_name(port)))
1319 goto err_encoder_init;
1320
1321 intel_encoder_link_check_init(encoder: intel_encoder, callback: intel_dp_link_check);
1322
1323 intel_encoder->hotplug = intel_dp_hotplug;
1324 intel_encoder->compute_config = g4x_dp_compute_config;
1325 intel_encoder->get_hw_state = intel_dp_get_hw_state;
1326 intel_encoder->get_config = intel_dp_get_config;
1327 intel_encoder->sync_state = intel_dp_sync_state;
1328 intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
1329 intel_encoder->update_pipe = intel_backlight_update;
1330 intel_encoder->suspend = intel_dp_encoder_suspend;
1331 intel_encoder->suspend_complete = g4x_dp_suspend_complete;
1332 intel_encoder->shutdown = intel_dp_encoder_shutdown;
1333 if (display->platform.cherryview) {
1334 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
1335 intel_encoder->pre_enable = chv_pre_enable_dp;
1336 intel_encoder->enable = vlv_enable_dp;
1337 intel_encoder->disable = vlv_disable_dp;
1338 intel_encoder->post_disable = chv_post_disable_dp;
1339 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
1340 } else if (display->platform.valleyview) {
1341 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
1342 intel_encoder->pre_enable = vlv_pre_enable_dp;
1343 intel_encoder->enable = vlv_enable_dp;
1344 intel_encoder->disable = vlv_disable_dp;
1345 intel_encoder->post_disable = vlv_post_disable_dp;
1346 } else {
1347 intel_encoder->pre_enable = g4x_pre_enable_dp;
1348 intel_encoder->enable = g4x_enable_dp;
1349 intel_encoder->disable = g4x_disable_dp;
1350 intel_encoder->post_disable = g4x_post_disable_dp;
1351 }
1352 intel_encoder->audio_enable = g4x_dp_audio_enable;
1353 intel_encoder->audio_disable = g4x_dp_audio_disable;
1354
1355 if ((display->platform.ivybridge && port == PORT_A) ||
1356 (HAS_PCH_CPT(display) && port != PORT_A)) {
1357 dig_port->dp.set_link_train = cpt_set_link_train;
1358 dig_port->dp.set_idle_link_train = cpt_set_idle_link_train;
1359 } else {
1360 dig_port->dp.set_link_train = g4x_set_link_train;
1361 dig_port->dp.set_idle_link_train = g4x_set_idle_link_train;
1362 }
1363
1364 if (display->platform.cherryview)
1365 intel_encoder->set_signal_levels = chv_set_signal_levels;
1366 else if (display->platform.valleyview)
1367 intel_encoder->set_signal_levels = vlv_set_signal_levels;
1368 else if (display->platform.ivybridge && port == PORT_A)
1369 intel_encoder->set_signal_levels = ivb_cpu_edp_set_signal_levels;
1370 else if (display->platform.sandybridge && port == PORT_A)
1371 intel_encoder->set_signal_levels = snb_cpu_edp_set_signal_levels;
1372 else
1373 intel_encoder->set_signal_levels = g4x_set_signal_levels;
1374
1375 if (display->platform.valleyview || display->platform.cherryview ||
1376 (HAS_PCH_SPLIT(display) && port != PORT_A)) {
1377 dig_port->dp.preemph_max = intel_dp_preemph_max_3;
1378 dig_port->dp.voltage_max = intel_dp_voltage_max_3;
1379 } else {
1380 dig_port->dp.preemph_max = intel_dp_preemph_max_2;
1381 dig_port->dp.voltage_max = intel_dp_voltage_max_2;
1382 }
1383
1384 dig_port->dp.output_reg = output_reg;
1385
1386 intel_encoder->type = INTEL_OUTPUT_DP;
1387 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);
1388 if (display->platform.cherryview) {
1389 if (port == PORT_D)
1390 intel_encoder->pipe_mask = BIT(PIPE_C);
1391 else
1392 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
1393 } else {
1394 intel_encoder->pipe_mask = ~0;
1395 }
1396 intel_encoder->cloneable = 0;
1397 intel_encoder->port = port;
1398 intel_encoder->hpd_pin = intel_hpd_pin_default(port);
1399
1400 dig_port->hpd_pulse = intel_dp_hpd_pulse;
1401
1402 if (HAS_GMCH(display)) {
1403 dig_port->connected = g4x_digital_port_connected;
1404 } else {
1405 if (port == PORT_A)
1406 dig_port->connected = ilk_digital_port_connected;
1407 else
1408 dig_port->connected = ibx_digital_port_connected;
1409 }
1410
1411 if (port != PORT_A)
1412 intel_infoframe_init(dig_port);
1413
1414 dig_port->aux_ch = intel_dp_aux_ch(encoder: intel_encoder);
1415 if (dig_port->aux_ch == AUX_CH_NONE)
1416 goto err_init_connector;
1417
1418 if (!intel_dp_init_connector(dig_port, intel_connector))
1419 goto err_init_connector;
1420
1421 return true;
1422
1423err_init_connector:
1424 drm_encoder_cleanup(encoder);
1425err_encoder_init:
1426 kfree(objp: intel_connector);
1427err_connector_alloc:
1428 kfree(objp: dig_port);
1429 return false;
1430}
1431