1/*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#include <linux/string_helpers.h>
26
27#include <drm/drm_print.h>
28#include <drm/intel/pciids.h>
29
30#include "gt/intel_gt_regs.h"
31#include "i915_drv.h"
32#include "i915_reg.h"
33#include "i915_utils.h"
34#include "intel_device_info.h"
35
36#define PLATFORM_NAME(x) [INTEL_##x] = #x
37static const char * const platform_names[] = {
38 PLATFORM_NAME(I830),
39 PLATFORM_NAME(I845G),
40 PLATFORM_NAME(I85X),
41 PLATFORM_NAME(I865G),
42 PLATFORM_NAME(I915G),
43 PLATFORM_NAME(I915GM),
44 PLATFORM_NAME(I945G),
45 PLATFORM_NAME(I945GM),
46 PLATFORM_NAME(G33),
47 PLATFORM_NAME(PINEVIEW),
48 PLATFORM_NAME(I965G),
49 PLATFORM_NAME(I965GM),
50 PLATFORM_NAME(G45),
51 PLATFORM_NAME(GM45),
52 PLATFORM_NAME(IRONLAKE),
53 PLATFORM_NAME(SANDYBRIDGE),
54 PLATFORM_NAME(IVYBRIDGE),
55 PLATFORM_NAME(VALLEYVIEW),
56 PLATFORM_NAME(HASWELL),
57 PLATFORM_NAME(BROADWELL),
58 PLATFORM_NAME(CHERRYVIEW),
59 PLATFORM_NAME(SKYLAKE),
60 PLATFORM_NAME(BROXTON),
61 PLATFORM_NAME(KABYLAKE),
62 PLATFORM_NAME(GEMINILAKE),
63 PLATFORM_NAME(COFFEELAKE),
64 PLATFORM_NAME(COMETLAKE),
65 PLATFORM_NAME(ICELAKE),
66 PLATFORM_NAME(ELKHARTLAKE),
67 PLATFORM_NAME(JASPERLAKE),
68 PLATFORM_NAME(TIGERLAKE),
69 PLATFORM_NAME(ROCKETLAKE),
70 PLATFORM_NAME(DG1),
71 PLATFORM_NAME(ALDERLAKE_S),
72 PLATFORM_NAME(ALDERLAKE_P),
73 PLATFORM_NAME(DG2),
74 PLATFORM_NAME(METEORLAKE),
75};
76#undef PLATFORM_NAME
77
78const char *intel_platform_name(enum intel_platform platform)
79{
80 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
81
82 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
83 platform_names[platform] == NULL))
84 return "<unknown>";
85
86 return platform_names[platform];
87}
88
89void intel_device_info_print(const struct intel_device_info *info,
90 const struct intel_runtime_info *runtime,
91 struct drm_printer *p)
92{
93 if (runtime->graphics.ip.rel)
94 drm_printf(p, f: "graphics version: %u.%02u\n",
95 runtime->graphics.ip.ver,
96 runtime->graphics.ip.rel);
97 else
98 drm_printf(p, f: "graphics version: %u\n",
99 runtime->graphics.ip.ver);
100
101 if (runtime->media.ip.rel)
102 drm_printf(p, f: "media version: %u.%02u\n",
103 runtime->media.ip.ver,
104 runtime->media.ip.rel);
105 else
106 drm_printf(p, f: "media version: %u\n",
107 runtime->media.ip.ver);
108
109 drm_printf(p, f: "graphics stepping: %s\n", intel_step_name(step: runtime->step.graphics_step));
110 drm_printf(p, f: "media stepping: %s\n", intel_step_name(step: runtime->step.media_step));
111
112 drm_printf(p, f: "gt: %d\n", info->gt);
113 drm_printf(p, f: "memory-regions: 0x%x\n", info->memory_regions);
114 drm_printf(p, f: "page-sizes: 0x%x\n", runtime->page_sizes);
115 drm_printf(p, f: "platform: %s\n", intel_platform_name(platform: info->platform));
116 drm_printf(p, f: "ppgtt-size: %d\n", runtime->ppgtt_size);
117 drm_printf(p, f: "ppgtt-type: %d\n", runtime->ppgtt_type);
118 drm_printf(p, f: "dma_mask_size: %u\n", info->dma_mask_size);
119
120#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name))
121 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
122#undef PRINT_FLAG
123
124 drm_printf(p, f: "has_pooled_eu: %s\n", str_yes_no(v: runtime->has_pooled_eu));
125}
126
127#define ID(id) (id)
128
129static const u16 subplatform_ult_ids[] = {
130 INTEL_HSW_ULT_GT1_IDS(ID),
131 INTEL_HSW_ULT_GT2_IDS(ID),
132 INTEL_HSW_ULT_GT3_IDS(ID),
133 INTEL_BDW_ULT_GT1_IDS(ID),
134 INTEL_BDW_ULT_GT2_IDS(ID),
135 INTEL_BDW_ULT_GT3_IDS(ID),
136 INTEL_BDW_ULT_RSVD_IDS(ID),
137 INTEL_SKL_ULT_GT1_IDS(ID),
138 INTEL_SKL_ULT_GT2_IDS(ID),
139 INTEL_SKL_ULT_GT3_IDS(ID),
140 INTEL_KBL_ULT_GT1_IDS(ID),
141 INTEL_KBL_ULT_GT2_IDS(ID),
142 INTEL_KBL_ULT_GT3_IDS(ID),
143 INTEL_CFL_U_GT2_IDS(ID),
144 INTEL_CFL_U_GT3_IDS(ID),
145 INTEL_WHL_U_GT1_IDS(ID),
146 INTEL_WHL_U_GT2_IDS(ID),
147 INTEL_WHL_U_GT3_IDS(ID),
148 INTEL_CML_U_GT1_IDS(ID),
149 INTEL_CML_U_GT2_IDS(ID),
150};
151
152static const u16 subplatform_ulx_ids[] = {
153 INTEL_HSW_ULX_GT1_IDS(ID),
154 INTEL_HSW_ULX_GT2_IDS(ID),
155 INTEL_BDW_ULX_GT1_IDS(ID),
156 INTEL_BDW_ULX_GT2_IDS(ID),
157 INTEL_BDW_ULX_GT3_IDS(ID),
158 INTEL_BDW_ULX_RSVD_IDS(ID),
159 INTEL_SKL_ULX_GT1_IDS(ID),
160 INTEL_SKL_ULX_GT2_IDS(ID),
161 INTEL_KBL_ULX_GT1_IDS(ID),
162 INTEL_KBL_ULX_GT2_IDS(ID),
163 INTEL_AML_KBL_GT2_IDS(ID),
164 INTEL_AML_CFL_GT2_IDS(ID),
165};
166
167static const u16 subplatform_portf_ids[] = {
168 INTEL_ICL_PORT_F_IDS(ID),
169};
170
171static const u16 subplatform_uy_ids[] = {
172 INTEL_TGL_GT2_IDS(ID),
173};
174
175static const u16 subplatform_n_ids[] = {
176 INTEL_ADLN_IDS(ID),
177};
178
179static const u16 subplatform_rpl_ids[] = {
180 INTEL_RPLS_IDS(ID),
181 INTEL_RPLU_IDS(ID),
182 INTEL_RPLP_IDS(ID),
183};
184
185static const u16 subplatform_rplu_ids[] = {
186 INTEL_RPLU_IDS(ID),
187};
188
189static const u16 subplatform_g10_ids[] = {
190 INTEL_DG2_G10_IDS(ID),
191 INTEL_ATS_M150_IDS(ID),
192};
193
194static const u16 subplatform_g11_ids[] = {
195 INTEL_DG2_G11_IDS(ID),
196 INTEL_ATS_M75_IDS(ID),
197};
198
199static const u16 subplatform_g12_ids[] = {
200 INTEL_DG2_G12_IDS(ID),
201};
202
203static const u16 subplatform_dg2_d_ids[] = {
204 INTEL_DG2_D_IDS(ID),
205};
206
207static const u16 subplatform_arl_h_ids[] = {
208 INTEL_ARL_H_IDS(ID),
209};
210
211static const u16 subplatform_arl_u_ids[] = {
212 INTEL_ARL_U_IDS(ID),
213};
214
215static const u16 subplatform_arl_s_ids[] = {
216 INTEL_ARL_S_IDS(ID),
217};
218
219static bool find_devid(u16 id, const u16 *p, unsigned int num)
220{
221 for (; num; num--, p++) {
222 if (*p == id)
223 return true;
224 }
225
226 return false;
227}
228
229static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
230{
231 const struct intel_device_info *info = INTEL_INFO(i915);
232 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
233 const unsigned int pi = __platform_mask_index(info: rinfo, p: info->platform);
234 const unsigned int pb = __platform_mask_bit(info: rinfo, p: info->platform);
235 u16 devid = INTEL_DEVID(i915);
236 u32 mask = 0;
237
238 /* Make sure IS_<platform> checks are working. */
239 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
240
241 /* Find and mark subplatform bits based on the PCI device id. */
242 if (find_devid(id: devid, p: subplatform_ult_ids,
243 ARRAY_SIZE(subplatform_ult_ids))) {
244 mask = BIT(INTEL_SUBPLATFORM_ULT);
245 } else if (find_devid(id: devid, p: subplatform_ulx_ids,
246 ARRAY_SIZE(subplatform_ulx_ids))) {
247 mask = BIT(INTEL_SUBPLATFORM_ULX);
248 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
249 /* ULX machines are also considered ULT. */
250 mask |= BIT(INTEL_SUBPLATFORM_ULT);
251 }
252 } else if (find_devid(id: devid, p: subplatform_portf_ids,
253 ARRAY_SIZE(subplatform_portf_ids))) {
254 mask = BIT(INTEL_SUBPLATFORM_PORTF);
255 } else if (find_devid(id: devid, p: subplatform_uy_ids,
256 ARRAY_SIZE(subplatform_uy_ids))) {
257 mask = BIT(INTEL_SUBPLATFORM_UY);
258 } else if (find_devid(id: devid, p: subplatform_n_ids,
259 ARRAY_SIZE(subplatform_n_ids))) {
260 mask = BIT(INTEL_SUBPLATFORM_N);
261 } else if (find_devid(id: devid, p: subplatform_rpl_ids,
262 ARRAY_SIZE(subplatform_rpl_ids))) {
263 mask = BIT(INTEL_SUBPLATFORM_RPL);
264 if (find_devid(id: devid, p: subplatform_rplu_ids,
265 ARRAY_SIZE(subplatform_rplu_ids)))
266 mask |= BIT(INTEL_SUBPLATFORM_RPLU);
267 } else if (find_devid(id: devid, p: subplatform_g10_ids,
268 ARRAY_SIZE(subplatform_g10_ids))) {
269 mask = BIT(INTEL_SUBPLATFORM_G10);
270 } else if (find_devid(id: devid, p: subplatform_g11_ids,
271 ARRAY_SIZE(subplatform_g11_ids))) {
272 mask = BIT(INTEL_SUBPLATFORM_G11);
273 } else if (find_devid(id: devid, p: subplatform_g12_ids,
274 ARRAY_SIZE(subplatform_g12_ids))) {
275 mask = BIT(INTEL_SUBPLATFORM_G12);
276 } else if (find_devid(id: devid, p: subplatform_arl_h_ids,
277 ARRAY_SIZE(subplatform_arl_h_ids))) {
278 mask = BIT(INTEL_SUBPLATFORM_ARL_H);
279 } else if (find_devid(id: devid, p: subplatform_arl_u_ids,
280 ARRAY_SIZE(subplatform_arl_u_ids))) {
281 mask = BIT(INTEL_SUBPLATFORM_ARL_U);
282 } else if (find_devid(id: devid, p: subplatform_arl_s_ids,
283 ARRAY_SIZE(subplatform_arl_s_ids))) {
284 mask = BIT(INTEL_SUBPLATFORM_ARL_S);
285 }
286
287 /* DG2_D ids span across multiple DG2 subplatforms */
288 if (find_devid(id: devid, p: subplatform_dg2_d_ids,
289 ARRAY_SIZE(subplatform_dg2_d_ids)))
290 mask |= BIT(INTEL_SUBPLATFORM_D);
291
292 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
293
294 RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
295}
296
297static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_ip_version *ip)
298{
299 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
300 void __iomem *addr;
301 u32 val;
302 u8 expected_ver = ip->ver;
303 u8 expected_rel = ip->rel;
304
305 addr = pci_iomap_range(dev: pdev, bar: 0, offset, maxlen: sizeof(u32));
306 if (drm_WARN_ON(&i915->drm, !addr))
307 return;
308
309 val = ioread32(addr);
310 pci_iounmap(dev: pdev, addr);
311
312 ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
313 ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
314 ip->step = REG_FIELD_GET(GMD_ID_STEP, val);
315
316 /* Sanity check against expected versions from device info */
317 if (IP_VER(ip->ver, ip->rel) < IP_VER(expected_ver, expected_rel))
318 drm_dbg(&i915->drm,
319 "Hardware reports GMD IP version %u.%u (REG[0x%x] = 0x%08x) but minimum expected is %u.%u\n",
320 ip->ver, ip->rel, offset, val, expected_ver, expected_rel);
321}
322
323/*
324 * Setup the graphics version for the current device. This must be done before
325 * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this
326 * function should be called very early in the driver initialization sequence.
327 *
328 * Regular MMIO access is not yet setup at the point this function is called so
329 * we peek at the appropriate MMIO offset directly. The GMD_ID register is
330 * part of an 'always on' power well by design, so we don't need to worry about
331 * forcewake while reading it.
332 */
333static void intel_ipver_early_init(struct drm_i915_private *i915)
334{
335 struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
336
337 if (!HAS_GMD_ID(i915)) {
338 drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
339 /*
340 * On older platforms, graphics and media share the same ip
341 * version and release.
342 */
343 RUNTIME_INFO(i915)->media.ip =
344 RUNTIME_INFO(i915)->graphics.ip;
345 return;
346 }
347
348 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),
349 ip: &runtime->graphics.ip);
350 /* Wa_22012778468 */
351 if (runtime->graphics.ip.ver == 0x0 &&
352 INTEL_INFO(i915)->platform == INTEL_METEORLAKE) {
353 RUNTIME_INFO(i915)->graphics.ip.ver = 12;
354 RUNTIME_INFO(i915)->graphics.ip.rel = 70;
355 }
356 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
357 ip: &runtime->media.ip);
358}
359
360/**
361 * intel_device_info_runtime_init_early - initialize early runtime info
362 * @i915: the i915 device
363 *
364 * Determine early intel_device_info fields at runtime. This function needs
365 * to be called before the MMIO has been setup.
366 */
367void intel_device_info_runtime_init_early(struct drm_i915_private *i915)
368{
369 intel_ipver_early_init(i915);
370 intel_device_info_subplatform_init(i915);
371}
372
373/**
374 * intel_device_info_runtime_init - initialize runtime info
375 * @dev_priv: the i915 device
376 *
377 * Determine various intel_device_info fields at runtime.
378 *
379 * Use it when either:
380 * - it's judged too laborious to fill n static structures with the limit
381 * when a simple if statement does the job,
382 * - run-time checks (eg read fuse/strap registers) are needed.
383 *
384 * This function needs to be called:
385 * - after the MMIO has been setup as we are reading registers,
386 * - after the PCH has been detected,
387 * - before the first usage of the fields it can tweak.
388 */
389void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
390{
391 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
392
393 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
394
395 if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(i915: dev_priv)) {
396 drm_info(&dev_priv->drm,
397 "Disabling ppGTT for VT-d support\n");
398 runtime->ppgtt_type = INTEL_PPGTT_NONE;
399 }
400}
401
402/*
403 * Set up device info and initial runtime info at driver create.
404 *
405 * Note: i915 is only an allocated blob of memory at this point.
406 */
407void intel_device_info_driver_create(struct drm_i915_private *i915,
408 u16 device_id,
409 const struct intel_device_info *match_info)
410{
411 struct intel_runtime_info *runtime;
412
413 /* Setup INTEL_INFO() */
414 i915->__info = match_info;
415
416 /* Initialize initial runtime info from static const data and pdev. */
417 runtime = RUNTIME_INFO(i915);
418 memcpy(to: runtime, from: &INTEL_INFO(i915)->__runtime, len: sizeof(*runtime));
419
420 runtime->device_id = device_id;
421}
422
423void intel_driver_caps_print(const struct intel_driver_caps *caps,
424 struct drm_printer *p)
425{
426 drm_printf(p, f: "Has logical contexts? %s\n",
427 str_yes_no(v: caps->has_logical_contexts));
428 drm_printf(p, f: "scheduler: 0x%x\n", caps->scheduler);
429}
430