1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
4 * Intel Management Engine Interface (Intel MEI) Linux driver
5 */
6
7#include <linux/pci.h>
8
9#include <linux/kthread.h>
10#include <linux/interrupt.h>
11#include <linux/pm_runtime.h>
12#include <linux/sizes.h>
13#include <linux/delay.h>
14
15#include "mei_dev.h"
16#include "hbm.h"
17
18#include "hw-me.h"
19#include "hw-me-regs.h"
20
21#include "mei-trace.h"
22
23/**
24 * mei_me_reg_read - Reads 32bit data from the mei device
25 *
26 * @hw: the me hardware structure
27 * @offset: offset from which to read the data
28 *
29 * Return: register value (u32)
30 */
31static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
32 unsigned long offset)
33{
34 return ioread32(hw->mem_addr + offset);
35}
36
37
38/**
39 * mei_me_reg_write - Writes 32bit data to the mei device
40 *
41 * @hw: the me hardware structure
42 * @offset: offset from which to write the data
43 * @value: register value to write (u32)
44 */
45static inline void mei_me_reg_write(const struct mei_me_hw *hw,
46 unsigned long offset, u32 value)
47{
48 iowrite32(value, hw->mem_addr + offset);
49}
50
51/**
52 * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
53 * read window register
54 *
55 * @dev: the device structure
56 *
57 * Return: ME_CB_RW register value (u32)
58 */
59static inline u32 mei_me_mecbrw_read(const struct mei_device *dev)
60{
61 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
62}
63
64/**
65 * mei_me_hcbww_write - write 32bit data to the host circular buffer
66 *
67 * @dev: the device structure
68 * @data: 32bit data to be written to the host circular buffer
69 */
70static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data)
71{
72 mei_me_reg_write(to_me_hw(dev), H_CB_WW, value: data);
73}
74
75/**
76 * mei_me_mecsr_read - Reads 32bit data from the ME CSR
77 *
78 * @dev: the device structure
79 *
80 * Return: ME_CSR_HA register value (u32)
81 */
82static inline u32 mei_me_mecsr_read(const struct mei_device *dev)
83{
84 u32 reg;
85
86 reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA);
87 trace_mei_reg_read(dev: &dev->dev, reg: "ME_CSR_HA", ME_CSR_HA, val: reg);
88
89 return reg;
90}
91
92/**
93 * mei_hcsr_read - Reads 32bit data from the host CSR
94 *
95 * @dev: the device structure
96 *
97 * Return: H_CSR register value (u32)
98 */
99static inline u32 mei_hcsr_read(const struct mei_device *dev)
100{
101 u32 reg;
102
103 reg = mei_me_reg_read(to_me_hw(dev), H_CSR);
104 trace_mei_reg_read(dev: &dev->dev, reg: "H_CSR", H_CSR, val: reg);
105
106 return reg;
107}
108
109/**
110 * mei_hcsr_write - writes H_CSR register to the mei device
111 *
112 * @dev: the device structure
113 * @reg: new register value
114 */
115static inline void mei_hcsr_write(struct mei_device *dev, u32 reg)
116{
117 trace_mei_reg_write(dev: &dev->dev, reg: "H_CSR", H_CSR, val: reg);
118 mei_me_reg_write(to_me_hw(dev), H_CSR, value: reg);
119}
120
121/**
122 * mei_hcsr_set - writes H_CSR register to the mei device,
123 * and ignores the H_IS bit for it is write-one-to-zero.
124 *
125 * @dev: the device structure
126 * @reg: new register value
127 */
128static inline void mei_hcsr_set(struct mei_device *dev, u32 reg)
129{
130 reg &= ~H_CSR_IS_MASK;
131 mei_hcsr_write(dev, reg);
132}
133
134/**
135 * mei_hcsr_set_hig - set host interrupt (set H_IG)
136 *
137 * @dev: the device structure
138 */
139static inline void mei_hcsr_set_hig(struct mei_device *dev)
140{
141 u32 hcsr;
142
143 hcsr = mei_hcsr_read(dev) | H_IG;
144 mei_hcsr_set(dev, reg: hcsr);
145}
146
147/**
148 * mei_me_d0i3c_read - Reads 32bit data from the D0I3C register
149 *
150 * @dev: the device structure
151 *
152 * Return: H_D0I3C register value (u32)
153 */
154static inline u32 mei_me_d0i3c_read(const struct mei_device *dev)
155{
156 u32 reg;
157
158 reg = mei_me_reg_read(to_me_hw(dev), H_D0I3C);
159 trace_mei_reg_read(dev: &dev->dev, reg: "H_D0I3C", H_D0I3C, val: reg);
160
161 return reg;
162}
163
164/**
165 * mei_me_d0i3c_write - writes H_D0I3C register to device
166 *
167 * @dev: the device structure
168 * @reg: new register value
169 */
170static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg)
171{
172 trace_mei_reg_write(dev: &dev->dev, reg: "H_D0I3C", H_D0I3C, val: reg);
173 mei_me_reg_write(to_me_hw(dev), H_D0I3C, value: reg);
174}
175
176/**
177 * mei_me_trc_status - read trc status register
178 *
179 * @dev: mei device
180 * @trc: trc status register value
181 *
182 * Return: 0 on success, error otherwise
183 */
184static int mei_me_trc_status(struct mei_device *dev, u32 *trc)
185{
186 struct mei_me_hw *hw = to_me_hw(dev);
187
188 if (!hw->cfg->hw_trc_supported)
189 return -EOPNOTSUPP;
190
191 *trc = mei_me_reg_read(hw, ME_TRC);
192 trace_mei_reg_read(dev: &dev->dev, reg: "ME_TRC", ME_TRC, val: *trc);
193
194 return 0;
195}
196
197/**
198 * mei_me_fw_status - read fw status register from pci config space
199 *
200 * @dev: mei device
201 * @fw_status: fw status register values
202 *
203 * Return: 0 on success, error otherwise
204 */
205static int mei_me_fw_status(struct mei_device *dev,
206 struct mei_fw_status *fw_status)
207{
208 struct mei_me_hw *hw = to_me_hw(dev);
209 const struct mei_fw_status *fw_src = &hw->cfg->fw_status;
210 int ret;
211 int i;
212
213 if (!fw_status || !hw->read_fws)
214 return -EINVAL;
215
216 fw_status->count = fw_src->count;
217 for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
218 ret = hw->read_fws(dev, fw_src->status[i],
219 &fw_status->status[i]);
220 trace_mei_pci_cfg_read(dev: &dev->dev, reg: "PCI_CFG_HFS_X",
221 offs: fw_src->status[i],
222 val: fw_status->status[i]);
223 if (ret)
224 return ret;
225 }
226
227 return 0;
228}
229
230/**
231 * mei_me_hw_config - configure hw dependent settings
232 *
233 * @dev: mei device
234 *
235 * Return:
236 * * -EINVAL when read_fws is not set
237 * * 0 on success
238 *
239 */
240static int mei_me_hw_config(struct mei_device *dev)
241{
242 struct mei_me_hw *hw = to_me_hw(dev);
243 u32 hcsr, reg;
244
245 if (WARN_ON(!hw->read_fws))
246 return -EINVAL;
247
248 /* Doesn't change in runtime */
249 hcsr = mei_hcsr_read(dev);
250 hw->hbuf_depth = (hcsr & H_CBD) >> 24;
251
252 reg = 0;
253 hw->read_fws(dev, PCI_CFG_HFS_1, &reg);
254 trace_mei_pci_cfg_read(dev: &dev->dev, reg: "PCI_CFG_HFS_1", PCI_CFG_HFS_1, val: reg);
255 hw->d0i3_supported =
256 ((reg & PCI_CFG_HFS_1_D0I3_MSK) == PCI_CFG_HFS_1_D0I3_MSK);
257
258 hw->pg_state = MEI_PG_OFF;
259 if (hw->d0i3_supported) {
260 reg = mei_me_d0i3c_read(dev);
261 if (reg & H_D0I3C_I3)
262 hw->pg_state = MEI_PG_ON;
263 }
264
265 return 0;
266}
267
268/**
269 * mei_me_pg_state - translate internal pg state
270 * to the mei power gating state
271 *
272 * @dev: mei device
273 *
274 * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
275 */
276static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)
277{
278 struct mei_me_hw *hw = to_me_hw(dev);
279
280 return hw->pg_state;
281}
282
283static inline u32 me_intr_src(u32 hcsr)
284{
285 return hcsr & H_CSR_IS_MASK;
286}
287
288/**
289 * me_intr_disable - disables mei device interrupts
290 * using supplied hcsr register value.
291 *
292 * @dev: the device structure
293 * @hcsr: supplied hcsr register value
294 */
295static inline void me_intr_disable(struct mei_device *dev, u32 hcsr)
296{
297 hcsr &= ~H_CSR_IE_MASK;
298 mei_hcsr_set(dev, reg: hcsr);
299}
300
301/**
302 * me_intr_clear - clear and stop interrupts
303 *
304 * @dev: the device structure
305 * @hcsr: supplied hcsr register value
306 */
307static inline void me_intr_clear(struct mei_device *dev, u32 hcsr)
308{
309 if (me_intr_src(hcsr))
310 mei_hcsr_write(dev, reg: hcsr);
311}
312
313/**
314 * mei_me_intr_clear - clear and stop interrupts
315 *
316 * @dev: the device structure
317 */
318static void mei_me_intr_clear(struct mei_device *dev)
319{
320 u32 hcsr = mei_hcsr_read(dev);
321
322 me_intr_clear(dev, hcsr);
323}
324/**
325 * mei_me_intr_enable - enables mei device interrupts
326 *
327 * @dev: the device structure
328 */
329static void mei_me_intr_enable(struct mei_device *dev)
330{
331 u32 hcsr;
332
333 if (mei_me_hw_use_polling(to_me_hw(dev)))
334 return;
335
336 hcsr = mei_hcsr_read(dev) | H_CSR_IE_MASK;
337 mei_hcsr_set(dev, reg: hcsr);
338}
339
340/**
341 * mei_me_intr_disable - disables mei device interrupts
342 *
343 * @dev: the device structure
344 */
345static void mei_me_intr_disable(struct mei_device *dev)
346{
347 u32 hcsr = mei_hcsr_read(dev);
348
349 me_intr_disable(dev, hcsr);
350}
351
352/**
353 * mei_me_synchronize_irq - wait for pending IRQ handlers
354 *
355 * @dev: the device structure
356 */
357static void mei_me_synchronize_irq(struct mei_device *dev)
358{
359 struct mei_me_hw *hw = to_me_hw(dev);
360
361 if (mei_me_hw_use_polling(hw))
362 return;
363
364 synchronize_irq(irq: hw->irq);
365}
366
367/**
368 * mei_me_hw_reset_release - release device from the reset
369 *
370 * @dev: the device structure
371 */
372static void mei_me_hw_reset_release(struct mei_device *dev)
373{
374 u32 hcsr = mei_hcsr_read(dev);
375
376 hcsr |= H_IG;
377 hcsr &= ~H_RST;
378 mei_hcsr_set(dev, reg: hcsr);
379}
380
381/**
382 * mei_me_host_set_ready - enable device
383 *
384 * @dev: mei device
385 */
386static void mei_me_host_set_ready(struct mei_device *dev)
387{
388 u32 hcsr = mei_hcsr_read(dev);
389
390 if (!mei_me_hw_use_polling(to_me_hw(dev)))
391 hcsr |= H_CSR_IE_MASK;
392
393 hcsr |= H_IG | H_RDY;
394 mei_hcsr_set(dev, reg: hcsr);
395}
396
397/**
398 * mei_me_host_is_ready - check whether the host has turned ready
399 *
400 * @dev: mei device
401 * Return: bool
402 */
403static bool mei_me_host_is_ready(struct mei_device *dev)
404{
405 u32 hcsr = mei_hcsr_read(dev);
406
407 return (hcsr & H_RDY) == H_RDY;
408}
409
410/**
411 * mei_me_hw_is_ready - check whether the me(hw) has turned ready
412 *
413 * @dev: mei device
414 * Return: bool
415 */
416static bool mei_me_hw_is_ready(struct mei_device *dev)
417{
418 u32 mecsr = mei_me_mecsr_read(dev);
419
420 return (mecsr & ME_RDY_HRA) == ME_RDY_HRA;
421}
422
423/**
424 * mei_me_hw_is_resetting - check whether the me(hw) is in reset
425 *
426 * @dev: mei device
427 * Return: bool
428 */
429static bool mei_me_hw_is_resetting(struct mei_device *dev)
430{
431 u32 mecsr = mei_me_mecsr_read(dev);
432
433 return (mecsr & ME_RST_HRA) == ME_RST_HRA;
434}
435
436/**
437 * mei_gsc_pxp_check - check for gsc firmware entering pxp mode
438 *
439 * @dev: the device structure
440 */
441static void mei_gsc_pxp_check(struct mei_device *dev)
442{
443 struct mei_me_hw *hw = to_me_hw(dev);
444 u32 fwsts5 = 0;
445
446 if (!kind_is_gsc(dev) && !kind_is_gscfi(dev))
447 return;
448
449 hw->read_fws(dev, PCI_CFG_HFS_5, &fwsts5);
450 trace_mei_pci_cfg_read(dev: &dev->dev, reg: "PCI_CFG_HFS_5", PCI_CFG_HFS_5, val: fwsts5);
451
452 if ((fwsts5 & GSC_CFG_HFS_5_BOOT_TYPE_MSK) == GSC_CFG_HFS_5_BOOT_TYPE_PXP) {
453 if (dev->gsc_reset_to_pxp == MEI_DEV_RESET_TO_PXP_DEFAULT)
454 dev->gsc_reset_to_pxp = MEI_DEV_RESET_TO_PXP_PERFORMED;
455 } else {
456 dev->gsc_reset_to_pxp = MEI_DEV_RESET_TO_PXP_DEFAULT;
457 }
458
459 if (dev->pxp_mode == MEI_DEV_PXP_DEFAULT)
460 return;
461
462 if ((fwsts5 & GSC_CFG_HFS_5_BOOT_TYPE_MSK) == GSC_CFG_HFS_5_BOOT_TYPE_PXP) {
463 dev_dbg(&dev->dev, "pxp mode is ready 0x%08x\n", fwsts5);
464 dev->pxp_mode = MEI_DEV_PXP_READY;
465 } else {
466 dev_dbg(&dev->dev, "pxp mode is not ready 0x%08x\n", fwsts5);
467 }
468}
469
470/**
471 * mei_me_hw_ready_wait - wait until the me(hw) has turned ready
472 * or timeout is reached
473 *
474 * @dev: mei device
475 * Return: 0 on success, error otherwise
476 */
477static int mei_me_hw_ready_wait(struct mei_device *dev)
478{
479 mutex_unlock(lock: &dev->device_lock);
480 wait_event_timeout(dev->wait_hw_ready,
481 dev->recvd_hw_ready,
482 dev->timeouts.hw_ready);
483 mutex_lock(lock: &dev->device_lock);
484 if (!dev->recvd_hw_ready) {
485 dev_err(&dev->dev, "wait hw ready failed\n");
486 return -ETIME;
487 }
488
489 mei_gsc_pxp_check(dev);
490
491 mei_me_hw_reset_release(dev);
492 dev->recvd_hw_ready = false;
493 return 0;
494}
495
496/**
497 * mei_me_hw_start - hw start routine
498 *
499 * @dev: mei device
500 * Return: 0 on success, error otherwise
501 */
502static int mei_me_hw_start(struct mei_device *dev)
503{
504 int ret = mei_me_hw_ready_wait(dev);
505
506 if ((kind_is_gsc(dev) || kind_is_gscfi(dev)) &&
507 dev->gsc_reset_to_pxp == MEI_DEV_RESET_TO_PXP_PERFORMED)
508 dev->gsc_reset_to_pxp = MEI_DEV_RESET_TO_PXP_DONE;
509 if (ret)
510 return ret;
511 dev_dbg(&dev->dev, "hw is ready\n");
512
513 mei_me_host_set_ready(dev);
514 return ret;
515}
516
517
518/**
519 * mei_hbuf_filled_slots - gets number of device filled buffer slots
520 *
521 * @dev: the device structure
522 *
523 * Return: number of filled slots
524 */
525static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
526{
527 u32 hcsr;
528 char read_ptr, write_ptr;
529
530 hcsr = mei_hcsr_read(dev);
531
532 read_ptr = (char) ((hcsr & H_CBRP) >> 8);
533 write_ptr = (char) ((hcsr & H_CBWP) >> 16);
534
535 return (unsigned char) (write_ptr - read_ptr);
536}
537
538/**
539 * mei_me_hbuf_is_empty - checks if host buffer is empty.
540 *
541 * @dev: the device structure
542 *
543 * Return: true if empty, false - otherwise.
544 */
545static bool mei_me_hbuf_is_empty(struct mei_device *dev)
546{
547 return mei_hbuf_filled_slots(dev) == 0;
548}
549
550/**
551 * mei_me_hbuf_empty_slots - counts write empty slots.
552 *
553 * @dev: the device structure
554 *
555 * Return: -EOVERFLOW if overflow, otherwise empty slots count
556 */
557static int mei_me_hbuf_empty_slots(struct mei_device *dev)
558{
559 struct mei_me_hw *hw = to_me_hw(dev);
560 unsigned char filled_slots, empty_slots;
561
562 filled_slots = mei_hbuf_filled_slots(dev);
563 empty_slots = hw->hbuf_depth - filled_slots;
564
565 /* check for overflow */
566 if (filled_slots > hw->hbuf_depth)
567 return -EOVERFLOW;
568
569 return empty_slots;
570}
571
572/**
573 * mei_me_hbuf_depth - returns depth of the hw buffer.
574 *
575 * @dev: the device structure
576 *
577 * Return: size of hw buffer in slots
578 */
579static u32 mei_me_hbuf_depth(const struct mei_device *dev)
580{
581 struct mei_me_hw *hw = to_me_hw(dev);
582
583 return hw->hbuf_depth;
584}
585
586/**
587 * mei_me_hbuf_write - writes a message to host hw buffer.
588 *
589 * @dev: the device structure
590 * @hdr: header of message
591 * @hdr_len: header length in bytes: must be multiplication of a slot (4bytes)
592 * @data: payload
593 * @data_len: payload length in bytes
594 *
595 * Return: 0 if success, < 0 - otherwise.
596 */
597static int mei_me_hbuf_write(struct mei_device *dev,
598 const void *hdr, size_t hdr_len,
599 const void *data, size_t data_len)
600{
601 unsigned long rem;
602 unsigned long i;
603 const u32 *reg_buf;
604 u32 dw_cnt;
605 int empty_slots;
606
607 if (WARN_ON(!hdr || hdr_len & 0x3))
608 return -EINVAL;
609
610 if (!data && data_len) {
611 dev_err(&dev->dev, "wrong parameters null data with data_len = %zu\n", data_len);
612 return -EINVAL;
613 }
614
615 dev_dbg(&dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr));
616
617 empty_slots = mei_hbuf_empty_slots(dev);
618 dev_dbg(&dev->dev, "empty slots = %d.\n", empty_slots);
619
620 if (empty_slots < 0)
621 return -EOVERFLOW;
622
623 dw_cnt = mei_data2slots(length: hdr_len + data_len);
624 if (dw_cnt > (u32)empty_slots)
625 return -EMSGSIZE;
626
627 reg_buf = hdr;
628 for (i = 0; i < hdr_len / MEI_SLOT_SIZE; i++)
629 mei_me_hcbww_write(dev, data: reg_buf[i]);
630
631 reg_buf = data;
632 for (i = 0; i < data_len / MEI_SLOT_SIZE; i++)
633 mei_me_hcbww_write(dev, data: reg_buf[i]);
634
635 rem = data_len & 0x3;
636 if (rem > 0) {
637 u32 reg = 0;
638
639 memcpy(to: &reg, from: (const u8 *)data + data_len - rem, len: rem);
640 mei_me_hcbww_write(dev, data: reg);
641 }
642
643 mei_hcsr_set_hig(dev);
644 if (!mei_me_hw_is_ready(dev))
645 return -EIO;
646
647 return 0;
648}
649
650/**
651 * mei_me_count_full_read_slots - counts read full slots.
652 *
653 * @dev: the device structure
654 *
655 * Return: -EOVERFLOW if overflow, otherwise filled slots count
656 */
657static int mei_me_count_full_read_slots(struct mei_device *dev)
658{
659 u32 me_csr;
660 char read_ptr, write_ptr;
661 unsigned char buffer_depth, filled_slots;
662
663 me_csr = mei_me_mecsr_read(dev);
664 buffer_depth = (unsigned char)((me_csr & ME_CBD_HRA) >> 24);
665 read_ptr = (char) ((me_csr & ME_CBRP_HRA) >> 8);
666 write_ptr = (char) ((me_csr & ME_CBWP_HRA) >> 16);
667 filled_slots = (unsigned char) (write_ptr - read_ptr);
668
669 /* check for overflow */
670 if (filled_slots > buffer_depth)
671 return -EOVERFLOW;
672
673 dev_dbg(&dev->dev, "filled_slots =%08x\n", filled_slots);
674 return (int)filled_slots;
675}
676
677/**
678 * mei_me_read_slots - reads a message from mei device.
679 *
680 * @dev: the device structure
681 * @buffer: message buffer will be written
682 * @buffer_length: message size will be read
683 *
684 * Return: always 0
685 */
686static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
687 unsigned long buffer_length)
688{
689 u32 *reg_buf = (u32 *)buffer;
690
691 for (; buffer_length >= MEI_SLOT_SIZE; buffer_length -= MEI_SLOT_SIZE)
692 *reg_buf++ = mei_me_mecbrw_read(dev);
693
694 if (buffer_length > 0) {
695 u32 reg = mei_me_mecbrw_read(dev);
696
697 memcpy(to: reg_buf, from: &reg, len: buffer_length);
698 }
699
700 mei_hcsr_set_hig(dev);
701 return 0;
702}
703
704/**
705 * mei_me_pg_set - write pg enter register
706 *
707 * @dev: the device structure
708 */
709static void mei_me_pg_set(struct mei_device *dev)
710{
711 struct mei_me_hw *hw = to_me_hw(dev);
712 u32 reg;
713
714 reg = mei_me_reg_read(hw, H_HPG_CSR);
715 trace_mei_reg_read(dev: &dev->dev, reg: "H_HPG_CSR", H_HPG_CSR, val: reg);
716
717 reg |= H_HPG_CSR_PGI;
718
719 trace_mei_reg_write(dev: &dev->dev, reg: "H_HPG_CSR", H_HPG_CSR, val: reg);
720 mei_me_reg_write(hw, H_HPG_CSR, value: reg);
721}
722
723/**
724 * mei_me_pg_unset - write pg exit register
725 *
726 * @dev: the device structure
727 */
728static void mei_me_pg_unset(struct mei_device *dev)
729{
730 struct mei_me_hw *hw = to_me_hw(dev);
731 u32 reg;
732
733 reg = mei_me_reg_read(hw, H_HPG_CSR);
734 trace_mei_reg_read(dev: &dev->dev, reg: "H_HPG_CSR", H_HPG_CSR, val: reg);
735
736 WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n");
737
738 reg |= H_HPG_CSR_PGIHEXR;
739
740 trace_mei_reg_write(dev: &dev->dev, reg: "H_HPG_CSR", H_HPG_CSR, val: reg);
741 mei_me_reg_write(hw, H_HPG_CSR, value: reg);
742}
743
744/**
745 * mei_me_pg_legacy_enter_sync - perform legacy pg entry procedure
746 *
747 * @dev: the device structure
748 *
749 * Return: 0 on success an error code otherwise
750 */
751static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
752{
753 struct mei_me_hw *hw = to_me_hw(dev);
754 int ret;
755
756 dev->pg_event = MEI_PG_EVENT_WAIT;
757
758 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
759 if (ret)
760 return ret;
761
762 mutex_unlock(lock: &dev->device_lock);
763 wait_event_timeout(dev->wait_pg,
764 dev->pg_event == MEI_PG_EVENT_RECEIVED,
765 dev->timeouts.pgi);
766 mutex_lock(lock: &dev->device_lock);
767
768 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
769 mei_me_pg_set(dev);
770 ret = 0;
771 } else {
772 ret = -ETIME;
773 }
774
775 dev->pg_event = MEI_PG_EVENT_IDLE;
776 hw->pg_state = MEI_PG_ON;
777
778 return ret;
779}
780
781/**
782 * mei_me_pg_legacy_exit_sync - perform legacy pg exit procedure
783 *
784 * @dev: the device structure
785 *
786 * Return: 0 on success an error code otherwise
787 */
788static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
789{
790 struct mei_me_hw *hw = to_me_hw(dev);
791 int ret;
792
793 if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
794 goto reply;
795
796 dev->pg_event = MEI_PG_EVENT_WAIT;
797
798 mei_me_pg_unset(dev);
799
800 mutex_unlock(lock: &dev->device_lock);
801 wait_event_timeout(dev->wait_pg,
802 dev->pg_event == MEI_PG_EVENT_RECEIVED,
803 dev->timeouts.pgi);
804 mutex_lock(lock: &dev->device_lock);
805
806reply:
807 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
808 ret = -ETIME;
809 goto out;
810 }
811
812 dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
813 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD);
814 if (ret)
815 return ret;
816
817 mutex_unlock(lock: &dev->device_lock);
818 wait_event_timeout(dev->wait_pg,
819 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
820 dev->timeouts.pgi);
821 mutex_lock(lock: &dev->device_lock);
822
823 if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED)
824 ret = 0;
825 else
826 ret = -ETIME;
827
828out:
829 dev->pg_event = MEI_PG_EVENT_IDLE;
830 hw->pg_state = MEI_PG_OFF;
831
832 return ret;
833}
834
835/**
836 * mei_me_pg_in_transition - is device now in pg transition
837 *
838 * @dev: the device structure
839 *
840 * Return: true if in pg transition, false otherwise
841 */
842static bool mei_me_pg_in_transition(struct mei_device *dev)
843{
844 return dev->pg_event >= MEI_PG_EVENT_WAIT &&
845 dev->pg_event <= MEI_PG_EVENT_INTR_WAIT;
846}
847
848/**
849 * mei_me_pg_is_enabled - detect if PG is supported by HW
850 *
851 * @dev: the device structure
852 *
853 * Return: true is pg supported, false otherwise
854 */
855static bool mei_me_pg_is_enabled(struct mei_device *dev)
856{
857 struct mei_me_hw *hw = to_me_hw(dev);
858 u32 reg = mei_me_mecsr_read(dev);
859
860 if (hw->d0i3_supported)
861 return true;
862
863 if ((reg & ME_PGIC_HRA) == 0)
864 goto notsupported;
865
866 if (!dev->hbm_f_pg_supported)
867 goto notsupported;
868
869 return true;
870
871notsupported:
872 dev_dbg(&dev->dev, "pg: not supported: d0i3 = %d HGP = %d hbm version %d.%d ?= %d.%d\n",
873 hw->d0i3_supported,
874 !!(reg & ME_PGIC_HRA),
875 dev->version.major_version,
876 dev->version.minor_version,
877 HBM_MAJOR_VERSION_PGI,
878 HBM_MINOR_VERSION_PGI);
879
880 return false;
881}
882
883/**
884 * mei_me_d0i3_set - write d0i3 register bit on mei device.
885 *
886 * @dev: the device structure
887 * @intr: ask for interrupt
888 *
889 * Return: D0I3C register value
890 */
891static u32 mei_me_d0i3_set(struct mei_device *dev, bool intr)
892{
893 u32 reg = mei_me_d0i3c_read(dev);
894
895 reg |= H_D0I3C_I3;
896 if (intr)
897 reg |= H_D0I3C_IR;
898 else
899 reg &= ~H_D0I3C_IR;
900 mei_me_d0i3c_write(dev, reg);
901 /* read it to ensure HW consistency */
902 reg = mei_me_d0i3c_read(dev);
903 return reg;
904}
905
906/**
907 * mei_me_d0i3_unset - clean d0i3 register bit on mei device.
908 *
909 * @dev: the device structure
910 *
911 * Return: D0I3C register value
912 */
913static u32 mei_me_d0i3_unset(struct mei_device *dev)
914{
915 u32 reg = mei_me_d0i3c_read(dev);
916
917 reg &= ~H_D0I3C_I3;
918 reg |= H_D0I3C_IR;
919 mei_me_d0i3c_write(dev, reg);
920 /* read it to ensure HW consistency */
921 reg = mei_me_d0i3c_read(dev);
922 return reg;
923}
924
925/**
926 * mei_me_d0i3_enter_sync - perform d0i3 entry procedure
927 *
928 * @dev: the device structure
929 *
930 * Return: 0 on success an error code otherwise
931 */
932static int mei_me_d0i3_enter_sync(struct mei_device *dev)
933{
934 struct mei_me_hw *hw = to_me_hw(dev);
935 int ret;
936 u32 reg;
937
938 reg = mei_me_d0i3c_read(dev);
939 if (reg & H_D0I3C_I3) {
940 /* we are in d0i3, nothing to do */
941 dev_dbg(&dev->dev, "d0i3 set not needed\n");
942 ret = 0;
943 goto on;
944 }
945
946 /* PGI entry procedure */
947 dev->pg_event = MEI_PG_EVENT_WAIT;
948
949 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
950 if (ret)
951 /* FIXME: should we reset here? */
952 goto out;
953
954 mutex_unlock(lock: &dev->device_lock);
955 wait_event_timeout(dev->wait_pg,
956 dev->pg_event == MEI_PG_EVENT_RECEIVED,
957 dev->timeouts.pgi);
958 mutex_lock(lock: &dev->device_lock);
959
960 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
961 ret = -ETIME;
962 goto out;
963 }
964 /* end PGI entry procedure */
965
966 dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
967
968 reg = mei_me_d0i3_set(dev, intr: true);
969 if (!(reg & H_D0I3C_CIP)) {
970 dev_dbg(&dev->dev, "d0i3 enter wait not needed\n");
971 ret = 0;
972 goto on;
973 }
974
975 mutex_unlock(lock: &dev->device_lock);
976 wait_event_timeout(dev->wait_pg,
977 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
978 dev->timeouts.d0i3);
979 mutex_lock(lock: &dev->device_lock);
980
981 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
982 reg = mei_me_d0i3c_read(dev);
983 if (!(reg & H_D0I3C_I3)) {
984 ret = -ETIME;
985 goto out;
986 }
987 }
988
989 ret = 0;
990on:
991 hw->pg_state = MEI_PG_ON;
992out:
993 dev->pg_event = MEI_PG_EVENT_IDLE;
994 dev_dbg(&dev->dev, "d0i3 enter ret = %d\n", ret);
995 return ret;
996}
997
998/**
999 * mei_me_d0i3_enter - perform d0i3 entry procedure
1000 * no hbm PG handshake
1001 * no waiting for confirmation; runs with interrupts
1002 * disabled
1003 *
1004 * @dev: the device structure
1005 *
1006 * Return: 0 on success an error code otherwise
1007 */
1008static int mei_me_d0i3_enter(struct mei_device *dev)
1009{
1010 struct mei_me_hw *hw = to_me_hw(dev);
1011 u32 reg;
1012
1013 reg = mei_me_d0i3c_read(dev);
1014 if (reg & H_D0I3C_I3) {
1015 /* we are in d0i3, nothing to do */
1016 dev_dbg(&dev->dev, "already d0i3 : set not needed\n");
1017 goto on;
1018 }
1019
1020 mei_me_d0i3_set(dev, intr: false);
1021on:
1022 hw->pg_state = MEI_PG_ON;
1023 dev->pg_event = MEI_PG_EVENT_IDLE;
1024 dev_dbg(&dev->dev, "d0i3 enter\n");
1025 return 0;
1026}
1027
1028/**
1029 * mei_me_d0i3_exit_sync - perform d0i3 exit procedure
1030 *
1031 * @dev: the device structure
1032 *
1033 * Return: 0 on success an error code otherwise
1034 */
1035static int mei_me_d0i3_exit_sync(struct mei_device *dev)
1036{
1037 struct mei_me_hw *hw = to_me_hw(dev);
1038 int ret;
1039 u32 reg;
1040
1041 dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
1042
1043 reg = mei_me_d0i3c_read(dev);
1044 if (!(reg & H_D0I3C_I3)) {
1045 /* we are not in d0i3, nothing to do */
1046 dev_dbg(&dev->dev, "d0i3 exit not needed\n");
1047 ret = 0;
1048 goto off;
1049 }
1050
1051 reg = mei_me_d0i3_unset(dev);
1052 if (!(reg & H_D0I3C_CIP)) {
1053 dev_dbg(&dev->dev, "d0i3 exit wait not needed\n");
1054 ret = 0;
1055 goto off;
1056 }
1057
1058 mutex_unlock(lock: &dev->device_lock);
1059 wait_event_timeout(dev->wait_pg,
1060 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
1061 dev->timeouts.d0i3);
1062 mutex_lock(lock: &dev->device_lock);
1063
1064 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
1065 reg = mei_me_d0i3c_read(dev);
1066 if (reg & H_D0I3C_I3) {
1067 ret = -ETIME;
1068 goto out;
1069 }
1070 }
1071
1072 ret = 0;
1073off:
1074 hw->pg_state = MEI_PG_OFF;
1075out:
1076 dev->pg_event = MEI_PG_EVENT_IDLE;
1077
1078 dev_dbg(&dev->dev, "d0i3 exit ret = %d\n", ret);
1079 return ret;
1080}
1081
1082/**
1083 * mei_me_pg_legacy_intr - perform legacy pg processing
1084 * in interrupt thread handler
1085 *
1086 * @dev: the device structure
1087 */
1088static void mei_me_pg_legacy_intr(struct mei_device *dev)
1089{
1090 struct mei_me_hw *hw = to_me_hw(dev);
1091
1092 if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT)
1093 return;
1094
1095 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED;
1096 hw->pg_state = MEI_PG_OFF;
1097 if (waitqueue_active(wq_head: &dev->wait_pg))
1098 wake_up(&dev->wait_pg);
1099}
1100
1101/**
1102 * mei_me_d0i3_intr - perform d0i3 processing in interrupt thread handler
1103 *
1104 * @dev: the device structure
1105 * @intr_source: interrupt source
1106 */
1107static void mei_me_d0i3_intr(struct mei_device *dev, u32 intr_source)
1108{
1109 struct mei_me_hw *hw = to_me_hw(dev);
1110
1111 if (dev->pg_event == MEI_PG_EVENT_INTR_WAIT &&
1112 (intr_source & H_D0I3C_IS)) {
1113 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED;
1114 if (hw->pg_state == MEI_PG_ON) {
1115 hw->pg_state = MEI_PG_OFF;
1116 if (dev->hbm_state != MEI_HBM_IDLE) {
1117 /*
1118 * force H_RDY because it could be
1119 * wiped off during PG
1120 */
1121 dev_dbg(&dev->dev, "d0i3 set host ready\n");
1122 mei_me_host_set_ready(dev);
1123 }
1124 } else {
1125 hw->pg_state = MEI_PG_ON;
1126 }
1127
1128 wake_up(&dev->wait_pg);
1129 }
1130
1131 if (hw->pg_state == MEI_PG_ON && (intr_source & H_IS)) {
1132 /*
1133 * HW sent some data and we are in D0i3, so
1134 * we got here because of HW initiated exit from D0i3.
1135 * Start runtime pm resume sequence to exit low power state.
1136 */
1137 dev_dbg(&dev->dev, "d0i3 want resume\n");
1138 mei_hbm_pg_resume(dev);
1139 }
1140}
1141
1142/**
1143 * mei_me_pg_intr - perform pg processing in interrupt thread handler
1144 *
1145 * @dev: the device structure
1146 * @intr_source: interrupt source
1147 */
1148static void mei_me_pg_intr(struct mei_device *dev, u32 intr_source)
1149{
1150 struct mei_me_hw *hw = to_me_hw(dev);
1151
1152 if (hw->d0i3_supported)
1153 mei_me_d0i3_intr(dev, intr_source);
1154 else
1155 mei_me_pg_legacy_intr(dev);
1156}
1157
1158/**
1159 * mei_me_pg_enter_sync - perform runtime pm entry procedure
1160 *
1161 * @dev: the device structure
1162 *
1163 * Return: 0 on success an error code otherwise
1164 */
1165int mei_me_pg_enter_sync(struct mei_device *dev)
1166{
1167 struct mei_me_hw *hw = to_me_hw(dev);
1168
1169 if (hw->d0i3_supported)
1170 return mei_me_d0i3_enter_sync(dev);
1171 else
1172 return mei_me_pg_legacy_enter_sync(dev);
1173}
1174
1175/**
1176 * mei_me_pg_exit_sync - perform runtime pm exit procedure
1177 *
1178 * @dev: the device structure
1179 *
1180 * Return: 0 on success an error code otherwise
1181 */
1182int mei_me_pg_exit_sync(struct mei_device *dev)
1183{
1184 struct mei_me_hw *hw = to_me_hw(dev);
1185
1186 if (hw->d0i3_supported)
1187 return mei_me_d0i3_exit_sync(dev);
1188 else
1189 return mei_me_pg_legacy_exit_sync(dev);
1190}
1191
1192/**
1193 * mei_me_hw_reset - resets fw via mei csr register.
1194 *
1195 * @dev: the device structure
1196 * @intr_enable: if interrupt should be enabled after reset.
1197 *
1198 * Return: 0 on success an error code otherwise
1199 */
1200static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
1201{
1202 struct mei_me_hw *hw = to_me_hw(dev);
1203 int ret;
1204 u32 hcsr;
1205
1206 if (intr_enable) {
1207 mei_me_intr_enable(dev);
1208 if (hw->d0i3_supported) {
1209 ret = mei_me_d0i3_exit_sync(dev);
1210 if (ret)
1211 return ret;
1212 } else {
1213 hw->pg_state = MEI_PG_OFF;
1214 }
1215 }
1216
1217 pm_runtime_set_active(dev: dev->parent);
1218
1219 hcsr = mei_hcsr_read(dev);
1220 /* H_RST may be found lit before reset is started,
1221 * for example if preceding reset flow hasn't completed.
1222 * In that case asserting H_RST will be ignored, therefore
1223 * we need to clean H_RST bit to start a successful reset sequence.
1224 */
1225 if ((hcsr & H_RST) == H_RST) {
1226 dev_warn(&dev->dev, "H_RST is set = 0x%08X", hcsr);
1227 hcsr &= ~H_RST;
1228 mei_hcsr_set(dev, reg: hcsr);
1229 hcsr = mei_hcsr_read(dev);
1230 }
1231
1232 hcsr |= H_RST | H_IG | H_CSR_IS_MASK;
1233
1234 if (!intr_enable || mei_me_hw_use_polling(to_me_hw(dev)))
1235 hcsr &= ~H_CSR_IE_MASK;
1236
1237 dev->recvd_hw_ready = false;
1238 mei_hcsr_write(dev, reg: hcsr);
1239
1240 /*
1241 * Host reads the H_CSR once to ensure that the
1242 * posted write to H_CSR completes.
1243 */
1244 hcsr = mei_hcsr_read(dev);
1245
1246 if ((hcsr & H_RST) == 0)
1247 dev_warn(&dev->dev, "H_RST is not set = 0x%08X", hcsr);
1248
1249 if ((hcsr & H_RDY) == H_RDY)
1250 dev_warn(&dev->dev, "H_RDY is not cleared 0x%08X", hcsr);
1251
1252 if (!intr_enable) {
1253 mei_me_hw_reset_release(dev);
1254 if (hw->d0i3_supported) {
1255 ret = mei_me_d0i3_enter(dev);
1256 if (ret)
1257 return ret;
1258 }
1259 }
1260 return 0;
1261}
1262
1263/**
1264 * mei_me_irq_quick_handler - The ISR of the MEI device
1265 *
1266 * @irq: The irq number
1267 * @dev_id: pointer to the device structure
1268 *
1269 * Return: irqreturn_t
1270 */
1271irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
1272{
1273 struct mei_device *dev = (struct mei_device *)dev_id;
1274 u32 hcsr;
1275
1276 hcsr = mei_hcsr_read(dev);
1277 if (!me_intr_src(hcsr))
1278 return IRQ_NONE;
1279
1280 dev_dbg(&dev->dev, "interrupt source 0x%08X\n", me_intr_src(hcsr));
1281
1282 /* disable interrupts on device */
1283 me_intr_disable(dev, hcsr);
1284 return IRQ_WAKE_THREAD;
1285}
1286EXPORT_SYMBOL_GPL(mei_me_irq_quick_handler);
1287
1288/**
1289 * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
1290 * processing.
1291 *
1292 * @irq: The irq number
1293 * @dev_id: pointer to the device structure
1294 *
1295 * Return: irqreturn_t
1296 *
1297 */
1298irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
1299{
1300 struct mei_device *dev = (struct mei_device *) dev_id;
1301 struct list_head cmpl_list;
1302 s32 slots;
1303 u32 hcsr;
1304 int rets = 0;
1305
1306 dev_dbg(&dev->dev, "function called after ISR to handle the interrupt processing.\n");
1307 /* initialize our complete list */
1308 mutex_lock(lock: &dev->device_lock);
1309
1310 hcsr = mei_hcsr_read(dev);
1311 me_intr_clear(dev, hcsr);
1312
1313 INIT_LIST_HEAD(list: &cmpl_list);
1314
1315 /* check if ME wants a reset */
1316 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
1317 if (kind_is_gsc(dev) || kind_is_gscfi(dev)) {
1318 dev_dbg(&dev->dev, "FW not ready: resetting: dev_state = %d\n",
1319 dev->dev_state);
1320 } else {
1321 dev_warn(&dev->dev, "FW not ready: resetting: dev_state = %d\n",
1322 dev->dev_state);
1323 }
1324 if (dev->dev_state == MEI_DEV_POWERING_DOWN ||
1325 dev->dev_state == MEI_DEV_POWER_DOWN)
1326 mei_cl_all_disconnect(dev);
1327 else if (dev->dev_state != MEI_DEV_DISABLED)
1328 schedule_work(work: &dev->reset_work);
1329 goto end;
1330 }
1331
1332 if (mei_me_hw_is_resetting(dev))
1333 mei_hcsr_set_hig(dev);
1334
1335 mei_me_pg_intr(dev, intr_source: me_intr_src(hcsr));
1336
1337 /* check if we need to start the dev */
1338 if (!mei_host_is_ready(dev)) {
1339 if (mei_hw_is_ready(dev)) {
1340 /* synchronized by dev mutex */
1341 if (waitqueue_active(wq_head: &dev->wait_hw_ready)) {
1342 dev_dbg(&dev->dev, "we need to start the dev.\n");
1343 dev->recvd_hw_ready = true;
1344 wake_up(&dev->wait_hw_ready);
1345 } else if (dev->dev_state != MEI_DEV_UNINITIALIZED &&
1346 dev->dev_state != MEI_DEV_POWERING_DOWN &&
1347 dev->dev_state != MEI_DEV_POWER_DOWN) {
1348 dev_dbg(&dev->dev, "Force link reset.\n");
1349 schedule_work(work: &dev->reset_work);
1350 } else {
1351 dev_dbg(&dev->dev, "Ignore this interrupt in state = %d\n",
1352 dev->dev_state);
1353 }
1354 } else {
1355 dev_dbg(&dev->dev, "Spurious Interrupt\n");
1356 }
1357 goto end;
1358 }
1359 /* check slots available for reading */
1360 slots = mei_count_full_read_slots(dev);
1361 while (slots > 0) {
1362 dev_dbg(&dev->dev, "slots to read = %08x\n", slots);
1363 rets = mei_irq_read_handler(dev, cmpl_list: &cmpl_list, slots: &slots);
1364 /* There is a race between ME write and interrupt delivery:
1365 * Not all data is always available immediately after the
1366 * interrupt, so try to read again on the next interrupt.
1367 */
1368 if (rets == -ENODATA)
1369 break;
1370
1371 if (rets) {
1372 dev_err(&dev->dev, "mei_irq_read_handler ret = %d, state = %d.\n",
1373 rets, dev->dev_state);
1374 if (dev->dev_state != MEI_DEV_RESETTING &&
1375 dev->dev_state != MEI_DEV_DISABLED &&
1376 dev->dev_state != MEI_DEV_POWERING_DOWN &&
1377 dev->dev_state != MEI_DEV_POWER_DOWN)
1378 schedule_work(work: &dev->reset_work);
1379 goto end;
1380 }
1381 }
1382
1383 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1384
1385 /*
1386 * During PG handshake only allowed write is the replay to the
1387 * PG exit message, so block calling write function
1388 * if the pg event is in PG handshake
1389 */
1390 if (dev->pg_event != MEI_PG_EVENT_WAIT &&
1391 dev->pg_event != MEI_PG_EVENT_RECEIVED) {
1392 rets = mei_irq_write_handler(dev, cmpl_list: &cmpl_list);
1393 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1394 }
1395
1396 mei_irq_compl_handler(dev, cmpl_list: &cmpl_list);
1397
1398end:
1399 dev_dbg(&dev->dev, "interrupt thread end ret = %d\n", rets);
1400 mei_me_intr_enable(dev);
1401 mutex_unlock(lock: &dev->device_lock);
1402 return IRQ_HANDLED;
1403}
1404EXPORT_SYMBOL_GPL(mei_me_irq_thread_handler);
1405
1406#define MEI_POLLING_TIMEOUT_ACTIVE 100
1407#define MEI_POLLING_TIMEOUT_IDLE 500
1408
1409/**
1410 * mei_me_polling_thread - interrupt register polling thread
1411 *
1412 * @_dev: mei device
1413 *
1414 * The thread monitors the interrupt source register and calls
1415 * mei_me_irq_thread_handler() to handle the firmware
1416 * input.
1417 *
1418 * The function polls in MEI_POLLING_TIMEOUT_ACTIVE timeout
1419 * in case there was an event, in idle case the polling
1420 * time increases yet again by MEI_POLLING_TIMEOUT_ACTIVE
1421 * up to MEI_POLLING_TIMEOUT_IDLE.
1422 *
1423 * Return: always 0
1424 */
1425int mei_me_polling_thread(void *_dev)
1426{
1427 struct mei_device *dev = _dev;
1428 irqreturn_t irq_ret;
1429 long polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE;
1430
1431 dev_dbg(&dev->dev, "kernel thread is running\n");
1432 while (!kthread_should_stop()) {
1433 struct mei_me_hw *hw = to_me_hw(dev);
1434 u32 hcsr;
1435
1436 wait_event_timeout(hw->wait_active,
1437 hw->is_active || kthread_should_stop(),
1438 msecs_to_jiffies(MEI_POLLING_TIMEOUT_IDLE));
1439
1440 if (kthread_should_stop())
1441 break;
1442
1443 hcsr = mei_hcsr_read(dev);
1444 if (me_intr_src(hcsr)) {
1445 polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE;
1446 irq_ret = mei_me_irq_thread_handler(1, dev);
1447 if (irq_ret != IRQ_HANDLED)
1448 dev_err(&dev->dev, "irq_ret %d\n", irq_ret);
1449 } else {
1450 /*
1451 * Increase timeout by MEI_POLLING_TIMEOUT_ACTIVE
1452 * up to MEI_POLLING_TIMEOUT_IDLE
1453 */
1454 polling_timeout = clamp_val(polling_timeout + MEI_POLLING_TIMEOUT_ACTIVE,
1455 MEI_POLLING_TIMEOUT_ACTIVE,
1456 MEI_POLLING_TIMEOUT_IDLE);
1457 }
1458
1459 schedule_timeout_interruptible(timeout: msecs_to_jiffies(m: polling_timeout));
1460 }
1461
1462 return 0;
1463}
1464EXPORT_SYMBOL_GPL(mei_me_polling_thread);
1465
1466static const struct mei_hw_ops mei_me_hw_ops = {
1467
1468 .trc_status = mei_me_trc_status,
1469 .fw_status = mei_me_fw_status,
1470 .pg_state = mei_me_pg_state,
1471
1472 .host_is_ready = mei_me_host_is_ready,
1473
1474 .hw_is_ready = mei_me_hw_is_ready,
1475 .hw_reset = mei_me_hw_reset,
1476 .hw_config = mei_me_hw_config,
1477 .hw_start = mei_me_hw_start,
1478
1479 .pg_in_transition = mei_me_pg_in_transition,
1480 .pg_is_enabled = mei_me_pg_is_enabled,
1481
1482 .intr_clear = mei_me_intr_clear,
1483 .intr_enable = mei_me_intr_enable,
1484 .intr_disable = mei_me_intr_disable,
1485 .synchronize_irq = mei_me_synchronize_irq,
1486
1487 .hbuf_free_slots = mei_me_hbuf_empty_slots,
1488 .hbuf_is_ready = mei_me_hbuf_is_empty,
1489 .hbuf_depth = mei_me_hbuf_depth,
1490
1491 .write = mei_me_hbuf_write,
1492
1493 .rdbuf_full_slots = mei_me_count_full_read_slots,
1494 .read_hdr = mei_me_mecbrw_read,
1495 .read = mei_me_read_slots
1496};
1497
1498/**
1499 * mei_me_fw_type_nm() - check for nm sku
1500 *
1501 * @pdev: pci device
1502 *
1503 * Read ME FW Status register to check for the Node Manager (NM) Firmware.
1504 * The NM FW is only signaled in PCI function 0.
1505 * __Note__: Deprecated by PCH8 and newer.
1506 *
1507 * Return: true in case of NM firmware
1508 */
1509static bool mei_me_fw_type_nm(const struct pci_dev *pdev)
1510{
1511 u32 reg;
1512 unsigned int devfn;
1513
1514 devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
1515 pci_bus_read_config_dword(bus: pdev->bus, devfn, PCI_CFG_HFS_2, val: &reg);
1516 trace_mei_pci_cfg_read(dev: &pdev->dev, reg: "PCI_CFG_HFS_2", PCI_CFG_HFS_2, val: reg);
1517 /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
1518 return (reg & 0x600) == 0x200;
1519}
1520
1521#define MEI_CFG_FW_NM \
1522 .quirk_probe = mei_me_fw_type_nm
1523
1524/**
1525 * mei_me_fw_type_sps_4() - check for sps 4.0 sku
1526 *
1527 * @pdev: pci device
1528 *
1529 * Read ME FW Status register to check for SPS Firmware.
1530 * The SPS FW is only signaled in the PCI function 0.
1531 * __Note__: Deprecated by SPS 5.0 and newer.
1532 *
1533 * Return: true in case of SPS firmware
1534 */
1535static bool mei_me_fw_type_sps_4(const struct pci_dev *pdev)
1536{
1537 u32 reg;
1538 unsigned int devfn;
1539
1540 devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
1541 pci_bus_read_config_dword(bus: pdev->bus, devfn, PCI_CFG_HFS_1, val: &reg);
1542 trace_mei_pci_cfg_read(dev: &pdev->dev, reg: "PCI_CFG_HFS_1", PCI_CFG_HFS_1, val: reg);
1543 return (reg & PCI_CFG_HFS_1_OPMODE_MSK) == PCI_CFG_HFS_1_OPMODE_SPS;
1544}
1545
1546#define MEI_CFG_FW_SPS_4 \
1547 .quirk_probe = mei_me_fw_type_sps_4
1548
1549/**
1550 * mei_me_fw_type_sps_ign() - check for sps or ign sku
1551 *
1552 * @pdev: pci device
1553 *
1554 * Read ME FW Status register to check for SPS or IGN Firmware.
1555 * The SPS/IGN FW is only signaled in pci function 0
1556 *
1557 * Return: true in case of SPS/IGN firmware
1558 */
1559static bool mei_me_fw_type_sps_ign(const struct pci_dev *pdev)
1560{
1561 u32 reg;
1562 u32 fw_type;
1563 unsigned int devfn;
1564
1565 devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
1566 pci_bus_read_config_dword(bus: pdev->bus, devfn, PCI_CFG_HFS_3, val: &reg);
1567 trace_mei_pci_cfg_read(dev: &pdev->dev, reg: "PCI_CFG_HFS_3", PCI_CFG_HFS_3, val: reg);
1568 fw_type = (reg & PCI_CFG_HFS_3_FW_SKU_MSK);
1569
1570 dev_dbg(&pdev->dev, "fw type is %d\n", fw_type);
1571
1572 return fw_type == PCI_CFG_HFS_3_FW_SKU_IGN ||
1573 fw_type == PCI_CFG_HFS_3_FW_SKU_SPS;
1574}
1575
1576#define MEI_CFG_KIND_ITOUCH \
1577 .kind = "itouch"
1578
1579#define MEI_CFG_TYPE_GSC \
1580 .kind = "gsc"
1581
1582#define MEI_CFG_TYPE_GSCFI \
1583 .kind = "gscfi"
1584
1585#define MEI_CFG_FW_SPS_IGN \
1586 .quirk_probe = mei_me_fw_type_sps_ign
1587
1588#define MEI_CFG_FW_VER_SUPP \
1589 .fw_ver_supported = 1
1590
1591#define MEI_CFG_ICH_HFS \
1592 .fw_status.count = 0
1593
1594#define MEI_CFG_ICH10_HFS \
1595 .fw_status.count = 1, \
1596 .fw_status.status[0] = PCI_CFG_HFS_1
1597
1598#define MEI_CFG_PCH_HFS \
1599 .fw_status.count = 2, \
1600 .fw_status.status[0] = PCI_CFG_HFS_1, \
1601 .fw_status.status[1] = PCI_CFG_HFS_2
1602
1603#define MEI_CFG_PCH8_HFS \
1604 .fw_status.count = 6, \
1605 .fw_status.status[0] = PCI_CFG_HFS_1, \
1606 .fw_status.status[1] = PCI_CFG_HFS_2, \
1607 .fw_status.status[2] = PCI_CFG_HFS_3, \
1608 .fw_status.status[3] = PCI_CFG_HFS_4, \
1609 .fw_status.status[4] = PCI_CFG_HFS_5, \
1610 .fw_status.status[5] = PCI_CFG_HFS_6
1611
1612#define MEI_CFG_DMA_128 \
1613 .dma_size[DMA_DSCR_HOST] = SZ_128K, \
1614 .dma_size[DMA_DSCR_DEVICE] = SZ_128K, \
1615 .dma_size[DMA_DSCR_CTRL] = PAGE_SIZE
1616
1617#define MEI_CFG_TRC \
1618 .hw_trc_supported = 1
1619
1620/* ICH Legacy devices */
1621static const struct mei_cfg mei_me_ich_cfg = {
1622 MEI_CFG_ICH_HFS,
1623};
1624
1625/* ICH devices */
1626static const struct mei_cfg mei_me_ich10_cfg = {
1627 MEI_CFG_ICH10_HFS,
1628};
1629
1630/* PCH6 devices */
1631static const struct mei_cfg mei_me_pch6_cfg = {
1632 MEI_CFG_PCH_HFS,
1633};
1634
1635/* PCH7 devices */
1636static const struct mei_cfg mei_me_pch7_cfg = {
1637 MEI_CFG_PCH_HFS,
1638 MEI_CFG_FW_VER_SUPP,
1639};
1640
1641/* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */
1642static const struct mei_cfg mei_me_pch_cpt_pbg_cfg = {
1643 MEI_CFG_PCH_HFS,
1644 MEI_CFG_FW_VER_SUPP,
1645 MEI_CFG_FW_NM,
1646};
1647
1648/* PCH8 Lynx Point and newer devices */
1649static const struct mei_cfg mei_me_pch8_cfg = {
1650 MEI_CFG_PCH8_HFS,
1651 MEI_CFG_FW_VER_SUPP,
1652};
1653
1654/* PCH8 Lynx Point and newer devices - iTouch */
1655static const struct mei_cfg mei_me_pch8_itouch_cfg = {
1656 MEI_CFG_KIND_ITOUCH,
1657 MEI_CFG_PCH8_HFS,
1658 MEI_CFG_FW_VER_SUPP,
1659};
1660
1661/* PCH8 Lynx Point with quirk for SPS Firmware exclusion */
1662static const struct mei_cfg mei_me_pch8_sps_4_cfg = {
1663 MEI_CFG_PCH8_HFS,
1664 MEI_CFG_FW_VER_SUPP,
1665 MEI_CFG_FW_SPS_4,
1666};
1667
1668/* LBG with quirk for SPS (4.0) Firmware exclusion */
1669static const struct mei_cfg mei_me_pch12_sps_4_cfg = {
1670 MEI_CFG_PCH8_HFS,
1671 MEI_CFG_FW_VER_SUPP,
1672 MEI_CFG_FW_SPS_4,
1673};
1674
1675/* Cannon Lake and newer devices */
1676static const struct mei_cfg mei_me_pch12_cfg = {
1677 MEI_CFG_PCH8_HFS,
1678 MEI_CFG_FW_VER_SUPP,
1679 MEI_CFG_DMA_128,
1680};
1681
1682/* Cannon Lake with quirk for SPS 5.0 and newer Firmware exclusion */
1683static const struct mei_cfg mei_me_pch12_sps_cfg = {
1684 MEI_CFG_PCH8_HFS,
1685 MEI_CFG_FW_VER_SUPP,
1686 MEI_CFG_DMA_128,
1687 MEI_CFG_FW_SPS_IGN,
1688};
1689
1690/* Cannon Lake itouch with quirk for SPS 5.0 and newer Firmware exclusion
1691 * w/o DMA support.
1692 */
1693static const struct mei_cfg mei_me_pch12_itouch_sps_cfg = {
1694 MEI_CFG_KIND_ITOUCH,
1695 MEI_CFG_PCH8_HFS,
1696 MEI_CFG_FW_VER_SUPP,
1697 MEI_CFG_FW_SPS_IGN,
1698};
1699
1700/* Tiger Lake and newer devices */
1701static const struct mei_cfg mei_me_pch15_cfg = {
1702 MEI_CFG_PCH8_HFS,
1703 MEI_CFG_FW_VER_SUPP,
1704 MEI_CFG_DMA_128,
1705 MEI_CFG_TRC,
1706};
1707
1708/* Tiger Lake with quirk for SPS 5.0 and newer Firmware exclusion */
1709static const struct mei_cfg mei_me_pch15_sps_cfg = {
1710 MEI_CFG_PCH8_HFS,
1711 MEI_CFG_FW_VER_SUPP,
1712 MEI_CFG_DMA_128,
1713 MEI_CFG_TRC,
1714 MEI_CFG_FW_SPS_IGN,
1715};
1716
1717/* Graphics System Controller */
1718static const struct mei_cfg mei_me_gsc_cfg = {
1719 MEI_CFG_TYPE_GSC,
1720 MEI_CFG_PCH8_HFS,
1721 MEI_CFG_FW_VER_SUPP,
1722};
1723
1724/* Graphics System Controller Firmware Interface */
1725static const struct mei_cfg mei_me_gscfi_cfg = {
1726 MEI_CFG_TYPE_GSCFI,
1727 MEI_CFG_PCH8_HFS,
1728 MEI_CFG_FW_VER_SUPP,
1729};
1730
1731/*
1732 * mei_cfg_list - A list of platform platform specific configurations.
1733 * Note: has to be synchronized with enum mei_cfg_idx.
1734 */
1735static const struct mei_cfg *const mei_cfg_list[] = {
1736 [MEI_ME_UNDEF_CFG] = NULL,
1737 [MEI_ME_ICH_CFG] = &mei_me_ich_cfg,
1738 [MEI_ME_ICH10_CFG] = &mei_me_ich10_cfg,
1739 [MEI_ME_PCH6_CFG] = &mei_me_pch6_cfg,
1740 [MEI_ME_PCH7_CFG] = &mei_me_pch7_cfg,
1741 [MEI_ME_PCH_CPT_PBG_CFG] = &mei_me_pch_cpt_pbg_cfg,
1742 [MEI_ME_PCH8_CFG] = &mei_me_pch8_cfg,
1743 [MEI_ME_PCH8_ITOUCH_CFG] = &mei_me_pch8_itouch_cfg,
1744 [MEI_ME_PCH8_SPS_4_CFG] = &mei_me_pch8_sps_4_cfg,
1745 [MEI_ME_PCH12_CFG] = &mei_me_pch12_cfg,
1746 [MEI_ME_PCH12_SPS_4_CFG] = &mei_me_pch12_sps_4_cfg,
1747 [MEI_ME_PCH12_SPS_CFG] = &mei_me_pch12_sps_cfg,
1748 [MEI_ME_PCH12_SPS_ITOUCH_CFG] = &mei_me_pch12_itouch_sps_cfg,
1749 [MEI_ME_PCH15_CFG] = &mei_me_pch15_cfg,
1750 [MEI_ME_PCH15_SPS_CFG] = &mei_me_pch15_sps_cfg,
1751 [MEI_ME_GSC_CFG] = &mei_me_gsc_cfg,
1752 [MEI_ME_GSCFI_CFG] = &mei_me_gscfi_cfg,
1753};
1754
1755const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx)
1756{
1757 BUILD_BUG_ON(ARRAY_SIZE(mei_cfg_list) != MEI_ME_NUM_CFG);
1758
1759 if (idx >= MEI_ME_NUM_CFG)
1760 return NULL;
1761
1762 return mei_cfg_list[idx];
1763}
1764EXPORT_SYMBOL_GPL(mei_me_get_cfg);
1765
1766/**
1767 * mei_me_dev_init - allocates and initializes the mei device structure
1768 *
1769 * @parent: device associated with physical device (pci/platform)
1770 * @cfg: per device generation config
1771 * @slow_fw: configure longer timeouts as FW is slow
1772 *
1773 * Return: The mei_device pointer on success, NULL on failure.
1774 */
1775struct mei_device *mei_me_dev_init(struct device *parent,
1776 const struct mei_cfg *cfg, bool slow_fw)
1777{
1778 struct mei_device *dev;
1779 struct mei_me_hw *hw;
1780 int i;
1781
1782 dev = kzalloc(sizeof(*dev) + sizeof(*hw), GFP_KERNEL);
1783 if (!dev)
1784 return NULL;
1785
1786 hw = to_me_hw(dev);
1787
1788 for (i = 0; i < DMA_DSCR_NUM; i++)
1789 dev->dr_dscr[i].size = cfg->dma_size[i];
1790
1791 mei_device_init(dev, parent, slow_fw, hw_ops: &mei_me_hw_ops);
1792 hw->cfg = cfg;
1793
1794 dev->fw_f_fw_ver_supported = cfg->fw_ver_supported;
1795
1796 dev->kind = cfg->kind;
1797
1798 return dev;
1799}
1800EXPORT_SYMBOL_GPL(mei_me_dev_init);
1801