1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2012-2022, Intel Corporation. All rights reserved.
4 * Intel Management Engine Interface (Intel MEI) Linux driver
5 */
6
7#ifndef _MEI_INTERFACE_H_
8#define _MEI_INTERFACE_H_
9
10#include <linux/irqreturn.h>
11#include <linux/pci.h>
12#include <linux/mei.h>
13
14#include "mei_dev.h"
15#include "client.h"
16
17/*
18 * mei_cfg - mei device configuration
19 *
20 * @fw_status: FW status
21 * @quirk_probe: device exclusion quirk
22 * @kind: MEI head kind
23 * @dma_size: device DMA buffers size
24 * @fw_ver_supported: is fw version retrievable from FW
25 * @hw_trc_supported: does the hw support trc register
26 */
27struct mei_cfg {
28 const struct mei_fw_status fw_status;
29 bool (*quirk_probe)(const struct pci_dev *pdev);
30 const char *kind;
31 size_t dma_size[DMA_DSCR_NUM];
32 u32 fw_ver_supported:1;
33 u32 hw_trc_supported:1;
34};
35
36
37#define MEI_PCI_DEVICE(dev, cfg) \
38 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
39 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
40 .driver_data = (kernel_ulong_t)(cfg),
41
42#define MEI_ME_RPM_TIMEOUT 500 /* ms */
43
44/**
45 * struct mei_me_hw - me hw specific data
46 *
47 * @cfg: per device generation config and ops
48 * @mem_addr: io memory address
49 * @irq: irq number
50 * @pg_state: power gating state
51 * @d0i3_supported: di03 support
52 * @hbuf_depth: depth of hardware host/write buffer in slots
53 * @read_fws: read FW status register handler
54 * @polling_thread: interrupt polling thread
55 * @wait_active: the polling thread activity wait queue
56 * @is_active: the device is active
57 */
58struct mei_me_hw {
59 const struct mei_cfg *cfg;
60 void __iomem *mem_addr;
61 int irq;
62 enum mei_pg_state pg_state;
63 bool d0i3_supported;
64 u8 hbuf_depth;
65 int (*read_fws)(const struct mei_device *dev, int where, u32 *val);
66 /* polling */
67 struct task_struct *polling_thread;
68 wait_queue_head_t wait_active;
69 bool is_active;
70};
71
72#define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw)
73
74static inline bool mei_me_hw_use_polling(const struct mei_me_hw *hw)
75{
76 return hw->irq < 0;
77}
78
79/**
80 * enum mei_cfg_idx - indices to platform specific configurations.
81 *
82 * Note: has to be synchronized with mei_cfg_list[]
83 *
84 * @MEI_ME_UNDEF_CFG: Lower sentinel.
85 * @MEI_ME_ICH_CFG: I/O Controller Hub legacy devices.
86 * @MEI_ME_ICH10_CFG: I/O Controller Hub platforms Gen10
87 * @MEI_ME_PCH6_CFG: Platform Controller Hub platforms (Gen6).
88 * @MEI_ME_PCH7_CFG: Platform Controller Hub platforms (Gen7).
89 * @MEI_ME_PCH_CPT_PBG_CFG:Platform Controller Hub workstations
90 * with quirk for Node Manager exclusion.
91 * @MEI_ME_PCH8_CFG: Platform Controller Hub Gen8 and newer
92 * client platforms.
93 * @MEI_ME_PCH8_ITOUCH_CFG:Platform Controller Hub Gen8 and newer
94 * client platforms (iTouch).
95 * @MEI_ME_PCH8_SPS_4_CFG: Platform Controller Hub Gen8 and newer
96 * servers platforms with quirk for
97 * SPS firmware exclusion.
98 * @MEI_ME_PCH12_CFG: Platform Controller Hub Gen12 and newer
99 * @MEI_ME_PCH12_SPS_4_CFG:Platform Controller Hub Gen12 up to 4.0
100 * servers platforms with quirk for
101 * SPS firmware exclusion.
102 * @MEI_ME_PCH12_SPS_CFG: Platform Controller Hub Gen12 5.0 and newer
103 * servers platforms with quirk for
104 * SPS firmware exclusion.
105 * @MEI_ME_PCH12_SPS_ITOUCH_CFG: Platform Controller Hub Gen12
106 * client platforms (iTouch)
107 * @MEI_ME_PCH15_CFG: Platform Controller Hub Gen15 and newer
108 * @MEI_ME_PCH15_SPS_CFG: Platform Controller Hub Gen15 and newer
109 * servers platforms with quirk for
110 * SPS firmware exclusion.
111 * @MEI_ME_GSC_CFG: Graphics System Controller
112 * @MEI_ME_GSCFI_CFG: Graphics System Controller Firmware Interface
113 * @MEI_ME_NUM_CFG: Upper Sentinel.
114 */
115enum mei_cfg_idx {
116 MEI_ME_UNDEF_CFG,
117 MEI_ME_ICH_CFG,
118 MEI_ME_ICH10_CFG,
119 MEI_ME_PCH6_CFG,
120 MEI_ME_PCH7_CFG,
121 MEI_ME_PCH_CPT_PBG_CFG,
122 MEI_ME_PCH8_CFG,
123 MEI_ME_PCH8_ITOUCH_CFG,
124 MEI_ME_PCH8_SPS_4_CFG,
125 MEI_ME_PCH12_CFG,
126 MEI_ME_PCH12_SPS_4_CFG,
127 MEI_ME_PCH12_SPS_CFG,
128 MEI_ME_PCH12_SPS_ITOUCH_CFG,
129 MEI_ME_PCH15_CFG,
130 MEI_ME_PCH15_SPS_CFG,
131 MEI_ME_GSC_CFG,
132 MEI_ME_GSCFI_CFG,
133 MEI_ME_NUM_CFG,
134};
135
136const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx);
137
138struct mei_device *mei_me_dev_init(struct device *parent,
139 const struct mei_cfg *cfg, bool slow_fw);
140
141int mei_me_pg_enter_sync(struct mei_device *dev);
142int mei_me_pg_exit_sync(struct mei_device *dev);
143
144irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id);
145irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id);
146int mei_me_polling_thread(void *_dev);
147
148#endif /* _MEI_INTERFACE_H_ */
149