1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * r8169_phy_config.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
10 */
11
12#include <linux/delay.h>
13#include <linux/phy.h>
14
15#include "r8169.h"
16
17typedef void (*rtl_phy_cfg_fct)(struct rtl8169_private *tp,
18 struct phy_device *phydev);
19
20static void r8168d_modify_extpage(struct phy_device *phydev, int extpage,
21 int reg, u16 mask, u16 val)
22{
23 int oldpage = phy_select_page(phydev, page: 0x0007);
24
25 __phy_write(phydev, regnum: 0x1e, val: extpage);
26 __phy_modify(phydev, regnum: reg, mask, set: val);
27
28 phy_restore_page(phydev, oldpage, ret: 0);
29}
30
31static void r8168d_phy_param(struct phy_device *phydev, u16 parm,
32 u16 mask, u16 val)
33{
34 int oldpage = phy_select_page(phydev, page: 0x0005);
35
36 __phy_write(phydev, regnum: 0x05, val: parm);
37 __phy_modify(phydev, regnum: 0x06, mask, set: val);
38
39 phy_restore_page(phydev, oldpage, ret: 0);
40}
41
42static void r8168g_phy_param(struct phy_device *phydev, u16 parm,
43 u16 mask, u16 val)
44{
45 int oldpage = phy_select_page(phydev, page: 0x0a43);
46
47 __phy_write(phydev, regnum: 0x13, val: parm);
48 __phy_modify(phydev, regnum: 0x14, mask, set: val);
49
50 phy_restore_page(phydev, oldpage, ret: 0);
51}
52
53static void rtl8125_phy_param(struct phy_device *phydev, u16 parm,
54 u16 mask, u16 val)
55{
56 phy_lock_mdio_bus(phydev);
57 __phy_write_mmd(phydev, MDIO_MMD_VEND2, regnum: 0xb87c, val: parm);
58 __phy_modify_mmd(phydev, MDIO_MMD_VEND2, regnum: 0xb87e, mask, set: val);
59 phy_unlock_mdio_bus(phydev);
60}
61
62struct phy_reg {
63 u16 reg;
64 u16 val;
65};
66
67static void __rtl_writephy_batch(struct phy_device *phydev,
68 const struct phy_reg *regs, int len)
69{
70 phy_lock_mdio_bus(phydev);
71
72 while (len-- > 0) {
73 __phy_write(phydev, regnum: regs->reg, val: regs->val);
74 regs++;
75 }
76
77 phy_unlock_mdio_bus(phydev);
78}
79
80#define rtl_writephy_batch(p, a) __rtl_writephy_batch(p, a, ARRAY_SIZE(a))
81
82static void rtl8168f_config_eee_phy(struct phy_device *phydev)
83{
84 r8168d_modify_extpage(phydev, extpage: 0x0020, reg: 0x15, mask: 0, BIT(8));
85 r8168d_phy_param(phydev, parm: 0x8b85, mask: 0, BIT(13));
86}
87
88static void rtl8168g_config_eee_phy(struct phy_device *phydev)
89{
90 phy_modify_paged(phydev, page: 0x0a43, regnum: 0x11, mask: 0, BIT(4));
91}
92
93static void rtl8168h_config_eee_phy(struct phy_device *phydev)
94{
95 rtl8168g_config_eee_phy(phydev);
96
97 phy_modify_paged(phydev, page: 0xa4a, regnum: 0x11, mask: 0x0000, set: 0x0200);
98 phy_modify_paged(phydev, page: 0xa42, regnum: 0x14, mask: 0x0000, set: 0x0080);
99}
100
101static void rtl8125_common_config_eee_phy(struct phy_device *phydev)
102{
103 phy_modify_paged(phydev, page: 0xa6d, regnum: 0x14, mask: 0x0010, set: 0x0000);
104 phy_modify_paged(phydev, page: 0xa42, regnum: 0x14, mask: 0x0080, set: 0x0000);
105 phy_modify_paged(phydev, page: 0xa4a, regnum: 0x11, mask: 0x0200, set: 0x0000);
106}
107
108static void rtl8125_config_eee_phy(struct phy_device *phydev)
109{
110 rtl8168g_config_eee_phy(phydev);
111 rtl8125_common_config_eee_phy(phydev);
112}
113
114static void rtl8169s_hw_phy_config(struct rtl8169_private *tp,
115 struct phy_device *phydev)
116{
117 static const struct phy_reg phy_reg_init[] = {
118 { 0x1f, 0x0001 },
119 { 0x06, 0x006e },
120 { 0x08, 0x0708 },
121 { 0x15, 0x4000 },
122 { 0x18, 0x65c7 },
123
124 { 0x1f, 0x0001 },
125 { 0x03, 0x00a1 },
126 { 0x02, 0x0008 },
127 { 0x01, 0x0120 },
128 { 0x00, 0x1000 },
129 { 0x04, 0x0800 },
130 { 0x04, 0x0000 },
131
132 { 0x03, 0xff41 },
133 { 0x02, 0xdf60 },
134 { 0x01, 0x0140 },
135 { 0x00, 0x0077 },
136 { 0x04, 0x7800 },
137 { 0x04, 0x7000 },
138
139 { 0x03, 0x802f },
140 { 0x02, 0x4f02 },
141 { 0x01, 0x0409 },
142 { 0x00, 0xf0f9 },
143 { 0x04, 0x9800 },
144 { 0x04, 0x9000 },
145
146 { 0x03, 0xdf01 },
147 { 0x02, 0xdf20 },
148 { 0x01, 0xff95 },
149 { 0x00, 0xba00 },
150 { 0x04, 0xa800 },
151 { 0x04, 0xa000 },
152
153 { 0x03, 0xff41 },
154 { 0x02, 0xdf20 },
155 { 0x01, 0x0140 },
156 { 0x00, 0x00bb },
157 { 0x04, 0xb800 },
158 { 0x04, 0xb000 },
159
160 { 0x03, 0xdf41 },
161 { 0x02, 0xdc60 },
162 { 0x01, 0x6340 },
163 { 0x00, 0x007d },
164 { 0x04, 0xd800 },
165 { 0x04, 0xd000 },
166
167 { 0x03, 0xdf01 },
168 { 0x02, 0xdf20 },
169 { 0x01, 0x100a },
170 { 0x00, 0xa0ff },
171 { 0x04, 0xf800 },
172 { 0x04, 0xf000 },
173
174 { 0x1f, 0x0000 },
175 { 0x0b, 0x0000 },
176 { 0x00, 0x9200 }
177 };
178
179 rtl_writephy_batch(phydev, phy_reg_init);
180}
181
182static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp,
183 struct phy_device *phydev)
184{
185 phy_write_paged(phydev, page: 0x0002, regnum: 0x01, val: 0x90d0);
186}
187
188static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
189 struct phy_device *phydev)
190{
191 static const struct phy_reg phy_reg_init[] = {
192 { 0x1f, 0x0001 },
193 { 0x04, 0x0000 },
194 { 0x03, 0x00a1 },
195 { 0x02, 0x0008 },
196 { 0x01, 0x0120 },
197 { 0x00, 0x1000 },
198 { 0x04, 0x0800 },
199 { 0x04, 0x9000 },
200 { 0x03, 0x802f },
201 { 0x02, 0x4f02 },
202 { 0x01, 0x0409 },
203 { 0x00, 0xf099 },
204 { 0x04, 0x9800 },
205 { 0x04, 0xa000 },
206 { 0x03, 0xdf01 },
207 { 0x02, 0xdf20 },
208 { 0x01, 0xff95 },
209 { 0x00, 0xba00 },
210 { 0x04, 0xa800 },
211 { 0x04, 0xf000 },
212 { 0x03, 0xdf01 },
213 { 0x02, 0xdf20 },
214 { 0x01, 0x101a },
215 { 0x00, 0xa0ff },
216 { 0x04, 0xf800 },
217 { 0x04, 0x0000 },
218 { 0x1f, 0x0000 },
219
220 { 0x1f, 0x0001 },
221 { 0x10, 0xf41b },
222 { 0x14, 0xfb54 },
223 { 0x18, 0xf5c7 },
224 { 0x1f, 0x0000 },
225
226 { 0x1f, 0x0001 },
227 { 0x17, 0x0cc0 },
228 { 0x1f, 0x0000 }
229 };
230
231 rtl_writephy_batch(phydev, phy_reg_init);
232}
233
234static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp,
235 struct phy_device *phydev)
236{
237 static const struct phy_reg phy_reg_init[] = {
238 { 0x1f, 0x0001 },
239 { 0x04, 0x0000 },
240 { 0x03, 0x00a1 },
241 { 0x02, 0x0008 },
242 { 0x01, 0x0120 },
243 { 0x00, 0x1000 },
244 { 0x04, 0x0800 },
245 { 0x04, 0x9000 },
246 { 0x03, 0x802f },
247 { 0x02, 0x4f02 },
248 { 0x01, 0x0409 },
249 { 0x00, 0xf099 },
250 { 0x04, 0x9800 },
251 { 0x04, 0xa000 },
252 { 0x03, 0xdf01 },
253 { 0x02, 0xdf20 },
254 { 0x01, 0xff95 },
255 { 0x00, 0xba00 },
256 { 0x04, 0xa800 },
257 { 0x04, 0xf000 },
258 { 0x03, 0xdf01 },
259 { 0x02, 0xdf20 },
260 { 0x01, 0x101a },
261 { 0x00, 0xa0ff },
262 { 0x04, 0xf800 },
263 { 0x04, 0x0000 },
264 { 0x1f, 0x0000 },
265
266 { 0x1f, 0x0001 },
267 { 0x0b, 0x8480 },
268 { 0x1f, 0x0000 },
269
270 { 0x1f, 0x0001 },
271 { 0x18, 0x67c7 },
272 { 0x04, 0x2000 },
273 { 0x03, 0x002f },
274 { 0x02, 0x4360 },
275 { 0x01, 0x0109 },
276 { 0x00, 0x3022 },
277 { 0x04, 0x2800 },
278 { 0x1f, 0x0000 },
279
280 { 0x1f, 0x0001 },
281 { 0x17, 0x0cc0 },
282 { 0x1f, 0x0000 }
283 };
284
285 rtl_writephy_batch(phydev, phy_reg_init);
286}
287
288static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp,
289 struct phy_device *phydev)
290{
291 phy_write_paged(phydev, page: 0x0001, regnum: 0x10, val: 0xf41b);
292}
293
294static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp,
295 struct phy_device *phydev)
296{
297 phy_write(phydev, regnum: 0x1d, val: 0x0f00);
298 phy_write_paged(phydev, page: 0x0002, regnum: 0x0c, val: 0x1ec8);
299}
300
301static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp,
302 struct phy_device *phydev)
303{
304 phy_set_bits(phydev, regnum: 0x14, BIT(5));
305 phy_set_bits(phydev, regnum: 0x0d, BIT(5));
306 phy_write_paged(phydev, page: 0x0001, regnum: 0x1d, val: 0x3d98);
307}
308
309static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp,
310 struct phy_device *phydev)
311{
312 static const struct phy_reg phy_reg_init[] = {
313 { 0x1f, 0x0001 },
314 { 0x12, 0x2300 },
315 { 0x1f, 0x0002 },
316 { 0x00, 0x88d4 },
317 { 0x01, 0x82b1 },
318 { 0x03, 0x7002 },
319 { 0x08, 0x9e30 },
320 { 0x09, 0x01f0 },
321 { 0x0a, 0x5500 },
322 { 0x0c, 0x00c8 },
323 { 0x1f, 0x0003 },
324 { 0x12, 0xc096 },
325 { 0x16, 0x000a },
326 { 0x1f, 0x0000 },
327 { 0x1f, 0x0000 },
328 { 0x09, 0x2000 },
329 { 0x09, 0x0000 }
330 };
331
332 rtl_writephy_batch(phydev, phy_reg_init);
333
334 phy_set_bits(phydev, regnum: 0x14, BIT(5));
335 phy_set_bits(phydev, regnum: 0x0d, BIT(5));
336}
337
338static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp,
339 struct phy_device *phydev)
340{
341 static const struct phy_reg phy_reg_init[] = {
342 { 0x1f, 0x0001 },
343 { 0x12, 0x2300 },
344 { 0x03, 0x802f },
345 { 0x02, 0x4f02 },
346 { 0x01, 0x0409 },
347 { 0x00, 0xf099 },
348 { 0x04, 0x9800 },
349 { 0x04, 0x9000 },
350 { 0x1d, 0x3d98 },
351 { 0x1f, 0x0002 },
352 { 0x0c, 0x7eb8 },
353 { 0x06, 0x0761 },
354 { 0x1f, 0x0003 },
355 { 0x16, 0x0f0a },
356 { 0x1f, 0x0000 }
357 };
358
359 rtl_writephy_batch(phydev, phy_reg_init);
360
361 phy_set_bits(phydev, regnum: 0x16, BIT(0));
362 phy_set_bits(phydev, regnum: 0x14, BIT(5));
363 phy_set_bits(phydev, regnum: 0x0d, BIT(5));
364}
365
366static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp,
367 struct phy_device *phydev)
368{
369 static const struct phy_reg phy_reg_init[] = {
370 { 0x1f, 0x0001 },
371 { 0x12, 0x2300 },
372 { 0x1d, 0x3d98 },
373 { 0x1f, 0x0002 },
374 { 0x0c, 0x7eb8 },
375 { 0x06, 0x5461 },
376 { 0x1f, 0x0003 },
377 { 0x16, 0x0f0a },
378 { 0x1f, 0x0000 }
379 };
380
381 rtl_writephy_batch(phydev, phy_reg_init);
382
383 phy_set_bits(phydev, regnum: 0x16, BIT(0));
384 phy_set_bits(phydev, regnum: 0x14, BIT(5));
385 phy_set_bits(phydev, regnum: 0x0d, BIT(5));
386}
387
388static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
389 /* Channel Estimation */
390 { 0x1f, 0x0001 },
391 { 0x06, 0x4064 },
392 { 0x07, 0x2863 },
393 { 0x08, 0x059c },
394 { 0x09, 0x26b4 },
395 { 0x0a, 0x6a19 },
396 { 0x0b, 0xdcc8 },
397 { 0x10, 0xf06d },
398 { 0x14, 0x7f68 },
399 { 0x18, 0x7fd9 },
400 { 0x1c, 0xf0ff },
401 { 0x1d, 0x3d9c },
402 { 0x1f, 0x0003 },
403 { 0x12, 0xf49f },
404 { 0x13, 0x070b },
405 { 0x1a, 0x05ad },
406 { 0x14, 0x94c0 },
407
408 /*
409 * Tx Error Issue
410 * Enhance line driver power
411 */
412 { 0x1f, 0x0002 },
413 { 0x06, 0x5561 },
414 { 0x1f, 0x0005 },
415 { 0x05, 0x8332 },
416 { 0x06, 0x5561 },
417
418 /*
419 * Can not link to 1Gbps with bad cable
420 * Decrease SNR threshold form 21.07dB to 19.04dB
421 */
422 { 0x1f, 0x0001 },
423 { 0x17, 0x0cc0 },
424
425 { 0x1f, 0x0000 },
426 { 0x0d, 0xf880 }
427};
428
429static void rtl8168d_apply_firmware_cond(struct rtl8169_private *tp,
430 struct phy_device *phydev,
431 u16 val)
432{
433 u16 reg_val;
434
435 phy_write(phydev, regnum: 0x1f, val: 0x0005);
436 phy_write(phydev, regnum: 0x05, val: 0x001b);
437 reg_val = phy_read(phydev, regnum: 0x06);
438 phy_write(phydev, regnum: 0x1f, val: 0x0000);
439
440 if (reg_val != val)
441 phydev_warn(phydev, "chipset not ready for firmware\n");
442 else
443 r8169_apply_firmware(tp);
444}
445
446static void rtl8168d_1_common(struct phy_device *phydev)
447{
448 u16 val;
449
450 phy_write_paged(phydev, page: 0x0002, regnum: 0x05, val: 0x669a);
451 r8168d_phy_param(phydev, parm: 0x8330, mask: 0xffff, val: 0x669a);
452 phy_write(phydev, regnum: 0x1f, val: 0x0002);
453
454 val = phy_read(phydev, regnum: 0x0d);
455
456 if ((val & 0x00ff) != 0x006c) {
457 static const u16 set[] = {
458 0x0065, 0x0066, 0x0067, 0x0068,
459 0x0069, 0x006a, 0x006b, 0x006c
460 };
461 int i;
462
463 val &= 0xff00;
464 for (i = 0; i < ARRAY_SIZE(set); i++)
465 phy_write(phydev, regnum: 0x0d, val: val | set[i]);
466 }
467}
468
469static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp,
470 struct phy_device *phydev)
471{
472 rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0);
473
474 /*
475 * Rx Error Issue
476 * Fine Tune Switching regulator parameter
477 */
478 phy_write(phydev, regnum: 0x1f, val: 0x0002);
479 phy_modify(phydev, regnum: 0x0b, mask: 0x00ef, set: 0x0010);
480 phy_modify(phydev, regnum: 0x0c, mask: 0x5d00, set: 0xa200);
481
482 if (rtl8168d_efuse_read(tp, reg_addr: 0x01) == 0xb1) {
483 rtl8168d_1_common(phydev);
484 } else {
485 phy_write_paged(phydev, page: 0x0002, regnum: 0x05, val: 0x6662);
486 r8168d_phy_param(phydev, parm: 0x8330, mask: 0xffff, val: 0x6662);
487 }
488
489 /* RSET couple improve */
490 phy_write(phydev, regnum: 0x1f, val: 0x0002);
491 phy_set_bits(phydev, regnum: 0x0d, val: 0x0300);
492 phy_set_bits(phydev, regnum: 0x0f, val: 0x0010);
493
494 /* Fine tune PLL performance */
495 phy_write(phydev, regnum: 0x1f, val: 0x0002);
496 phy_modify(phydev, regnum: 0x02, mask: 0x0600, set: 0x0100);
497 phy_clear_bits(phydev, regnum: 0x03, val: 0xe000);
498 phy_write(phydev, regnum: 0x1f, val: 0x0000);
499
500 rtl8168d_apply_firmware_cond(tp, phydev, val: 0xbf00);
501}
502
503static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp,
504 struct phy_device *phydev)
505{
506 rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0);
507
508 if (rtl8168d_efuse_read(tp, reg_addr: 0x01) == 0xb1) {
509 rtl8168d_1_common(phydev);
510 } else {
511 phy_write_paged(phydev, page: 0x0002, regnum: 0x05, val: 0x2642);
512 r8168d_phy_param(phydev, parm: 0x8330, mask: 0xffff, val: 0x2642);
513 }
514
515 /* Fine tune PLL performance */
516 phy_write(phydev, regnum: 0x1f, val: 0x0002);
517 phy_modify(phydev, regnum: 0x02, mask: 0x0600, set: 0x0100);
518 phy_clear_bits(phydev, regnum: 0x03, val: 0xe000);
519 phy_write(phydev, regnum: 0x1f, val: 0x0000);
520
521 /* Switching regulator Slew rate */
522 phy_modify_paged(phydev, page: 0x0002, regnum: 0x0f, mask: 0x0000, set: 0x0017);
523
524 rtl8168d_apply_firmware_cond(tp, phydev, val: 0xb300);
525}
526
527static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp,
528 struct phy_device *phydev)
529{
530 phy_write_paged(phydev, page: 0x0001, regnum: 0x17, val: 0x0cc0);
531 r8168d_modify_extpage(phydev, extpage: 0x002d, reg: 0x18, mask: 0xffff, val: 0x0040);
532 phy_set_bits(phydev, regnum: 0x0d, BIT(5));
533}
534
535static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp,
536 struct phy_device *phydev)
537{
538 static const struct phy_reg phy_reg_init[] = {
539 /* Channel estimation fine tune */
540 { 0x1f, 0x0001 },
541 { 0x0b, 0x6c20 },
542 { 0x07, 0x2872 },
543 { 0x1c, 0xefff },
544 { 0x1f, 0x0003 },
545 { 0x14, 0x6420 },
546 { 0x1f, 0x0000 },
547 };
548
549 r8169_apply_firmware(tp);
550
551 /* Enable Delay cap */
552 r8168d_phy_param(phydev, parm: 0x8b80, mask: 0xffff, val: 0xc896);
553
554 rtl_writephy_batch(phydev, phy_reg_init);
555
556 /* Update PFM & 10M TX idle timer */
557 r8168d_modify_extpage(phydev, extpage: 0x002f, reg: 0x15, mask: 0xffff, val: 0x1919);
558
559 r8168d_modify_extpage(phydev, extpage: 0x00ac, reg: 0x18, mask: 0xffff, val: 0x0006);
560
561 /* DCO enable for 10M IDLE Power */
562 r8168d_modify_extpage(phydev, extpage: 0x0023, reg: 0x17, mask: 0x0000, val: 0x0006);
563
564 /* For impedance matching */
565 phy_modify_paged(phydev, page: 0x0002, regnum: 0x08, mask: 0x7f00, set: 0x8000);
566
567 /* PHY auto speed down */
568 r8168d_modify_extpage(phydev, extpage: 0x002d, reg: 0x18, mask: 0x0000, val: 0x0050);
569 phy_set_bits(phydev, regnum: 0x14, BIT(15));
570
571 r8168d_phy_param(phydev, parm: 0x8b86, mask: 0x0000, val: 0x0001);
572 r8168d_phy_param(phydev, parm: 0x8b85, mask: 0x2000, val: 0x0000);
573
574 r8168d_modify_extpage(phydev, extpage: 0x0020, reg: 0x15, mask: 0x1100, val: 0x0000);
575 phy_write_paged(phydev, page: 0x0006, regnum: 0x00, val: 0x5a00);
576
577 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val: 0x0000);
578}
579
580static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp,
581 struct phy_device *phydev)
582{
583 r8169_apply_firmware(tp);
584
585 /* Enable Delay cap */
586 r8168d_modify_extpage(phydev, extpage: 0x00ac, reg: 0x18, mask: 0xffff, val: 0x0006);
587
588 /* Channel estimation fine tune */
589 phy_write_paged(phydev, page: 0x0003, regnum: 0x09, val: 0xa20f);
590
591 /* Green Setting */
592 r8168d_phy_param(phydev, parm: 0x8b5b, mask: 0xffff, val: 0x9222);
593 r8168d_phy_param(phydev, parm: 0x8b6d, mask: 0xffff, val: 0x8000);
594 r8168d_phy_param(phydev, parm: 0x8b76, mask: 0xffff, val: 0x8000);
595
596 /* For 4-corner performance improve */
597 phy_write(phydev, regnum: 0x1f, val: 0x0005);
598 phy_write(phydev, regnum: 0x05, val: 0x8b80);
599 phy_set_bits(phydev, regnum: 0x17, val: 0x0006);
600 phy_write(phydev, regnum: 0x1f, val: 0x0000);
601
602 /* PHY auto speed down */
603 r8168d_modify_extpage(phydev, extpage: 0x002d, reg: 0x18, mask: 0x0000, val: 0x0010);
604 phy_set_bits(phydev, regnum: 0x14, BIT(15));
605
606 /* improve 10M EEE waveform */
607 r8168d_phy_param(phydev, parm: 0x8b86, mask: 0x0000, val: 0x0001);
608
609 /* Improve 2-pair detection performance */
610 r8168d_phy_param(phydev, parm: 0x8b85, mask: 0x0000, val: 0x4000);
611
612 rtl8168f_config_eee_phy(phydev);
613
614 /* Green feature */
615 phy_write(phydev, regnum: 0x1f, val: 0x0003);
616 phy_set_bits(phydev, regnum: 0x19, BIT(0));
617 phy_set_bits(phydev, regnum: 0x10, BIT(10));
618 phy_write(phydev, regnum: 0x1f, val: 0x0000);
619 phy_modify_paged(phydev, page: 0x0005, regnum: 0x01, mask: 0, BIT(8));
620}
621
622static void rtl8168f_hw_phy_config(struct rtl8169_private *tp,
623 struct phy_device *phydev)
624{
625 /* For 4-corner performance improve */
626 r8168d_phy_param(phydev, parm: 0x8b80, mask: 0x0000, val: 0x0006);
627
628 /* PHY auto speed down */
629 r8168d_modify_extpage(phydev, extpage: 0x002d, reg: 0x18, mask: 0x0000, val: 0x0010);
630 phy_set_bits(phydev, regnum: 0x14, BIT(15));
631
632 /* Improve 10M EEE waveform */
633 r8168d_phy_param(phydev, parm: 0x8b86, mask: 0x0000, val: 0x0001);
634
635 rtl8168f_config_eee_phy(phydev);
636}
637
638static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp,
639 struct phy_device *phydev)
640{
641 r8169_apply_firmware(tp);
642
643 /* Channel estimation fine tune */
644 phy_write_paged(phydev, page: 0x0003, regnum: 0x09, val: 0xa20f);
645
646 /* Modify green table for giga & fnet */
647 r8168d_phy_param(phydev, parm: 0x8b55, mask: 0xffff, val: 0x0000);
648 r8168d_phy_param(phydev, parm: 0x8b5e, mask: 0xffff, val: 0x0000);
649 r8168d_phy_param(phydev, parm: 0x8b67, mask: 0xffff, val: 0x0000);
650 r8168d_phy_param(phydev, parm: 0x8b70, mask: 0xffff, val: 0x0000);
651 r8168d_modify_extpage(phydev, extpage: 0x0078, reg: 0x17, mask: 0xffff, val: 0x0000);
652 r8168d_modify_extpage(phydev, extpage: 0x0078, reg: 0x19, mask: 0xffff, val: 0x00fb);
653
654 /* Modify green table for 10M */
655 r8168d_phy_param(phydev, parm: 0x8b79, mask: 0xffff, val: 0xaa00);
656
657 /* Disable hiimpedance detection (RTCT) */
658 phy_write_paged(phydev, page: 0x0003, regnum: 0x01, val: 0x328a);
659
660 rtl8168f_hw_phy_config(tp, phydev);
661
662 /* Improve 2-pair detection performance */
663 r8168d_phy_param(phydev, parm: 0x8b85, mask: 0x0000, val: 0x4000);
664}
665
666static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp,
667 struct phy_device *phydev)
668{
669 r8169_apply_firmware(tp);
670
671 rtl8168f_hw_phy_config(tp, phydev);
672}
673
674static void rtl8411_hw_phy_config(struct rtl8169_private *tp,
675 struct phy_device *phydev)
676{
677 r8169_apply_firmware(tp);
678
679 rtl8168f_hw_phy_config(tp, phydev);
680
681 /* Improve 2-pair detection performance */
682 r8168d_phy_param(phydev, parm: 0x8b85, mask: 0x0000, val: 0x4000);
683
684 /* Channel estimation fine tune */
685 phy_write_paged(phydev, page: 0x0003, regnum: 0x09, val: 0xa20f);
686
687 /* Modify green table for giga & fnet */
688 r8168d_phy_param(phydev, parm: 0x8b55, mask: 0xffff, val: 0x0000);
689 r8168d_phy_param(phydev, parm: 0x8b5e, mask: 0xffff, val: 0x0000);
690 r8168d_phy_param(phydev, parm: 0x8b67, mask: 0xffff, val: 0x0000);
691 r8168d_phy_param(phydev, parm: 0x8b70, mask: 0xffff, val: 0x0000);
692 r8168d_modify_extpage(phydev, extpage: 0x0078, reg: 0x17, mask: 0xffff, val: 0x0000);
693 r8168d_modify_extpage(phydev, extpage: 0x0078, reg: 0x19, mask: 0xffff, val: 0x00aa);
694
695 /* Modify green table for 10M */
696 r8168d_phy_param(phydev, parm: 0x8b79, mask: 0xffff, val: 0xaa00);
697
698 /* Disable hiimpedance detection (RTCT) */
699 phy_write_paged(phydev, page: 0x0003, regnum: 0x01, val: 0x328a);
700
701 /* Modify green table for giga */
702 r8168d_phy_param(phydev, parm: 0x8b54, mask: 0x0800, val: 0x0000);
703 r8168d_phy_param(phydev, parm: 0x8b5d, mask: 0x0800, val: 0x0000);
704 r8168d_phy_param(phydev, parm: 0x8a7c, mask: 0x0100, val: 0x0000);
705 r8168d_phy_param(phydev, parm: 0x8a7f, mask: 0x0000, val: 0x0100);
706 r8168d_phy_param(phydev, parm: 0x8a82, mask: 0x0100, val: 0x0000);
707 r8168d_phy_param(phydev, parm: 0x8a85, mask: 0x0100, val: 0x0000);
708 r8168d_phy_param(phydev, parm: 0x8a88, mask: 0x0100, val: 0x0000);
709
710 /* uc same-seed solution */
711 r8168d_phy_param(phydev, parm: 0x8b85, mask: 0x0000, val: 0x8000);
712
713 /* Green feature */
714 phy_write(phydev, regnum: 0x1f, val: 0x0003);
715 phy_clear_bits(phydev, regnum: 0x19, BIT(0));
716 phy_clear_bits(phydev, regnum: 0x10, BIT(10));
717 phy_write(phydev, regnum: 0x1f, val: 0x0000);
718}
719
720static void rtl8168g_disable_aldps(struct phy_device *phydev)
721{
722 phy_modify_paged(phydev, page: 0x0a43, regnum: 0x10, BIT(2), set: 0);
723}
724
725static void rtl8168g_enable_gphy_10m(struct phy_device *phydev)
726{
727 phy_modify_paged(phydev, page: 0x0a44, regnum: 0x11, mask: 0, BIT(11));
728}
729
730static void rtl8168g_phy_adjust_10m_aldps(struct phy_device *phydev)
731{
732 phy_modify_paged(phydev, page: 0x0bcc, regnum: 0x14, BIT(8), set: 0);
733 phy_modify_paged(phydev, page: 0x0a44, regnum: 0x11, mask: 0, BIT(7) | BIT(6));
734 r8168g_phy_param(phydev, parm: 0x8084, mask: 0x6000, val: 0x0000);
735 phy_modify_paged(phydev, page: 0x0a43, regnum: 0x10, mask: 0x0000, set: 0x1003);
736}
737
738static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp,
739 struct phy_device *phydev)
740{
741 int ret;
742
743 r8169_apply_firmware(tp);
744
745 ret = phy_read_paged(phydev, page: 0x0a46, regnum: 0x10);
746 if (ret & BIT(8))
747 phy_modify_paged(phydev, page: 0x0bcc, regnum: 0x12, BIT(15), set: 0);
748 else
749 phy_modify_paged(phydev, page: 0x0bcc, regnum: 0x12, mask: 0, BIT(15));
750
751 ret = phy_read_paged(phydev, page: 0x0a46, regnum: 0x13);
752 if (ret & BIT(8))
753 phy_modify_paged(phydev, page: 0x0c41, regnum: 0x15, mask: 0, BIT(1));
754 else
755 phy_modify_paged(phydev, page: 0x0c41, regnum: 0x15, BIT(1), set: 0);
756
757 /* Enable PHY auto speed down */
758 phy_modify_paged(phydev, page: 0x0a44, regnum: 0x11, mask: 0, BIT(3) | BIT(2));
759
760 rtl8168g_phy_adjust_10m_aldps(phydev);
761
762 /* EEE auto-fallback function */
763 phy_modify_paged(phydev, page: 0x0a4b, regnum: 0x11, mask: 0, BIT(2));
764
765 /* Enable UC LPF tune function */
766 r8168g_phy_param(phydev, parm: 0x8012, mask: 0x0000, val: 0x8000);
767
768 phy_modify_paged(phydev, page: 0x0c42, regnum: 0x11, BIT(13), BIT(14));
769
770 /* Improve SWR Efficiency */
771 phy_write(phydev, regnum: 0x1f, val: 0x0bcd);
772 phy_write(phydev, regnum: 0x14, val: 0x5065);
773 phy_write(phydev, regnum: 0x14, val: 0xd065);
774 phy_write(phydev, regnum: 0x1f, val: 0x0bc8);
775 phy_write(phydev, regnum: 0x11, val: 0x5655);
776 phy_write(phydev, regnum: 0x1f, val: 0x0bcd);
777 phy_write(phydev, regnum: 0x14, val: 0x1065);
778 phy_write(phydev, regnum: 0x14, val: 0x9065);
779 phy_write(phydev, regnum: 0x14, val: 0x1065);
780 phy_write(phydev, regnum: 0x1f, val: 0x0000);
781
782 rtl8168g_disable_aldps(phydev);
783 rtl8168g_config_eee_phy(phydev);
784}
785
786static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp,
787 struct phy_device *phydev)
788{
789 r8169_apply_firmware(tp);
790 rtl8168g_config_eee_phy(phydev);
791}
792
793static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp,
794 struct phy_device *phydev)
795{
796 u16 ioffset, rlen;
797 u32 data;
798
799 r8169_apply_firmware(tp);
800
801 /* CHIN EST parameter update */
802 r8168g_phy_param(phydev, parm: 0x808a, mask: 0x003f, val: 0x000a);
803
804 /* enable R-tune & PGA-retune function */
805 r8168g_phy_param(phydev, parm: 0x0811, mask: 0x0000, val: 0x0800);
806 phy_modify_paged(phydev, page: 0x0a42, regnum: 0x16, mask: 0x0000, set: 0x0002);
807
808 rtl8168g_enable_gphy_10m(phydev);
809
810 ioffset = rtl8168h_2_get_adc_bias_ioffset(tp);
811 if (ioffset != 0xffff)
812 phy_write_paged(phydev, page: 0x0bcf, regnum: 0x16, val: ioffset);
813
814 /* Modify rlen (TX LPF corner frequency) level */
815 data = phy_read_paged(phydev, page: 0x0bcd, regnum: 0x16);
816 data &= 0x000f;
817 rlen = 0;
818 if (data > 3)
819 rlen = data - 3;
820 data = rlen | (rlen << 4) | (rlen << 8) | (rlen << 12);
821 phy_write_paged(phydev, page: 0x0bcd, regnum: 0x17, val: data);
822
823 /* disable phy pfm mode */
824 phy_modify_paged(phydev, page: 0x0a44, regnum: 0x11, BIT(7), set: 0);
825
826 /* disable 10m pll off */
827 phy_modify_paged(phydev, page: 0x0a43, regnum: 0x10, BIT(0), set: 0);
828
829 rtl8168g_disable_aldps(phydev);
830 rtl8168g_config_eee_phy(phydev);
831}
832
833static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp,
834 struct phy_device *phydev)
835{
836 rtl8168g_phy_adjust_10m_aldps(phydev);
837
838 /* Enable UC LPF tune function */
839 r8168g_phy_param(phydev, parm: 0x8012, mask: 0x0000, val: 0x8000);
840
841 /* Set rg_sel_sdm_rate */
842 phy_modify_paged(phydev, page: 0x0c42, regnum: 0x11, BIT(13), BIT(14));
843
844 /* Channel estimation parameters */
845 r8168g_phy_param(phydev, parm: 0x80f3, mask: 0xff00, val: 0x8b00);
846 r8168g_phy_param(phydev, parm: 0x80f0, mask: 0xff00, val: 0x3a00);
847 r8168g_phy_param(phydev, parm: 0x80ef, mask: 0xff00, val: 0x0500);
848 r8168g_phy_param(phydev, parm: 0x80f6, mask: 0xff00, val: 0x6e00);
849 r8168g_phy_param(phydev, parm: 0x80ec, mask: 0xff00, val: 0x6800);
850 r8168g_phy_param(phydev, parm: 0x80ed, mask: 0xff00, val: 0x7c00);
851 r8168g_phy_param(phydev, parm: 0x80f2, mask: 0xff00, val: 0xf400);
852 r8168g_phy_param(phydev, parm: 0x80f4, mask: 0xff00, val: 0x8500);
853 r8168g_phy_param(phydev, parm: 0x8110, mask: 0xff00, val: 0xa800);
854 r8168g_phy_param(phydev, parm: 0x810f, mask: 0xff00, val: 0x1d00);
855 r8168g_phy_param(phydev, parm: 0x8111, mask: 0xff00, val: 0xf500);
856 r8168g_phy_param(phydev, parm: 0x8113, mask: 0xff00, val: 0x6100);
857 r8168g_phy_param(phydev, parm: 0x8115, mask: 0xff00, val: 0x9200);
858 r8168g_phy_param(phydev, parm: 0x810e, mask: 0xff00, val: 0x0400);
859 r8168g_phy_param(phydev, parm: 0x810c, mask: 0xff00, val: 0x7c00);
860 r8168g_phy_param(phydev, parm: 0x810b, mask: 0xff00, val: 0x5a00);
861 r8168g_phy_param(phydev, parm: 0x80d1, mask: 0xff00, val: 0xff00);
862 r8168g_phy_param(phydev, parm: 0x80cd, mask: 0xff00, val: 0x9e00);
863 r8168g_phy_param(phydev, parm: 0x80d3, mask: 0xff00, val: 0x0e00);
864 r8168g_phy_param(phydev, parm: 0x80d5, mask: 0xff00, val: 0xca00);
865 r8168g_phy_param(phydev, parm: 0x80d7, mask: 0xff00, val: 0x8400);
866
867 /* Force PWM-mode */
868 phy_write(phydev, regnum: 0x1f, val: 0x0bcd);
869 phy_write(phydev, regnum: 0x14, val: 0x5065);
870 phy_write(phydev, regnum: 0x14, val: 0xd065);
871 phy_write(phydev, regnum: 0x1f, val: 0x0bc8);
872 phy_write(phydev, regnum: 0x12, val: 0x00ed);
873 phy_write(phydev, regnum: 0x1f, val: 0x0bcd);
874 phy_write(phydev, regnum: 0x14, val: 0x1065);
875 phy_write(phydev, regnum: 0x14, val: 0x9065);
876 phy_write(phydev, regnum: 0x14, val: 0x1065);
877 phy_write(phydev, regnum: 0x1f, val: 0x0000);
878
879 rtl8168g_disable_aldps(phydev);
880 rtl8168g_config_eee_phy(phydev);
881}
882
883static void rtl8117_hw_phy_config(struct rtl8169_private *tp,
884 struct phy_device *phydev)
885{
886 /* CHN EST parameters adjust - fnet */
887 r8168g_phy_param(phydev, parm: 0x808e, mask: 0xff00, val: 0x4800);
888 r8168g_phy_param(phydev, parm: 0x8090, mask: 0xff00, val: 0xcc00);
889 r8168g_phy_param(phydev, parm: 0x8092, mask: 0xff00, val: 0xb000);
890
891 r8168g_phy_param(phydev, parm: 0x8088, mask: 0xff00, val: 0x6000);
892 r8168g_phy_param(phydev, parm: 0x808b, mask: 0x3f00, val: 0x0b00);
893 r8168g_phy_param(phydev, parm: 0x808d, mask: 0x1f00, val: 0x0600);
894 r8168g_phy_param(phydev, parm: 0x808c, mask: 0xff00, val: 0xb000);
895 r8168g_phy_param(phydev, parm: 0x80a0, mask: 0xff00, val: 0x2800);
896 r8168g_phy_param(phydev, parm: 0x80a2, mask: 0xff00, val: 0x5000);
897 r8168g_phy_param(phydev, parm: 0x809b, mask: 0xf800, val: 0xb000);
898 r8168g_phy_param(phydev, parm: 0x809a, mask: 0xff00, val: 0x4b00);
899 r8168g_phy_param(phydev, parm: 0x809d, mask: 0x3f00, val: 0x0800);
900 r8168g_phy_param(phydev, parm: 0x80a1, mask: 0xff00, val: 0x7000);
901 r8168g_phy_param(phydev, parm: 0x809f, mask: 0x1f00, val: 0x0300);
902 r8168g_phy_param(phydev, parm: 0x809e, mask: 0xff00, val: 0x8800);
903 r8168g_phy_param(phydev, parm: 0x80b2, mask: 0xff00, val: 0x2200);
904 r8168g_phy_param(phydev, parm: 0x80ad, mask: 0xf800, val: 0x9800);
905 r8168g_phy_param(phydev, parm: 0x80af, mask: 0x3f00, val: 0x0800);
906 r8168g_phy_param(phydev, parm: 0x80b3, mask: 0xff00, val: 0x6f00);
907 r8168g_phy_param(phydev, parm: 0x80b1, mask: 0x1f00, val: 0x0300);
908 r8168g_phy_param(phydev, parm: 0x80b0, mask: 0xff00, val: 0x9300);
909
910 r8168g_phy_param(phydev, parm: 0x8011, mask: 0x0000, val: 0x0800);
911
912 rtl8168g_enable_gphy_10m(phydev);
913
914 r8168g_phy_param(phydev, parm: 0x8016, mask: 0x0000, val: 0x0400);
915
916 rtl8168g_disable_aldps(phydev);
917 rtl8168h_config_eee_phy(phydev);
918}
919
920static void rtl8102e_hw_phy_config(struct rtl8169_private *tp,
921 struct phy_device *phydev)
922{
923 static const struct phy_reg phy_reg_init[] = {
924 { 0x1f, 0x0003 },
925 { 0x08, 0x441d },
926 { 0x01, 0x9100 },
927 { 0x1f, 0x0000 }
928 };
929
930 phy_set_bits(phydev, regnum: 0x11, BIT(12));
931 phy_set_bits(phydev, regnum: 0x19, BIT(13));
932 phy_set_bits(phydev, regnum: 0x10, BIT(15));
933
934 rtl_writephy_batch(phydev, phy_reg_init);
935}
936
937static void rtl8401_hw_phy_config(struct rtl8169_private *tp,
938 struct phy_device *phydev)
939{
940 phy_set_bits(phydev, regnum: 0x11, BIT(12));
941 phy_modify_paged(phydev, page: 0x0002, regnum: 0x0f, mask: 0x0000, set: 0x0003);
942}
943
944static void rtl8105e_hw_phy_config(struct rtl8169_private *tp,
945 struct phy_device *phydev)
946{
947 /* Disable ALDPS before ram code */
948 phy_write(phydev, regnum: 0x18, val: 0x0310);
949 msleep(msecs: 100);
950
951 r8169_apply_firmware(tp);
952
953 phy_write_paged(phydev, page: 0x0005, regnum: 0x1a, val: 0x0000);
954 phy_write_paged(phydev, page: 0x0004, regnum: 0x1c, val: 0x0000);
955 phy_write_paged(phydev, page: 0x0001, regnum: 0x15, val: 0x7701);
956}
957
958static void rtl8402_hw_phy_config(struct rtl8169_private *tp,
959 struct phy_device *phydev)
960{
961 /* Disable ALDPS before setting firmware */
962 phy_write(phydev, regnum: 0x18, val: 0x0310);
963 msleep(msecs: 20);
964
965 r8169_apply_firmware(tp);
966
967 /* EEE setting */
968 phy_write(phydev, regnum: 0x1f, val: 0x0004);
969 phy_write(phydev, regnum: 0x10, val: 0x401f);
970 phy_write(phydev, regnum: 0x19, val: 0x7030);
971 phy_write(phydev, regnum: 0x1f, val: 0x0000);
972}
973
974static void rtl8106e_hw_phy_config(struct rtl8169_private *tp,
975 struct phy_device *phydev)
976{
977 static const struct phy_reg phy_reg_init[] = {
978 { 0x1f, 0x0004 },
979 { 0x10, 0xc07f },
980 { 0x19, 0x7030 },
981 { 0x1f, 0x0000 }
982 };
983
984 /* Disable ALDPS before ram code */
985 phy_write(phydev, regnum: 0x18, val: 0x0310);
986 msleep(msecs: 100);
987
988 r8169_apply_firmware(tp);
989
990 rtl_writephy_batch(phydev, phy_reg_init);
991}
992
993static void rtl8125_legacy_force_mode(struct phy_device *phydev)
994{
995 phy_modify_paged(phydev, page: 0xa5b, regnum: 0x12, BIT(15), set: 0);
996}
997
998static void rtl8125a_2_hw_phy_config(struct rtl8169_private *tp,
999 struct phy_device *phydev)
1000{
1001 int i;
1002
1003 phy_modify_paged(phydev, page: 0xad4, regnum: 0x17, mask: 0x0000, set: 0x0010);
1004 phy_modify_paged(phydev, page: 0xad1, regnum: 0x13, mask: 0x03ff, set: 0x03ff);
1005 phy_modify_paged(phydev, page: 0xad3, regnum: 0x11, mask: 0x003f, set: 0x0006);
1006 phy_modify_paged(phydev, page: 0xac0, regnum: 0x14, mask: 0x1100, set: 0x0000);
1007 phy_modify_paged(phydev, page: 0xacc, regnum: 0x10, mask: 0x0003, set: 0x0002);
1008 phy_modify_paged(phydev, page: 0xad4, regnum: 0x10, mask: 0x00e7, set: 0x0044);
1009 phy_modify_paged(phydev, page: 0xac1, regnum: 0x12, mask: 0x0080, set: 0x0000);
1010 phy_modify_paged(phydev, page: 0xac8, regnum: 0x10, mask: 0x0300, set: 0x0000);
1011 phy_modify_paged(phydev, page: 0xac5, regnum: 0x17, mask: 0x0007, set: 0x0002);
1012 phy_write_paged(phydev, page: 0xad4, regnum: 0x16, val: 0x00a8);
1013 phy_write_paged(phydev, page: 0xac5, regnum: 0x16, val: 0x01ff);
1014 phy_modify_paged(phydev, page: 0xac8, regnum: 0x15, mask: 0x00f0, set: 0x0030);
1015
1016 rtl8125_phy_param(phydev, parm: 0x80a2, mask: 0xffff, val: 0x0153);
1017 rtl8125_phy_param(phydev, parm: 0x809c, mask: 0xffff, val: 0x0153);
1018
1019 phy_write(phydev, regnum: 0x1f, val: 0x0a43);
1020 phy_write(phydev, regnum: 0x13, val: 0x81B3);
1021 phy_write(phydev, regnum: 0x14, val: 0x0043);
1022 phy_write(phydev, regnum: 0x14, val: 0x00A7);
1023 phy_write(phydev, regnum: 0x14, val: 0x00D6);
1024 phy_write(phydev, regnum: 0x14, val: 0x00EC);
1025 phy_write(phydev, regnum: 0x14, val: 0x00F6);
1026 phy_write(phydev, regnum: 0x14, val: 0x00FB);
1027 phy_write(phydev, regnum: 0x14, val: 0x00FD);
1028 phy_write(phydev, regnum: 0x14, val: 0x00FF);
1029 phy_write(phydev, regnum: 0x14, val: 0x00BB);
1030 phy_write(phydev, regnum: 0x14, val: 0x0058);
1031 phy_write(phydev, regnum: 0x14, val: 0x0029);
1032 phy_write(phydev, regnum: 0x14, val: 0x0013);
1033 phy_write(phydev, regnum: 0x14, val: 0x0009);
1034 phy_write(phydev, regnum: 0x14, val: 0x0004);
1035 phy_write(phydev, regnum: 0x14, val: 0x0002);
1036 for (i = 0; i < 25; i++)
1037 phy_write(phydev, regnum: 0x14, val: 0x0000);
1038 phy_write(phydev, regnum: 0x1f, val: 0x0000);
1039
1040 r8168g_phy_param(phydev, parm: 0x8257, mask: 0xffff, val: 0x020F);
1041 r8168g_phy_param(phydev, parm: 0x80ea, mask: 0xffff, val: 0x7843);
1042
1043 r8169_apply_firmware(tp);
1044
1045 phy_modify_paged(phydev, page: 0xd06, regnum: 0x14, mask: 0x0000, set: 0x2000);
1046
1047 r8168g_phy_param(phydev, parm: 0x81a2, mask: 0x0000, val: 0x0100);
1048
1049 phy_modify_paged(phydev, page: 0xb54, regnum: 0x16, mask: 0xff00, set: 0xdb00);
1050 phy_modify_paged(phydev, page: 0xa45, regnum: 0x12, mask: 0x0001, set: 0x0000);
1051 phy_modify_paged(phydev, page: 0xa5d, regnum: 0x12, mask: 0x0000, set: 0x0020);
1052 phy_modify_paged(phydev, page: 0xad4, regnum: 0x17, mask: 0x0010, set: 0x0000);
1053 phy_modify_paged(phydev, page: 0xa86, regnum: 0x15, mask: 0x0001, set: 0x0000);
1054 rtl8168g_enable_gphy_10m(phydev);
1055
1056 rtl8168g_disable_aldps(phydev);
1057 rtl8125_config_eee_phy(phydev);
1058}
1059
1060static void rtl8125b_hw_phy_config(struct rtl8169_private *tp,
1061 struct phy_device *phydev)
1062{
1063 r8169_apply_firmware(tp);
1064 rtl8168g_enable_gphy_10m(phydev);
1065
1066 phy_modify_paged(phydev, page: 0xac4, regnum: 0x13, mask: 0x00f0, set: 0x0090);
1067 phy_modify_paged(phydev, page: 0xad3, regnum: 0x10, mask: 0x0003, set: 0x0001);
1068
1069 rtl8125_phy_param(phydev, parm: 0x80f5, mask: 0xffff, val: 0x760e);
1070 rtl8125_phy_param(phydev, parm: 0x8107, mask: 0xffff, val: 0x360e);
1071 rtl8125_phy_param(phydev, parm: 0x8551, mask: 0xff00, val: 0x0800);
1072
1073 phy_modify_paged(phydev, page: 0xbf0, regnum: 0x10, mask: 0xe000, set: 0xa000);
1074 phy_modify_paged(phydev, page: 0xbf4, regnum: 0x13, mask: 0x0f00, set: 0x0300);
1075
1076 r8168g_phy_param(phydev, parm: 0x8044, mask: 0xffff, val: 0x2417);
1077 r8168g_phy_param(phydev, parm: 0x804a, mask: 0xffff, val: 0x2417);
1078 r8168g_phy_param(phydev, parm: 0x8050, mask: 0xffff, val: 0x2417);
1079 r8168g_phy_param(phydev, parm: 0x8056, mask: 0xffff, val: 0x2417);
1080 r8168g_phy_param(phydev, parm: 0x805c, mask: 0xffff, val: 0x2417);
1081 r8168g_phy_param(phydev, parm: 0x8062, mask: 0xffff, val: 0x2417);
1082 r8168g_phy_param(phydev, parm: 0x8068, mask: 0xffff, val: 0x2417);
1083 r8168g_phy_param(phydev, parm: 0x806e, mask: 0xffff, val: 0x2417);
1084 r8168g_phy_param(phydev, parm: 0x8074, mask: 0xffff, val: 0x2417);
1085 r8168g_phy_param(phydev, parm: 0x807a, mask: 0xffff, val: 0x2417);
1086
1087 phy_modify_paged(phydev, page: 0xa4c, regnum: 0x15, mask: 0x0000, set: 0x0040);
1088 phy_modify_paged(phydev, page: 0xbf8, regnum: 0x12, mask: 0xe000, set: 0xa000);
1089
1090 rtl8125_legacy_force_mode(phydev);
1091 rtl8168g_disable_aldps(phydev);
1092 rtl8125_config_eee_phy(phydev);
1093}
1094
1095static void rtl8125d_hw_phy_config(struct rtl8169_private *tp,
1096 struct phy_device *phydev)
1097{
1098 r8169_apply_firmware(tp);
1099 rtl8168g_enable_gphy_10m(phydev);
1100 rtl8125_legacy_force_mode(phydev);
1101 rtl8168g_disable_aldps(phydev);
1102 rtl8125_config_eee_phy(phydev);
1103}
1104
1105static void rtl8125bp_hw_phy_config(struct rtl8169_private *tp,
1106 struct phy_device *phydev)
1107{
1108 r8169_apply_firmware(tp);
1109 rtl8168g_enable_gphy_10m(phydev);
1110
1111 r8168g_phy_param(phydev, parm: 0x8010, mask: 0x0800, val: 0x0000);
1112
1113 rtl8125_phy_param(phydev, parm: 0x8088, mask: 0xff00, val: 0x9000);
1114 rtl8125_phy_param(phydev, parm: 0x808f, mask: 0xff00, val: 0x9000);
1115
1116 r8168g_phy_param(phydev, parm: 0x8174, mask: 0x2000, val: 0x1800);
1117
1118 rtl8125_legacy_force_mode(phydev);
1119 rtl8168g_disable_aldps(phydev);
1120 rtl8125_config_eee_phy(phydev);
1121}
1122
1123static void rtl8126a_hw_phy_config(struct rtl8169_private *tp,
1124 struct phy_device *phydev)
1125{
1126 r8169_apply_firmware(tp);
1127 rtl8168g_enable_gphy_10m(phydev);
1128 rtl8125_legacy_force_mode(phydev);
1129 rtl8168g_disable_aldps(phydev);
1130 rtl8125_common_config_eee_phy(phydev);
1131}
1132
1133static void rtl8127a_1_hw_phy_config(struct rtl8169_private *tp,
1134 struct phy_device *phydev)
1135{
1136 r8169_apply_firmware(tp);
1137 rtl8168g_enable_gphy_10m(phydev);
1138
1139 r8168g_phy_param(phydev, parm: 0x8415, mask: 0xff00, val: 0x9300);
1140 r8168g_phy_param(phydev, parm: 0x81a3, mask: 0xff00, val: 0x0f00);
1141 r8168g_phy_param(phydev, parm: 0x81ae, mask: 0xff00, val: 0x0f00);
1142 r8168g_phy_param(phydev, parm: 0x81b9, mask: 0xff00, val: 0xb900);
1143 rtl8125_phy_param(phydev, parm: 0x83b0, mask: 0x0e00, val: 0x0000);
1144 rtl8125_phy_param(phydev, parm: 0x83C5, mask: 0x0e00, val: 0x0000);
1145 rtl8125_phy_param(phydev, parm: 0x83da, mask: 0x0e00, val: 0x0000);
1146 rtl8125_phy_param(phydev, parm: 0x83ef, mask: 0x0e00, val: 0x0000);
1147 phy_modify_paged(phydev, page: 0x0bf3, regnum: 0x14, mask: 0x01f0, set: 0x0160);
1148 phy_modify_paged(phydev, page: 0x0bf3, regnum: 0x15, mask: 0x001f, set: 0x0014);
1149 phy_modify_paged(phydev, page: 0x0bf2, regnum: 0x14, mask: 0x6000, set: 0x0000);
1150 phy_modify_paged(phydev, page: 0x0bf2, regnum: 0x16, mask: 0xc000, set: 0x0000);
1151 phy_modify_paged(phydev, page: 0x0bf2, regnum: 0x14, mask: 0x1fff, set: 0x0187);
1152 phy_modify_paged(phydev, page: 0x0bf2, regnum: 0x15, mask: 0x003f, set: 0x0003);
1153
1154 r8168g_phy_param(phydev, parm: 0x8173, mask: 0xffff, val: 0x8620);
1155 r8168g_phy_param(phydev, parm: 0x8175, mask: 0xffff, val: 0x8671);
1156 r8168g_phy_param(phydev, parm: 0x817c, mask: 0x0000, val: 0x2000);
1157 r8168g_phy_param(phydev, parm: 0x8187, mask: 0x0000, val: 0x2000);
1158 r8168g_phy_param(phydev, parm: 0x8192, mask: 0x0000, val: 0x2000);
1159 r8168g_phy_param(phydev, parm: 0x819d, mask: 0x0000, val: 0x2000);
1160 r8168g_phy_param(phydev, parm: 0x81a8, mask: 0x2000, val: 0x0000);
1161 r8168g_phy_param(phydev, parm: 0x81b3, mask: 0x2000, val: 0x0000);
1162 r8168g_phy_param(phydev, parm: 0x81be, mask: 0x0000, val: 0x2000);
1163 r8168g_phy_param(phydev, parm: 0x817d, mask: 0xff00, val: 0xa600);
1164 r8168g_phy_param(phydev, parm: 0x8188, mask: 0xff00, val: 0xa600);
1165 r8168g_phy_param(phydev, parm: 0x8193, mask: 0xff00, val: 0xa600);
1166 r8168g_phy_param(phydev, parm: 0x819e, mask: 0xff00, val: 0xa600);
1167 r8168g_phy_param(phydev, parm: 0x81a9, mask: 0xff00, val: 0x1400);
1168 r8168g_phy_param(phydev, parm: 0x81b4, mask: 0xff00, val: 0x1400);
1169 r8168g_phy_param(phydev, parm: 0x81bf, mask: 0xff00, val: 0xa600);
1170
1171 phy_modify_paged(phydev, page: 0x0aea, regnum: 0x15, mask: 0x0028, set: 0x0000);
1172
1173 rtl8125_phy_param(phydev, parm: 0x84f0, mask: 0xffff, val: 0x201c);
1174 rtl8125_phy_param(phydev, parm: 0x84f2, mask: 0xffff, val: 0x3117);
1175
1176 phy_write_paged(phydev, page: 0x0aec, regnum: 0x13, val: 0x0000);
1177 phy_write_paged(phydev, page: 0x0ae2, regnum: 0x10, val: 0xffff);
1178 phy_write_paged(phydev, page: 0x0aec, regnum: 0x17, val: 0xffff);
1179 phy_write_paged(phydev, page: 0x0aed, regnum: 0x11, val: 0xffff);
1180 phy_write_paged(phydev, page: 0x0aec, regnum: 0x14, val: 0x0000);
1181 phy_modify_paged(phydev, page: 0x0aed, regnum: 0x10, mask: 0x0001, set: 0x0000);
1182 phy_write_paged(phydev, page: 0x0adb, regnum: 0x14, val: 0x0150);
1183 rtl8125_phy_param(phydev, parm: 0x8197, mask: 0xff00, val: 0x5000);
1184 rtl8125_phy_param(phydev, parm: 0x8231, mask: 0xff00, val: 0x5000);
1185 rtl8125_phy_param(phydev, parm: 0x82cb, mask: 0xff00, val: 0x5000);
1186 rtl8125_phy_param(phydev, parm: 0x82cd, mask: 0xff00, val: 0x5700);
1187 rtl8125_phy_param(phydev, parm: 0x8233, mask: 0xff00, val: 0x5700);
1188 rtl8125_phy_param(phydev, parm: 0x8199, mask: 0xff00, val: 0x5700);
1189
1190 rtl8125_phy_param(phydev, parm: 0x815a, mask: 0xffff, val: 0x0150);
1191 rtl8125_phy_param(phydev, parm: 0x81f4, mask: 0xffff, val: 0x0150);
1192 rtl8125_phy_param(phydev, parm: 0x828e, mask: 0xffff, val: 0x0150);
1193 rtl8125_phy_param(phydev, parm: 0x81b1, mask: 0xffff, val: 0x0000);
1194 rtl8125_phy_param(phydev, parm: 0x824b, mask: 0xffff, val: 0x0000);
1195 rtl8125_phy_param(phydev, parm: 0x82e5, mask: 0xffff, val: 0x0000);
1196
1197 rtl8125_phy_param(phydev, parm: 0x84f7, mask: 0xff00, val: 0x2800);
1198 phy_modify_paged(phydev, page: 0x0aec, regnum: 0x11, mask: 0x0000, set: 0x1000);
1199 rtl8125_phy_param(phydev, parm: 0x81b3, mask: 0xff00, val: 0xad00);
1200 rtl8125_phy_param(phydev, parm: 0x824d, mask: 0xff00, val: 0xad00);
1201 rtl8125_phy_param(phydev, parm: 0x82e7, mask: 0xff00, val: 0xad00);
1202 phy_modify_paged(phydev, page: 0x0ae4, regnum: 0x17, mask: 0x000f, set: 0x0001);
1203 rtl8125_phy_param(phydev, parm: 0x82ce, mask: 0xf000, val: 0x4000);
1204
1205 rtl8125_phy_param(phydev, parm: 0x84ac, mask: 0xffff, val: 0x0000);
1206 rtl8125_phy_param(phydev, parm: 0x84ae, mask: 0xffff, val: 0x0000);
1207 rtl8125_phy_param(phydev, parm: 0x84b0, mask: 0xffff, val: 0xf818);
1208 rtl8125_phy_param(phydev, parm: 0x84b2, mask: 0xff00, val: 0x6000);
1209
1210 rtl8125_phy_param(phydev, parm: 0x8ffc, mask: 0xffff, val: 0x6008);
1211 rtl8125_phy_param(phydev, parm: 0x8ffe, mask: 0xffff, val: 0xf450);
1212
1213 rtl8125_phy_param(phydev, parm: 0x8015, mask: 0x0000, val: 0x0200);
1214 rtl8125_phy_param(phydev, parm: 0x8016, mask: 0x0800, val: 0x0000);
1215 rtl8125_phy_param(phydev, parm: 0x8fe6, mask: 0xff00, val: 0x0800);
1216 rtl8125_phy_param(phydev, parm: 0x8fe4, mask: 0xffff, val: 0x2114);
1217
1218 rtl8125_phy_param(phydev, parm: 0x8647, mask: 0xffff, val: 0xa7b1);
1219 rtl8125_phy_param(phydev, parm: 0x8649, mask: 0xffff, val: 0xbbca);
1220 rtl8125_phy_param(phydev, parm: 0x864b, mask: 0xff00, val: 0xdc00);
1221
1222 rtl8125_phy_param(phydev, parm: 0x8154, mask: 0xc000, val: 0x4000);
1223 rtl8125_phy_param(phydev, parm: 0x8158, mask: 0xc000, val: 0x0000);
1224
1225 rtl8125_phy_param(phydev, parm: 0x826c, mask: 0xffff, val: 0xffff);
1226 rtl8125_phy_param(phydev, parm: 0x826e, mask: 0xffff, val: 0xffff);
1227
1228 rtl8125_phy_param(phydev, parm: 0x8872, mask: 0xff00, val: 0x0e00);
1229 r8168g_phy_param(phydev, parm: 0x8012, mask: 0x0000, val: 0x0800);
1230 r8168g_phy_param(phydev, parm: 0x8012, mask: 0x0000, val: 0x4000);
1231 phy_modify_paged(phydev, page: 0x0b57, regnum: 0x13, mask: 0x0000, set: 0x0001);
1232 r8168g_phy_param(phydev, parm: 0x834a, mask: 0xff00, val: 0x0700);
1233 rtl8125_phy_param(phydev, parm: 0x8217, mask: 0x3f00, val: 0x2a00);
1234 r8168g_phy_param(phydev, parm: 0x81b1, mask: 0xff00, val: 0x0b00);
1235 rtl8125_phy_param(phydev, parm: 0x8fed, mask: 0xff00, val: 0x4e00);
1236
1237 rtl8125_phy_param(phydev, parm: 0x88ac, mask: 0xff00, val: 0x2300);
1238 phy_modify_paged(phydev, page: 0x0bf0, regnum: 0x16, mask: 0x0000, set: 0x3800);
1239 rtl8125_phy_param(phydev, parm: 0x88de, mask: 0xff00, val: 0x0000);
1240 rtl8125_phy_param(phydev, parm: 0x80b4, mask: 0xffff, val: 0x5195);
1241
1242 r8168g_phy_param(phydev, parm: 0x8370, mask: 0xffff, val: 0x8671);
1243 r8168g_phy_param(phydev, parm: 0x8372, mask: 0xffff, val: 0x86c8);
1244
1245 r8168g_phy_param(phydev, parm: 0x8401, mask: 0xffff, val: 0x86c8);
1246 r8168g_phy_param(phydev, parm: 0x8403, mask: 0xffff, val: 0x86da);
1247 r8168g_phy_param(phydev, parm: 0x8406, mask: 0x1800, val: 0x1000);
1248 r8168g_phy_param(phydev, parm: 0x8408, mask: 0x1800, val: 0x1000);
1249 r8168g_phy_param(phydev, parm: 0x840a, mask: 0x1800, val: 0x1000);
1250 r8168g_phy_param(phydev, parm: 0x840c, mask: 0x1800, val: 0x1000);
1251 r8168g_phy_param(phydev, parm: 0x840e, mask: 0x1800, val: 0x1000);
1252 r8168g_phy_param(phydev, parm: 0x8410, mask: 0x1800, val: 0x1000);
1253 r8168g_phy_param(phydev, parm: 0x8412, mask: 0x1800, val: 0x1000);
1254 r8168g_phy_param(phydev, parm: 0x8414, mask: 0x1800, val: 0x1000);
1255 r8168g_phy_param(phydev, parm: 0x8416, mask: 0x1800, val: 0x1000);
1256
1257 r8168g_phy_param(phydev, parm: 0x82bd, mask: 0xffff, val: 0x1f40);
1258
1259 phy_modify_paged(phydev, page: 0x0bfb, regnum: 0x12, mask: 0x07ff, set: 0x0328);
1260 phy_write_paged(phydev, page: 0x0bfb, regnum: 0x13, val: 0x3e14);
1261
1262 r8168g_phy_param(phydev, parm: 0x81c4, mask: 0xffff, val: 0x003b);
1263 r8168g_phy_param(phydev, parm: 0x81c6, mask: 0xffff, val: 0x0086);
1264 r8168g_phy_param(phydev, parm: 0x81c8, mask: 0xffff, val: 0x00b7);
1265 r8168g_phy_param(phydev, parm: 0x81ca, mask: 0xffff, val: 0x00db);
1266 r8168g_phy_param(phydev, parm: 0x81cc, mask: 0xffff, val: 0x00fe);
1267 r8168g_phy_param(phydev, parm: 0x81ce, mask: 0xffff, val: 0x00fe);
1268 r8168g_phy_param(phydev, parm: 0x81d0, mask: 0xffff, val: 0x00fe);
1269 r8168g_phy_param(phydev, parm: 0x81d2, mask: 0xffff, val: 0x00fe);
1270 r8168g_phy_param(phydev, parm: 0x81d4, mask: 0xffff, val: 0x00c3);
1271 r8168g_phy_param(phydev, parm: 0x81d6, mask: 0xffff, val: 0x0078);
1272 r8168g_phy_param(phydev, parm: 0x81d8, mask: 0xffff, val: 0x0047);
1273 r8168g_phy_param(phydev, parm: 0x81da, mask: 0xffff, val: 0x0023);
1274
1275 rtl8125_phy_param(phydev, parm: 0x88d7, mask: 0xffff, val: 0x01a0);
1276 rtl8125_phy_param(phydev, parm: 0x88d9, mask: 0xffff, val: 0x01a0);
1277 rtl8125_phy_param(phydev, parm: 0x8ffa, mask: 0xffff, val: 0x002a);
1278
1279 rtl8125_phy_param(phydev, parm: 0x8fee, mask: 0xffff, val: 0xffdf);
1280 rtl8125_phy_param(phydev, parm: 0x8ff0, mask: 0xffff, val: 0xffff);
1281 rtl8125_phy_param(phydev, parm: 0x8ff2, mask: 0xffff, val: 0x0a4a);
1282 rtl8125_phy_param(phydev, parm: 0x8ff4, mask: 0xffff, val: 0xaa5a);
1283 rtl8125_phy_param(phydev, parm: 0x8ff6, mask: 0xffff, val: 0x0a4a);
1284
1285 rtl8125_phy_param(phydev, parm: 0x8ff8, mask: 0xffff, val: 0xaa5a);
1286 rtl8125_phy_param(phydev, parm: 0x88d5, mask: 0xff00, val: 0x0200);
1287
1288 r8168g_phy_param(phydev, parm: 0x84bb, mask: 0xff00, val: 0x0a00);
1289 r8168g_phy_param(phydev, parm: 0x84c0, mask: 0xff00, val: 0x1600);
1290
1291 phy_modify_paged(phydev, page: 0x0a43, regnum: 0x10, mask: 0x0000, set: 0x0003);
1292
1293 rtl8125_legacy_force_mode(phydev);
1294 rtl8168g_disable_aldps(phydev);
1295 rtl8125_common_config_eee_phy(phydev);
1296}
1297
1298void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev,
1299 enum mac_version ver)
1300{
1301 static const rtl_phy_cfg_fct phy_configs[] = {
1302 /* PCI devices. */
1303 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
1304 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
1305 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
1306 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
1307 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
1308 /* PCI-E devices. */
1309 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
1310 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
1311 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
1312 [RTL_GIGA_MAC_VER_10] = NULL,
1313 [RTL_GIGA_MAC_VER_14] = rtl8401_hw_phy_config,
1314 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
1315 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
1316 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
1317 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
1318 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
1319 [RTL_GIGA_MAC_VER_22] = rtl8168c_3_hw_phy_config,
1320 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
1321 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
1322 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
1323 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
1324 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
1325 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
1326 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
1327 [RTL_GIGA_MAC_VER_31] = NULL,
1328 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
1329 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
1330 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
1331 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
1332 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
1333 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
1334 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
1335 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
1336 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
1337 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
1338 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
1339 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
1340 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
1341 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
1342 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
1343 [RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config,
1344 [RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config,
1345 [RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config,
1346 [RTL_GIGA_MAC_VER_64] = rtl8125d_hw_phy_config,
1347 [RTL_GIGA_MAC_VER_66] = rtl8125bp_hw_phy_config,
1348 [RTL_GIGA_MAC_VER_70] = rtl8126a_hw_phy_config,
1349 [RTL_GIGA_MAC_VER_80] = rtl8127a_1_hw_phy_config,
1350 };
1351
1352 if (phy_configs[ver])
1353 phy_configs[ver](tp, phydev);
1354}
1355