1// SPDX-License-Identifier: GPL-2.0
2/*
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
6 *
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 *
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 *
11 * Init/reset quirks for USB host controllers should be in the USB quirks
12 * file, where their drivers can use them.
13 */
14
15#include <linux/aer.h>
16#include <linux/align.h>
17#include <linux/bitfield.h>
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/export.h>
21#include <linux/pci.h>
22#include <linux/isa-dma.h> /* isa_dma_bridge_buggy */
23#include <linux/init.h>
24#include <linux/delay.h>
25#include <linux/acpi.h>
26#include <linux/dmi.h>
27#include <linux/ioport.h>
28#include <linux/sched.h>
29#include <linux/ktime.h>
30#include <linux/mm.h>
31#include <linux/nvme.h>
32#include <linux/platform_data/x86/apple.h>
33#include <linux/pm_runtime.h>
34#include <linux/sizes.h>
35#include <linux/suspend.h>
36#include <linux/switchtec.h>
37#include "pci.h"
38
39static bool pcie_lbms_seen(struct pci_dev *dev, u16 lnksta)
40{
41 if (test_bit(PCI_LINK_LBMS_SEEN, &dev->priv_flags))
42 return true;
43
44 return lnksta & PCI_EXP_LNKSTA_LBMS;
45}
46
47/*
48 * Retrain the link of a downstream PCIe port by hand if necessary.
49 *
50 * This is needed at least where a downstream port of the ASMedia ASM2824
51 * Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304
52 * Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 >
53 * 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched
54 * board.
55 *
56 * In such a configuration the switches are supposed to negotiate the link
57 * speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link
58 * continues switching between the two speeds indefinitely and the data
59 * link layer never reaches the active state, with link training reported
60 * repeatedly active ~84% of the time. Forcing the target link speed to
61 * 2.5GT/s with the upstream ASM2824 device makes the two switches talk to
62 * each other correctly however. And more interestingly retraining with a
63 * higher target link speed afterwards lets the two successfully negotiate
64 * 5.0GT/s.
65 *
66 * With the ASM2824 we can rely on the otherwise optional Data Link Layer
67 * Link Active status bit and in the failed link training scenario it will
68 * be off along with the Link Bandwidth Management Status indicating that
69 * hardware has changed the link speed or width in an attempt to correct
70 * unreliable link operation. For a port that has been left unconnected
71 * both bits will be clear. So use this information to detect the problem
72 * rather than polling the Link Training bit and watching out for flips or
73 * at least the active status.
74 *
75 * Since the exact nature of the problem isn't known and in principle this
76 * could trigger where an ASM2824 device is downstream rather upstream,
77 * apply this erratum workaround to any downstream ports as long as they
78 * support Link Active reporting and have the Link Control 2 register.
79 * Restrict the speed to 2.5GT/s then with the Target Link Speed field,
80 * request a retrain and check the result.
81 *
82 * If this turns out successful and we know by the Vendor:Device ID it is
83 * safe to do so, then lift the restriction, letting the devices negotiate
84 * a higher speed. Also check for a similar 2.5GT/s speed restriction the
85 * firmware may have already arranged and lift it with ports that already
86 * report their data link being up.
87 *
88 * Otherwise revert the speed to the original setting and request a retrain
89 * again to remove any residual state, ignoring the result as it's supposed
90 * to fail anyway.
91 *
92 * Return 0 if the link has been successfully retrained. Return an error
93 * if retraining was not needed or we attempted a retrain and it failed.
94 */
95int pcie_failed_link_retrain(struct pci_dev *dev)
96{
97 static const struct pci_device_id ids[] = {
98 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */
99 {}
100 };
101 u16 lnksta, lnkctl2;
102 int ret = -ENOTTY;
103
104 if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) ||
105 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting)
106 return ret;
107
108 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, val: &lnksta);
109 if (!(lnksta & PCI_EXP_LNKSTA_DLLLA) && pcie_lbms_seen(dev, lnksta)) {
110 u16 oldlnkctl2;
111
112 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n");
113
114 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, val: &oldlnkctl2);
115 ret = pcie_set_target_speed(port: dev, speed_req: PCIE_SPEED_2_5GT, use_lt: false);
116 if (ret) {
117 pci_info(dev, "retraining failed\n");
118 pcie_set_target_speed(port: dev, PCIE_LNKCTL2_TLS2SPEED(oldlnkctl2),
119 use_lt: true);
120 return ret;
121 }
122
123 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, val: &lnksta);
124 }
125
126 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, val: &lnkctl2);
127
128 if ((lnksta & PCI_EXP_LNKSTA_DLLLA) &&
129 (lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT &&
130 pci_match_id(ids, dev)) {
131 u32 lnkcap;
132
133 pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n");
134 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, val: &lnkcap);
135 ret = pcie_set_target_speed(port: dev, PCIE_LNKCAP_SLS2SPEED(lnkcap), use_lt: false);
136 if (ret) {
137 pci_info(dev, "retraining failed\n");
138 return ret;
139 }
140 }
141
142 return ret;
143}
144
145static ktime_t fixup_debug_start(struct pci_dev *dev,
146 void (*fn)(struct pci_dev *dev))
147{
148 if (initcall_debug)
149 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current));
150
151 return ktime_get();
152}
153
154static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
155 void (*fn)(struct pci_dev *dev))
156{
157 ktime_t delta, rettime;
158 unsigned long long duration;
159
160 rettime = ktime_get();
161 delta = ktime_sub(rettime, calltime);
162 duration = (unsigned long long) ktime_to_ns(kt: delta) >> 10;
163 if (initcall_debug || duration > 10000)
164 pci_info(dev, "%pS took %lld usecs\n", fn, duration);
165}
166
167static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
168 struct pci_fixup *end)
169{
170 ktime_t calltime;
171
172 for (; f < end; f++)
173 if ((f->class == (u32) (dev->class >> f->class_shift) ||
174 f->class == (u32) PCI_ANY_ID) &&
175 (f->vendor == dev->vendor ||
176 f->vendor == (u16) PCI_ANY_ID) &&
177 (f->device == dev->device ||
178 f->device == (u16) PCI_ANY_ID)) {
179 void (*hook)(struct pci_dev *dev);
180#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
181 hook = offset_to_ptr(off: &f->hook_offset);
182#else
183 hook = f->hook;
184#endif
185 calltime = fixup_debug_start(dev, fn: hook);
186 hook(dev);
187 fixup_debug_report(dev, calltime, fn: hook);
188 }
189}
190
191extern struct pci_fixup __start_pci_fixups_early[];
192extern struct pci_fixup __end_pci_fixups_early[];
193extern struct pci_fixup __start_pci_fixups_header[];
194extern struct pci_fixup __end_pci_fixups_header[];
195extern struct pci_fixup __start_pci_fixups_final[];
196extern struct pci_fixup __end_pci_fixups_final[];
197extern struct pci_fixup __start_pci_fixups_enable[];
198extern struct pci_fixup __end_pci_fixups_enable[];
199extern struct pci_fixup __start_pci_fixups_resume[];
200extern struct pci_fixup __end_pci_fixups_resume[];
201extern struct pci_fixup __start_pci_fixups_resume_early[];
202extern struct pci_fixup __end_pci_fixups_resume_early[];
203extern struct pci_fixup __start_pci_fixups_suspend[];
204extern struct pci_fixup __end_pci_fixups_suspend[];
205extern struct pci_fixup __start_pci_fixups_suspend_late[];
206extern struct pci_fixup __end_pci_fixups_suspend_late[];
207
208static bool pci_apply_fixup_final_quirks;
209
210void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
211{
212 struct pci_fixup *start, *end;
213
214 switch (pass) {
215 case pci_fixup_early:
216 start = __start_pci_fixups_early;
217 end = __end_pci_fixups_early;
218 break;
219
220 case pci_fixup_header:
221 start = __start_pci_fixups_header;
222 end = __end_pci_fixups_header;
223 break;
224
225 case pci_fixup_final:
226 if (!pci_apply_fixup_final_quirks)
227 return;
228 start = __start_pci_fixups_final;
229 end = __end_pci_fixups_final;
230 break;
231
232 case pci_fixup_enable:
233 start = __start_pci_fixups_enable;
234 end = __end_pci_fixups_enable;
235 break;
236
237 case pci_fixup_resume:
238 start = __start_pci_fixups_resume;
239 end = __end_pci_fixups_resume;
240 break;
241
242 case pci_fixup_resume_early:
243 start = __start_pci_fixups_resume_early;
244 end = __end_pci_fixups_resume_early;
245 break;
246
247 case pci_fixup_suspend:
248 start = __start_pci_fixups_suspend;
249 end = __end_pci_fixups_suspend;
250 break;
251
252 case pci_fixup_suspend_late:
253 start = __start_pci_fixups_suspend_late;
254 end = __end_pci_fixups_suspend_late;
255 break;
256
257 default:
258 /* stupid compiler warning, you would think with an enum... */
259 return;
260 }
261 pci_do_fixups(dev, f: start, end);
262}
263EXPORT_SYMBOL(pci_fixup_device);
264
265static int __init pci_apply_final_quirks(void)
266{
267 struct pci_dev *dev = NULL;
268 u8 cls = 0;
269 u8 tmp;
270
271 if (pci_cache_line_size)
272 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
273
274 pci_apply_fixup_final_quirks = true;
275 for_each_pci_dev(dev) {
276 pci_fixup_device(pci_fixup_final, dev);
277 /*
278 * If arch hasn't set it explicitly yet, use the CLS
279 * value shared by all PCI devices. If there's a
280 * mismatch, fall back to the default value.
281 */
282 if (!pci_cache_line_size) {
283 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, val: &tmp);
284 if (!cls)
285 cls = tmp;
286 if (!tmp || cls == tmp)
287 continue;
288
289 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
290 cls << 2, tmp << 2,
291 pci_dfl_cache_line_size << 2);
292 pci_cache_line_size = pci_dfl_cache_line_size;
293 }
294 }
295
296 if (!pci_cache_line_size) {
297 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
298 pci_dfl_cache_line_size << 2);
299 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
300 }
301
302 return 0;
303}
304fs_initcall_sync(pci_apply_final_quirks);
305
306/*
307 * Decoding should be disabled for a PCI device during BAR sizing to avoid
308 * conflict. But doing so may cause problems on host bridge and perhaps other
309 * key system devices. For devices that need to have mmio decoding always-on,
310 * we need to set the dev->mmio_always_on bit.
311 */
312static void quirk_mmio_always_on(struct pci_dev *dev)
313{
314 dev->mmio_always_on = 1;
315}
316DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
317 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
318
319/*
320 * The Mellanox Tavor device gives false positive parity errors. Disable
321 * parity error reporting.
322 */
323DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity);
324DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity);
325
326/*
327 * Deal with broken BIOSes that neglect to enable passive release,
328 * which can cause problems in combination with the 82441FX/PPro MTRRs
329 */
330static void quirk_passive_release(struct pci_dev *dev)
331{
332 struct pci_dev *d = NULL;
333 unsigned char dlc;
334
335 /*
336 * We have to make sure a particular bit is set in the PIIX3
337 * ISA bridge, so we have to go out and find it.
338 */
339 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, from: d))) {
340 pci_read_config_byte(dev: d, where: 0x82, val: &dlc);
341 if (!(dlc & 1<<1)) {
342 pci_info(d, "PIIX3: Enabling Passive Release\n");
343 dlc |= 1<<1;
344 pci_write_config_byte(dev: d, where: 0x82, val: dlc);
345 }
346 }
347}
348DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
349DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
350
351#ifdef CONFIG_X86_32
352/*
353 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
354 * workaround but VIA don't answer queries. If you happen to have good
355 * contacts at VIA ask them for me please -- Alan
356 *
357 * This appears to be BIOS not version dependent. So presumably there is a
358 * chipset level fix.
359 */
360static void quirk_isa_dma_hangs(struct pci_dev *dev)
361{
362 if (!isa_dma_bridge_buggy) {
363 isa_dma_bridge_buggy = 1;
364 pci_info(dev, "Activating ISA DMA hang workarounds\n");
365 }
366}
367/*
368 * It's not totally clear which chipsets are the problematic ones. We know
369 * 82C586 and 82C596 variants are affected.
370 */
371DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
372DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
373DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
374DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
375DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
376DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
377DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
378#endif
379
380#ifdef CONFIG_HAS_IOPORT
381/*
382 * Intel NM10 "Tiger Point" LPC PM1a_STS.BM_STS must be clear
383 * for some HT machines to use C4 w/o hanging.
384 */
385static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
386{
387 u32 pmbase;
388 u16 pm1a;
389
390 pci_read_config_dword(dev, where: 0x40, val: &pmbase);
391 pmbase = pmbase & 0xff80;
392 pm1a = inw(port: pmbase);
393
394 if (pm1a & 0x10) {
395 pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n");
396 outw(value: 0x10, port: pmbase);
397 }
398}
399DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
400#endif
401
402/* Chipsets where PCI->PCI transfers vanish or hang */
403static void quirk_nopcipci(struct pci_dev *dev)
404{
405 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
406 pci_info(dev, "Disabling direct PCI/PCI transfers\n");
407 pci_pci_problems |= PCIPCI_FAIL;
408 }
409}
410DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
411DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
412
413static void quirk_nopciamd(struct pci_dev *dev)
414{
415 u8 rev;
416 pci_read_config_byte(dev, where: 0x08, val: &rev);
417 if (rev == 0x13) {
418 /* Erratum 24 */
419 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
420 pci_pci_problems |= PCIAGP_FAIL;
421 }
422}
423DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
424
425/* Triton requires workarounds to be used by the drivers */
426static void quirk_triton(struct pci_dev *dev)
427{
428 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
429 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
430 pci_pci_problems |= PCIPCI_TRITON;
431 }
432}
433DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
434DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
435DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
436DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
437
438/*
439 * VIA Apollo KT133 needs PCI latency patch
440 * Made according to a Windows driver-based patch by George E. Breese;
441 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
442 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
443 * which Mr Breese based his work.
444 *
445 * Updated based on further information from the site and also on
446 * information provided by VIA
447 */
448static void quirk_vialatency(struct pci_dev *dev)
449{
450 struct pci_dev *p;
451 u8 busarb;
452
453 /*
454 * Ok, we have a potential problem chipset here. Now see if we have
455 * a buggy southbridge.
456 */
457 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
458 if (p != NULL) {
459
460 /*
461 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
462 * thanks Dan Hollis.
463 * Check for buggy part revisions
464 */
465 if (p->revision < 0x40 || p->revision > 0x42)
466 goto exit;
467 } else {
468 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
469 if (p == NULL) /* No problem parts */
470 goto exit;
471
472 /* Check for buggy part revisions */
473 if (p->revision < 0x10 || p->revision > 0x12)
474 goto exit;
475 }
476
477 /*
478 * Ok we have the problem. Now set the PCI master grant to occur
479 * every master grant. The apparent bug is that under high PCI load
480 * (quite common in Linux of course) you can get data loss when the
481 * CPU is held off the bus for 3 bus master requests. This happens
482 * to include the IDE controllers....
483 *
484 * VIA only apply this fix when an SB Live! is present but under
485 * both Linux and Windows this isn't enough, and we have seen
486 * corruption without SB Live! but with things like 3 UDMA IDE
487 * controllers. So we ignore that bit of the VIA recommendation..
488 */
489 pci_read_config_byte(dev, where: 0x76, val: &busarb);
490
491 /*
492 * Set bit 4 and bit 5 of byte 76 to 0x01
493 * "Master priority rotation on every PCI master grant"
494 */
495 busarb &= ~(1<<5);
496 busarb |= (1<<4);
497 pci_write_config_byte(dev, where: 0x76, val: busarb);
498 pci_info(dev, "Applying VIA southbridge workaround\n");
499exit:
500 pci_dev_put(dev: p);
501}
502DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
503DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
504DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
505/* Must restore this on a resume from RAM */
506DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
507DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
508DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
509
510/* VIA Apollo VP3 needs ETBF on BT848/878 */
511static void quirk_viaetbf(struct pci_dev *dev)
512{
513 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
514 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
515 pci_pci_problems |= PCIPCI_VIAETBF;
516 }
517}
518DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
519
520static void quirk_vsfx(struct pci_dev *dev)
521{
522 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
523 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
524 pci_pci_problems |= PCIPCI_VSFX;
525 }
526}
527DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
528
529/*
530 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
531 * space. Latency must be set to 0xA and Triton workaround applied too.
532 * [Info kindly provided by ALi]
533 */
534static void quirk_alimagik(struct pci_dev *dev)
535{
536 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
537 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
538 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
539 }
540}
541DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
542DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
543
544/* Natoma has some interesting boundary conditions with Zoran stuff at least */
545static void quirk_natoma(struct pci_dev *dev)
546{
547 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
548 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
549 pci_pci_problems |= PCIPCI_NATOMA;
550 }
551}
552DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
553DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
554DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
555DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
556DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
557DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
558
559/*
560 * This chip can cause PCI parity errors if config register 0xA0 is read
561 * while DMAs are occurring.
562 */
563static void quirk_citrine(struct pci_dev *dev)
564{
565 dev->cfg_size = 0xA0;
566}
567DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
568
569/*
570 * This chip can cause bus lockups if config addresses above 0x600
571 * are read or written.
572 */
573static void quirk_nfp6000(struct pci_dev *dev)
574{
575 dev->cfg_size = 0x600;
576}
577DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
578DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
579DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000);
580DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
581
582/* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
583static void quirk_extend_bar_to_page(struct pci_dev *dev)
584{
585 int i;
586
587 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
588 struct resource *r = &dev->resource[i];
589 const char *r_name = pci_resource_name(dev, i);
590
591 if (r->flags & IORESOURCE_MEM && resource_size(res: r) < PAGE_SIZE) {
592 resource_set_range(res: r, start: 0, PAGE_SIZE);
593 r->flags |= IORESOURCE_UNSET;
594 pci_info(dev, "%s %pR: expanded to page size\n",
595 r_name, r);
596 }
597 }
598}
599DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
600
601/*
602 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
603 * If it's needed, re-allocate the region.
604 */
605static void quirk_s3_64M(struct pci_dev *dev)
606{
607 struct resource *r = &dev->resource[0];
608
609 if (!IS_ALIGNED(r->start, SZ_64M) || resource_size(res: r) != SZ_64M) {
610 r->flags |= IORESOURCE_UNSET;
611 resource_set_range(res: r, start: 0, SZ_64M);
612 }
613}
614DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
615DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
616
617static void quirk_io(struct pci_dev *dev, int pos, unsigned int size,
618 const char *name)
619{
620 u32 region;
621 struct pci_bus_region bus_region;
622 struct resource *res = pci_resource_n(dev, pos);
623 const char *res_name = pci_resource_name(dev, i: pos);
624
625 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), val: &region);
626
627 if (!region)
628 return;
629
630 res->name = pci_name(pdev: dev);
631 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
632 res->flags |=
633 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
634 region &= ~(size - 1);
635
636 /* Convert from PCI bus to resource space */
637 bus_region.start = region;
638 bus_region.end = region + size - 1;
639 pcibios_bus_to_resource(bus: dev->bus, res, region: &bus_region);
640
641 pci_info(dev, FW_BUG "%s %pR: %s quirk\n", res_name, res, name);
642}
643
644/*
645 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
646 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
647 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
648 * (which conflicts w/ BAR1's memory range).
649 *
650 * CS553x's ISA PCI BARs may also be read-only (ref:
651 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
652 */
653static void quirk_cs5536_vsa(struct pci_dev *dev)
654{
655 static char *name = "CS5536 ISA bridge";
656
657 if (pci_resource_len(dev, 0) != 8) {
658 quirk_io(dev, pos: 0, size: 8, name); /* SMB */
659 quirk_io(dev, pos: 1, size: 256, name); /* GPIO */
660 quirk_io(dev, pos: 2, size: 64, name); /* MFGPT */
661 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
662 name);
663 }
664}
665DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
666
667static void quirk_io_region(struct pci_dev *dev, int port,
668 unsigned int size, int nr, const char *name)
669{
670 u16 region;
671 struct pci_bus_region bus_region;
672 struct resource *res = pci_resource_n(dev, nr);
673
674 pci_read_config_word(dev, where: port, val: &region);
675 region &= ~(size - 1);
676
677 if (!region)
678 return;
679
680 res->name = pci_name(pdev: dev);
681 res->flags = IORESOURCE_IO;
682
683 /* Convert from PCI bus to resource space */
684 bus_region.start = region;
685 bus_region.end = region + size - 1;
686 pcibios_bus_to_resource(bus: dev->bus, res, region: &bus_region);
687
688 /*
689 * "res" is typically a bridge window resource that's not being
690 * used for a bridge window, so it's just a place to stash this
691 * non-standard resource. Printing "nr" or pci_resource_name() of
692 * it doesn't really make sense.
693 */
694 if (!pci_claim_resource(dev, nr))
695 pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
696}
697
698/*
699 * ATI Northbridge setups MCE the processor if you even read somewhere
700 * between 0x3b0->0x3bb or read 0x3d3
701 */
702static void quirk_ati_exploding_mce(struct pci_dev *dev)
703{
704 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
705 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
706 request_region(0x3b0, 0x0C, "RadeonIGP");
707 request_region(0x3d3, 0x01, "RadeonIGP");
708}
709DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
710
711/*
712 * In the AMD NL platform, this device ([1022:7912]) has a class code of
713 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
714 * claim it. The same applies on the VanGogh platform device ([1022:163a]).
715 *
716 * But the dwc3 driver is a more specific driver for this device, and we'd
717 * prefer to use it instead of xhci. To prevent xhci from claiming the
718 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
719 * defines as "USB device (not host controller)". The dwc3 driver can then
720 * claim it based on its Vendor and Device ID.
721 */
722static void quirk_amd_dwc_class(struct pci_dev *pdev)
723{
724 u32 class = pdev->class;
725
726 if (class != PCI_CLASS_SERIAL_USB_DEVICE) {
727 /* Use "USB Device (not host controller)" class */
728 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
729 pci_info(pdev,
730 "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
731 class, pdev->class);
732 }
733}
734DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
735 quirk_amd_dwc_class);
736DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VANGOGH_USB,
737 quirk_amd_dwc_class);
738
739/*
740 * Synopsys USB 3.x host HAPS platform has a class code of
741 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
742 * devices should use dwc3-haps driver. Change these devices' class code to
743 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
744 * them.
745 */
746static void quirk_synopsys_haps(struct pci_dev *pdev)
747{
748 u32 class = pdev->class;
749
750 switch (pdev->device) {
751 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
752 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
753 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
754 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
755 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
756 class, pdev->class);
757 break;
758 }
759}
760DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
761 PCI_CLASS_SERIAL_USB_XHCI, 0,
762 quirk_synopsys_haps);
763
764/*
765 * Let's make the southbridge information explicit instead of having to
766 * worry about people probing the ACPI areas, for example.. (Yes, it
767 * happens, and if you read the wrong ACPI register it will put the machine
768 * to sleep with no way of waking it up again. Bummer).
769 *
770 * ALI M7101: Two IO regions pointed to by words at
771 * 0xE0 (64 bytes of ACPI registers)
772 * 0xE2 (32 bytes of SMB registers)
773 */
774static void quirk_ali7101_acpi(struct pci_dev *dev)
775{
776 quirk_io_region(dev, port: 0xE0, size: 64, nr: PCI_BRIDGE_RESOURCES, name: "ali7101 ACPI");
777 quirk_io_region(dev, port: 0xE2, size: 32, nr: PCI_BRIDGE_RESOURCES+1, name: "ali7101 SMB");
778}
779DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
780
781static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
782{
783 u32 devres;
784 u32 mask, size, base;
785
786 pci_read_config_dword(dev, where: port, val: &devres);
787 if ((devres & enable) != enable)
788 return;
789 mask = (devres >> 16) & 15;
790 base = devres & 0xffff;
791 size = 16;
792 for (;;) {
793 unsigned int bit = size >> 1;
794 if ((bit & mask) == bit)
795 break;
796 size = bit;
797 }
798 /*
799 * For now we only print it out. Eventually we'll want to
800 * reserve it (at least if it's in the 0x1000+ range), but
801 * let's get enough confirmation reports first.
802 */
803 base &= -size;
804 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
805}
806
807static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
808{
809 u32 devres;
810 u32 mask, size, base;
811
812 pci_read_config_dword(dev, where: port, val: &devres);
813 if ((devres & enable) != enable)
814 return;
815 base = devres & 0xffff0000;
816 mask = (devres & 0x3f) << 16;
817 size = 128 << 16;
818 for (;;) {
819 unsigned int bit = size >> 1;
820 if ((bit & mask) == bit)
821 break;
822 size = bit;
823 }
824
825 /*
826 * For now we only print it out. Eventually we'll want to
827 * reserve it, but let's get enough confirmation reports first.
828 */
829 base &= -size;
830 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
831}
832
833/*
834 * PIIX4 ACPI: Two IO regions pointed to by longwords at
835 * 0x40 (64 bytes of ACPI registers)
836 * 0x90 (16 bytes of SMB registers)
837 * and a few strange programmable PIIX4 device resources.
838 */
839static void quirk_piix4_acpi(struct pci_dev *dev)
840{
841 u32 res_a;
842
843 quirk_io_region(dev, port: 0x40, size: 64, nr: PCI_BRIDGE_RESOURCES, name: "PIIX4 ACPI");
844 quirk_io_region(dev, port: 0x90, size: 16, nr: PCI_BRIDGE_RESOURCES+1, name: "PIIX4 SMB");
845
846 /* Device resource A has enables for some of the other ones */
847 pci_read_config_dword(dev, where: 0x5c, val: &res_a);
848
849 piix4_io_quirk(dev, name: "PIIX4 devres B", port: 0x60, enable: 3 << 21);
850 piix4_io_quirk(dev, name: "PIIX4 devres C", port: 0x64, enable: 3 << 21);
851
852 /* Device resource D is just bitfields for static resources */
853
854 /* Device 12 enabled? */
855 if (res_a & (1 << 29)) {
856 piix4_io_quirk(dev, name: "PIIX4 devres E", port: 0x68, enable: 1 << 20);
857 piix4_mem_quirk(dev, name: "PIIX4 devres F", port: 0x6c, enable: 1 << 7);
858 }
859 /* Device 13 enabled? */
860 if (res_a & (1 << 30)) {
861 piix4_io_quirk(dev, name: "PIIX4 devres G", port: 0x70, enable: 1 << 20);
862 piix4_mem_quirk(dev, name: "PIIX4 devres H", port: 0x74, enable: 1 << 7);
863 }
864 piix4_io_quirk(dev, name: "PIIX4 devres I", port: 0x78, enable: 1 << 20);
865 piix4_io_quirk(dev, name: "PIIX4 devres J", port: 0x7c, enable: 1 << 20);
866}
867DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
868DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
869
870#define ICH_PMBASE 0x40
871#define ICH_ACPI_CNTL 0x44
872#define ICH4_ACPI_EN 0x10
873#define ICH6_ACPI_EN 0x80
874#define ICH4_GPIOBASE 0x58
875#define ICH4_GPIO_CNTL 0x5c
876#define ICH4_GPIO_EN 0x10
877#define ICH6_GPIOBASE 0x48
878#define ICH6_GPIO_CNTL 0x4c
879#define ICH6_GPIO_EN 0x10
880
881/*
882 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
883 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
884 * 0x58 (64 bytes of GPIO I/O space)
885 */
886static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
887{
888 u8 enable;
889
890 /*
891 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
892 * with low legacy (and fixed) ports. We don't know the decoding
893 * priority and can't tell whether the legacy device or the one created
894 * here is really at that address. This happens on boards with broken
895 * BIOSes.
896 */
897 pci_read_config_byte(dev, ICH_ACPI_CNTL, val: &enable);
898 if (enable & ICH4_ACPI_EN)
899 quirk_io_region(dev, ICH_PMBASE, size: 128, nr: PCI_BRIDGE_RESOURCES,
900 name: "ICH4 ACPI/GPIO/TCO");
901
902 pci_read_config_byte(dev, ICH4_GPIO_CNTL, val: &enable);
903 if (enable & ICH4_GPIO_EN)
904 quirk_io_region(dev, ICH4_GPIOBASE, size: 64, nr: PCI_BRIDGE_RESOURCES+1,
905 name: "ICH4 GPIO");
906}
907DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
908DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
909DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
910DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
911DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
912DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
913DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
914DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
915DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
916DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
917
918static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
919{
920 u8 enable;
921
922 pci_read_config_byte(dev, ICH_ACPI_CNTL, val: &enable);
923 if (enable & ICH6_ACPI_EN)
924 quirk_io_region(dev, ICH_PMBASE, size: 128, nr: PCI_BRIDGE_RESOURCES,
925 name: "ICH6 ACPI/GPIO/TCO");
926
927 pci_read_config_byte(dev, ICH6_GPIO_CNTL, val: &enable);
928 if (enable & ICH6_GPIO_EN)
929 quirk_io_region(dev, ICH6_GPIOBASE, size: 64, nr: PCI_BRIDGE_RESOURCES+1,
930 name: "ICH6 GPIO");
931}
932
933static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg,
934 const char *name, int dynsize)
935{
936 u32 val;
937 u32 size, base;
938
939 pci_read_config_dword(dev, where: reg, val: &val);
940
941 /* Enabled? */
942 if (!(val & 1))
943 return;
944 base = val & 0xfffc;
945 if (dynsize) {
946 /*
947 * This is not correct. It is 16, 32 or 64 bytes depending on
948 * register D31:F0:ADh bits 5:4.
949 *
950 * But this gets us at least _part_ of it.
951 */
952 size = 16;
953 } else {
954 size = 128;
955 }
956 base &= ~(size-1);
957
958 /*
959 * Just print it out for now. We should reserve it after more
960 * debugging.
961 */
962 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
963}
964
965static void quirk_ich6_lpc(struct pci_dev *dev)
966{
967 /* Shared ACPI/GPIO decode with all ICH6+ */
968 ich6_lpc_acpi_gpio(dev);
969
970 /* ICH6-specific generic IO decode */
971 ich6_lpc_generic_decode(dev, reg: 0x84, name: "LPC Generic IO decode 1", dynsize: 0);
972 ich6_lpc_generic_decode(dev, reg: 0x88, name: "LPC Generic IO decode 2", dynsize: 1);
973}
974DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
975DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
976
977static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg,
978 const char *name)
979{
980 u32 val;
981 u32 mask, base;
982
983 pci_read_config_dword(dev, where: reg, val: &val);
984
985 /* Enabled? */
986 if (!(val & 1))
987 return;
988
989 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
990 base = val & 0xfffc;
991 mask = (val >> 16) & 0xfc;
992 mask |= 3;
993
994 /*
995 * Just print it out for now. We should reserve it after more
996 * debugging.
997 */
998 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
999}
1000
1001/* ICH7-10 has the same common LPC generic IO decode registers */
1002static void quirk_ich7_lpc(struct pci_dev *dev)
1003{
1004 /* We share the common ACPI/GPIO decode with ICH6 */
1005 ich6_lpc_acpi_gpio(dev);
1006
1007 /* And have 4 ICH7+ generic decodes */
1008 ich7_lpc_generic_decode(dev, reg: 0x84, name: "ICH7 LPC Generic IO decode 1");
1009 ich7_lpc_generic_decode(dev, reg: 0x88, name: "ICH7 LPC Generic IO decode 2");
1010 ich7_lpc_generic_decode(dev, reg: 0x8c, name: "ICH7 LPC Generic IO decode 3");
1011 ich7_lpc_generic_decode(dev, reg: 0x90, name: "ICH7 LPC Generic IO decode 4");
1012}
1013DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
1014DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
1015DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
1016DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
1017DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
1018DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
1019DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
1020DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
1021DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
1022DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
1023DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
1024DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
1025DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
1026
1027/*
1028 * VIA ACPI: One IO region pointed to by longword at
1029 * 0x48 or 0x20 (256 bytes of ACPI registers)
1030 */
1031static void quirk_vt82c586_acpi(struct pci_dev *dev)
1032{
1033 if (dev->revision & 0x10)
1034 quirk_io_region(dev, port: 0x48, size: 256, nr: PCI_BRIDGE_RESOURCES,
1035 name: "vt82c586 ACPI");
1036}
1037DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
1038
1039/*
1040 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
1041 * 0x48 (256 bytes of ACPI registers)
1042 * 0x70 (128 bytes of hardware monitoring register)
1043 * 0x90 (16 bytes of SMB registers)
1044 */
1045static void quirk_vt82c686_acpi(struct pci_dev *dev)
1046{
1047 quirk_vt82c586_acpi(dev);
1048
1049 quirk_io_region(dev, port: 0x70, size: 128, nr: PCI_BRIDGE_RESOURCES+1,
1050 name: "vt82c686 HW-mon");
1051
1052 quirk_io_region(dev, port: 0x90, size: 16, nr: PCI_BRIDGE_RESOURCES+2, name: "vt82c686 SMB");
1053}
1054DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
1055
1056/*
1057 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
1058 * 0x88 (128 bytes of power management registers)
1059 * 0xd0 (16 bytes of SMB registers)
1060 */
1061static void quirk_vt8235_acpi(struct pci_dev *dev)
1062{
1063 quirk_io_region(dev, port: 0x88, size: 128, nr: PCI_BRIDGE_RESOURCES, name: "vt8235 PM");
1064 quirk_io_region(dev, port: 0xd0, size: 16, nr: PCI_BRIDGE_RESOURCES+1, name: "vt8235 SMB");
1065}
1066DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
1067
1068/*
1069 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
1070 * back-to-back: Disable fast back-to-back on the secondary bus segment
1071 */
1072static void quirk_xio2000a(struct pci_dev *dev)
1073{
1074 struct pci_dev *pdev;
1075 u16 command;
1076
1077 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
1078 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
1079 pci_read_config_word(dev: pdev, PCI_COMMAND, val: &command);
1080 if (command & PCI_COMMAND_FAST_BACK)
1081 pci_write_config_word(dev: pdev, PCI_COMMAND, val: command & ~PCI_COMMAND_FAST_BACK);
1082 }
1083}
1084DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
1085 quirk_xio2000a);
1086
1087#ifdef CONFIG_X86_IO_APIC
1088
1089#include <asm/io_apic.h>
1090
1091/*
1092 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
1093 * devices to the external APIC.
1094 *
1095 * TODO: When we have device-specific interrupt routers, this code will go
1096 * away from quirks.
1097 */
1098static void quirk_via_ioapic(struct pci_dev *dev)
1099{
1100 u8 tmp;
1101
1102 if (nr_ioapics < 1)
1103 tmp = 0; /* nothing routed to external APIC */
1104 else
1105 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
1106
1107 pci_info(dev, "%s VIA external APIC routing\n",
1108 tmp ? "Enabling" : "Disabling");
1109
1110 /* Offset 0x58: External APIC IRQ output control */
1111 pci_write_config_byte(dev, where: 0x58, val: tmp);
1112}
1113DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
1114DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
1115
1116/*
1117 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
1118 * This leads to doubled level interrupt rates.
1119 * Set this bit to get rid of cycle wastage.
1120 * Otherwise uncritical.
1121 */
1122static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
1123{
1124 u8 misc_control2;
1125#define BYPASS_APIC_DEASSERT 8
1126
1127 pci_read_config_byte(dev, where: 0x5B, val: &misc_control2);
1128 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
1129 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
1130 pci_write_config_byte(dev, where: 0x5B, val: misc_control2|BYPASS_APIC_DEASSERT);
1131 }
1132}
1133DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1134DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1135
1136/*
1137 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1138 * We check all revs >= B0 (yet not in the pre production!) as the bug
1139 * is currently marked NoFix
1140 *
1141 * We have multiple reports of hangs with this chipset that went away with
1142 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1143 * of course. However the advice is demonstrably good even if so.
1144 */
1145static void quirk_amd_ioapic(struct pci_dev *dev)
1146{
1147 if (dev->revision >= 0x02) {
1148 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1149 pci_warn(dev, " : booting with the \"noapic\" option\n");
1150 }
1151}
1152DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1153#endif /* CONFIG_X86_IO_APIC */
1154
1155#if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1156
1157static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
1158{
1159 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1160 if (dev->subsystem_device == 0xa118)
1161 dev->sriov->link = dev->devfn;
1162}
1163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1164#endif
1165
1166/*
1167 * Some settings of MMRBC can lead to data corruption so block changes.
1168 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1169 */
1170static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
1171{
1172 if (dev->subordinate && dev->revision <= 0x12) {
1173 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1174 dev->revision);
1175 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
1176 }
1177}
1178DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1179
1180/*
1181 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1182 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1183 * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1184 * of the ACPI SCI interrupt is only done for convenience.
1185 * -jgarzik
1186 */
1187static void quirk_via_acpi(struct pci_dev *d)
1188{
1189 u8 irq;
1190
1191 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1192 pci_read_config_byte(dev: d, where: 0x42, val: &irq);
1193 irq &= 0xf;
1194 if (irq && (irq != 2))
1195 d->irq = irq;
1196}
1197DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
1198DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1199
1200/* VIA bridges which have VLink */
1201static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1202
1203static void quirk_via_bridge(struct pci_dev *dev)
1204{
1205 /* See what bridge we have and find the device ranges */
1206 switch (dev->device) {
1207 case PCI_DEVICE_ID_VIA_82C686:
1208 /*
1209 * The VT82C686 is special; it attaches to PCI and can have
1210 * any device number. All its subdevices are functions of
1211 * that single device.
1212 */
1213 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1214 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
1215 break;
1216 case PCI_DEVICE_ID_VIA_8237:
1217 case PCI_DEVICE_ID_VIA_8237A:
1218 via_vlink_dev_lo = 15;
1219 break;
1220 case PCI_DEVICE_ID_VIA_8235:
1221 via_vlink_dev_lo = 16;
1222 break;
1223 case PCI_DEVICE_ID_VIA_8231:
1224 case PCI_DEVICE_ID_VIA_8233_0:
1225 case PCI_DEVICE_ID_VIA_8233A:
1226 case PCI_DEVICE_ID_VIA_8233C_0:
1227 via_vlink_dev_lo = 17;
1228 break;
1229 }
1230}
1231DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
1232DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
1233DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
1234DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
1235DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
1236DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
1237DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
1238DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
1239
1240/*
1241 * quirk_via_vlink - VIA VLink IRQ number update
1242 * @dev: PCI device
1243 *
1244 * If the device we are dealing with is on a PIC IRQ we need to ensure that
1245 * the IRQ line register which usually is not relevant for PCI cards, is
1246 * actually written so that interrupts get sent to the right place.
1247 *
1248 * We only do this on systems where a VIA south bridge was detected, and
1249 * only for VIA devices on the motherboard (see quirk_via_bridge above).
1250 */
1251static void quirk_via_vlink(struct pci_dev *dev)
1252{
1253 u8 irq, new_irq;
1254
1255 /* Check if we have VLink at all */
1256 if (via_vlink_dev_lo == -1)
1257 return;
1258
1259 new_irq = dev->irq;
1260
1261 /* Don't quirk interrupts outside the legacy IRQ range */
1262 if (!new_irq || new_irq > 15)
1263 return;
1264
1265 /* Internal device ? */
1266 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1267 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1268 return;
1269
1270 /*
1271 * This is an internal VLink device on a PIC interrupt. The BIOS
1272 * ought to have set this but may not have, so we redo it.
1273 */
1274 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, val: &irq);
1275 if (new_irq != irq) {
1276 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
1277 irq, new_irq);
1278 udelay(usec: 15); /* unknown if delay really needed */
1279 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, val: new_irq);
1280 }
1281}
1282DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
1283
1284/*
1285 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1286 * of VT82C597 for backward compatibility. We need to switch it off to be
1287 * able to recognize the real type of the chip.
1288 */
1289static void quirk_vt82c598_id(struct pci_dev *dev)
1290{
1291 pci_write_config_byte(dev, where: 0xfc, val: 0);
1292 pci_read_config_word(dev, PCI_DEVICE_ID, val: &dev->device);
1293}
1294DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1295
1296/*
1297 * CardBus controllers have a legacy base address that enables them to
1298 * respond as i82365 pcmcia controllers. We don't want them to do this
1299 * even if the Linux CardBus driver is not loaded, because the Linux i82365
1300 * driver does not (and should not) handle CardBus.
1301 */
1302static void quirk_cardbus_legacy(struct pci_dev *dev)
1303{
1304 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, val: 0);
1305}
1306DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1307 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1308DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1309 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1310
1311/*
1312 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1313 * what the designers were smoking but let's not inhale...
1314 *
1315 * To be fair to AMD, it follows the spec by default, it's BIOS people who
1316 * turn it off!
1317 */
1318static void quirk_amd_ordering(struct pci_dev *dev)
1319{
1320 u32 pcic;
1321 pci_read_config_dword(dev, where: 0x4C, val: &pcic);
1322 if ((pcic & 6) != 6) {
1323 pcic |= 6;
1324 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1325 pci_write_config_dword(dev, where: 0x4C, val: pcic);
1326 pci_read_config_dword(dev, where: 0x84, val: &pcic);
1327 pcic |= (1 << 23); /* Required in this mode */
1328 pci_write_config_dword(dev, where: 0x84, val: pcic);
1329 }
1330}
1331DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1332DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1333
1334/*
1335 * DreamWorks-provided workaround for Dunord I-3000 problem
1336 *
1337 * This card decodes and responds to addresses not apparently assigned to
1338 * it. We force a larger allocation to ensure that nothing gets put too
1339 * close to it.
1340 */
1341static void quirk_dunord(struct pci_dev *dev)
1342{
1343 struct resource *r = &dev->resource[1];
1344
1345 r->flags |= IORESOURCE_UNSET;
1346 resource_set_range(res: r, start: 0, SZ_16M);
1347}
1348DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1349
1350/*
1351 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1352 * decoding (transparent), and does indicate this in the ProgIf.
1353 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1354 */
1355static void quirk_transparent_bridge(struct pci_dev *dev)
1356{
1357 dev->transparent = 1;
1358}
1359DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1360DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1361
1362/*
1363 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1364 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1365 * found at http://www.national.com/analog for info on what these bits do.
1366 * <christer@weinigel.se>
1367 */
1368static void quirk_mediagx_master(struct pci_dev *dev)
1369{
1370 u8 reg;
1371
1372 pci_read_config_byte(dev, where: 0x41, val: &reg);
1373 if (reg & 2) {
1374 reg &= ~2;
1375 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1376 reg);
1377 pci_write_config_byte(dev, where: 0x41, val: reg);
1378 }
1379}
1380DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1381DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1382
1383/*
1384 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1385 * in the odd case it is not the results are corruption hence the presence
1386 * of a Linux check.
1387 */
1388static void quirk_disable_pxb(struct pci_dev *pdev)
1389{
1390 u16 config;
1391
1392 if (pdev->revision != 0x04) /* Only C0 requires this */
1393 return;
1394 pci_read_config_word(dev: pdev, where: 0x40, val: &config);
1395 if (config & (1<<6)) {
1396 config &= ~(1<<6);
1397 pci_write_config_word(dev: pdev, where: 0x40, val: config);
1398 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1399 }
1400}
1401DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1402DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1403
1404static void quirk_amd_ide_mode(struct pci_dev *pdev)
1405{
1406 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1407 u8 tmp;
1408
1409 pci_read_config_byte(dev: pdev, PCI_CLASS_DEVICE, val: &tmp);
1410 if (tmp == 0x01) {
1411 pci_read_config_byte(dev: pdev, where: 0x40, val: &tmp);
1412 pci_write_config_byte(dev: pdev, where: 0x40, val: tmp|1);
1413 pci_write_config_byte(dev: pdev, where: 0x9, val: 1);
1414 pci_write_config_byte(dev: pdev, where: 0xa, val: 6);
1415 pci_write_config_byte(dev: pdev, where: 0x40, val: tmp);
1416
1417 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1418 pci_info(pdev, "set SATA to AHCI mode\n");
1419 }
1420}
1421DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1422DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1423DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1424DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1425DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1426DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1427DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1428DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1429
1430/* Serverworks CSB5 IDE does not fully support native mode */
1431static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1432{
1433 u8 prog;
1434 pci_read_config_byte(dev: pdev, PCI_CLASS_PROG, val: &prog);
1435 if (prog & 5) {
1436 prog &= ~5;
1437 pdev->class &= ~5;
1438 pci_write_config_byte(dev: pdev, PCI_CLASS_PROG, val: prog);
1439 /* PCI layer will sort out resources */
1440 }
1441}
1442DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1443
1444/* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1445static void quirk_ide_samemode(struct pci_dev *pdev)
1446{
1447 u8 prog;
1448
1449 pci_read_config_byte(dev: pdev, PCI_CLASS_PROG, val: &prog);
1450
1451 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1452 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1453 prog &= ~5;
1454 pdev->class &= ~5;
1455 pci_write_config_byte(dev: pdev, PCI_CLASS_PROG, val: prog);
1456 }
1457}
1458DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1459
1460/* Some ATA devices break if put into D3 */
1461static void quirk_no_ata_d3(struct pci_dev *pdev)
1462{
1463 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1464}
1465/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1466DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1467 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1468DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1469 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1470/* ALi loses some register settings that we cannot then restore */
1471DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1472 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1473/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1474 occur when mode detecting */
1475DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1476 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1477
1478/*
1479 * This was originally an Alpha-specific thing, but it really fits here.
1480 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1481 */
1482static void quirk_eisa_bridge(struct pci_dev *dev)
1483{
1484 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1485}
1486DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1487
1488/*
1489 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1490 * is not activated. The myth is that Asus said that they do not want the
1491 * users to be irritated by just another PCI Device in the Win98 device
1492 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1493 * package 2.7.0 for details)
1494 *
1495 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1496 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1497 * becomes necessary to do this tweak in two steps -- the chosen trigger
1498 * is either the Host bridge (preferred) or on-board VGA controller.
1499 *
1500 * Note that we used to unhide the SMBus that way on Toshiba laptops
1501 * (Satellite A40 and Tecra M2) but then found that the thermal management
1502 * was done by SMM code, which could cause unsynchronized concurrent
1503 * accesses to the SMBus registers, with potentially bad effects. Thus you
1504 * should be very careful when adding new entries: if SMM is accessing the
1505 * Intel SMBus, this is a very good reason to leave it hidden.
1506 *
1507 * Likewise, many recent laptops use ACPI for thermal management. If the
1508 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1509 * natively, and keeping the SMBus hidden is the right thing to do. If you
1510 * are about to add an entry in the table below, please first disassemble
1511 * the DSDT and double-check that there is no code accessing the SMBus.
1512 */
1513static int asus_hides_smbus;
1514
1515static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1516{
1517 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1518 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1519 switch (dev->subsystem_device) {
1520 case 0x8025: /* P4B-LX */
1521 case 0x8070: /* P4B */
1522 case 0x8088: /* P4B533 */
1523 case 0x1626: /* L3C notebook */
1524 asus_hides_smbus = 1;
1525 }
1526 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1527 switch (dev->subsystem_device) {
1528 case 0x80b1: /* P4GE-V */
1529 case 0x80b2: /* P4PE */
1530 case 0x8093: /* P4B533-V */
1531 asus_hides_smbus = 1;
1532 }
1533 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1534 switch (dev->subsystem_device) {
1535 case 0x8030: /* P4T533 */
1536 asus_hides_smbus = 1;
1537 }
1538 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1539 switch (dev->subsystem_device) {
1540 case 0x8070: /* P4G8X Deluxe */
1541 asus_hides_smbus = 1;
1542 }
1543 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1544 switch (dev->subsystem_device) {
1545 case 0x80c9: /* PU-DLS */
1546 asus_hides_smbus = 1;
1547 }
1548 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1549 switch (dev->subsystem_device) {
1550 case 0x1751: /* M2N notebook */
1551 case 0x1821: /* M5N notebook */
1552 case 0x1897: /* A6L notebook */
1553 asus_hides_smbus = 1;
1554 }
1555 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1556 switch (dev->subsystem_device) {
1557 case 0x184b: /* W1N notebook */
1558 case 0x186a: /* M6Ne notebook */
1559 asus_hides_smbus = 1;
1560 }
1561 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1562 switch (dev->subsystem_device) {
1563 case 0x80f2: /* P4P800-X */
1564 asus_hides_smbus = 1;
1565 }
1566 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1567 switch (dev->subsystem_device) {
1568 case 0x1882: /* M6V notebook */
1569 case 0x1977: /* A6VA notebook */
1570 asus_hides_smbus = 1;
1571 }
1572 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1573 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1574 switch (dev->subsystem_device) {
1575 case 0x088C: /* HP Compaq nc8000 */
1576 case 0x0890: /* HP Compaq nc6000 */
1577 asus_hides_smbus = 1;
1578 }
1579 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1580 switch (dev->subsystem_device) {
1581 case 0x12bc: /* HP D330L */
1582 case 0x12bd: /* HP D530 */
1583 case 0x006a: /* HP Compaq nx9500 */
1584 asus_hides_smbus = 1;
1585 }
1586 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1587 switch (dev->subsystem_device) {
1588 case 0x12bf: /* HP xw4100 */
1589 asus_hides_smbus = 1;
1590 }
1591 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1592 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1593 switch (dev->subsystem_device) {
1594 case 0xC00C: /* Samsung P35 notebook */
1595 asus_hides_smbus = 1;
1596 }
1597 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1598 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1599 switch (dev->subsystem_device) {
1600 case 0x0058: /* Compaq Evo N620c */
1601 asus_hides_smbus = 1;
1602 }
1603 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1604 switch (dev->subsystem_device) {
1605 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1606 /* Motherboard doesn't have Host bridge
1607 * subvendor/subdevice IDs, therefore checking
1608 * its on-board VGA controller */
1609 asus_hides_smbus = 1;
1610 }
1611 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1612 switch (dev->subsystem_device) {
1613 case 0x00b8: /* Compaq Evo D510 CMT */
1614 case 0x00b9: /* Compaq Evo D510 SFF */
1615 case 0x00ba: /* Compaq Evo D510 USDT */
1616 /* Motherboard doesn't have Host bridge
1617 * subvendor/subdevice IDs and on-board VGA
1618 * controller is disabled if an AGP card is
1619 * inserted, therefore checking USB UHCI
1620 * Controller #1 */
1621 asus_hides_smbus = 1;
1622 }
1623 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1624 switch (dev->subsystem_device) {
1625 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1626 /* Motherboard doesn't have host bridge
1627 * subvendor/subdevice IDs, therefore checking
1628 * its on-board VGA controller */
1629 asus_hides_smbus = 1;
1630 }
1631 }
1632}
1633DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1634DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1635DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1636DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1637DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1638DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1639DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1640DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1641DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1642DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1643
1644DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1645DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1646DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1647
1648static void asus_hides_smbus_lpc(struct pci_dev *dev)
1649{
1650 u16 val;
1651
1652 if (likely(!asus_hides_smbus))
1653 return;
1654
1655 pci_read_config_word(dev, where: 0xF2, val: &val);
1656 if (val & 0x8) {
1657 pci_write_config_word(dev, where: 0xF2, val: val & (~0x8));
1658 pci_read_config_word(dev, where: 0xF2, val: &val);
1659 if (val & 0x8)
1660 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1661 val);
1662 else
1663 pci_info(dev, "Enabled i801 SMBus device\n");
1664 }
1665}
1666DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1667DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1668DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1669DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1670DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1671DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1672DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1673DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1674DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1675DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1676DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1677DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1678DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1679DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1680
1681/* It appears we just have one such device. If not, we have a warning */
1682static void __iomem *asus_rcba_base;
1683static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1684{
1685 u32 rcba;
1686
1687 if (likely(!asus_hides_smbus))
1688 return;
1689 WARN_ON(asus_rcba_base);
1690
1691 pci_read_config_dword(dev, where: 0xF0, val: &rcba);
1692 /* use bits 31:14, 16 kB aligned */
1693 asus_rcba_base = ioremap(offset: rcba & 0xFFFFC000, size: 0x4000);
1694 if (asus_rcba_base == NULL)
1695 return;
1696}
1697
1698static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1699{
1700 u32 val;
1701
1702 if (likely(!asus_hides_smbus || !asus_rcba_base))
1703 return;
1704
1705 /* read the Function Disable register, dword mode only */
1706 val = readl(addr: asus_rcba_base + 0x3418);
1707
1708 /* enable the SMBus device */
1709 writel(val: val & 0xFFFFFFF7, addr: asus_rcba_base + 0x3418);
1710}
1711
1712static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1713{
1714 if (likely(!asus_hides_smbus || !asus_rcba_base))
1715 return;
1716
1717 iounmap(addr: asus_rcba_base);
1718 asus_rcba_base = NULL;
1719 pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1720}
1721
1722static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1723{
1724 asus_hides_smbus_lpc_ich6_suspend(dev);
1725 asus_hides_smbus_lpc_ich6_resume_early(dev);
1726 asus_hides_smbus_lpc_ich6_resume(dev);
1727}
1728DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1729DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1730DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1731DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1732
1733/* SiS 96x south bridge: BIOS typically hides SMBus device... */
1734static void quirk_sis_96x_smbus(struct pci_dev *dev)
1735{
1736 u8 val = 0;
1737 pci_read_config_byte(dev, where: 0x77, val: &val);
1738 if (val & 0x10) {
1739 pci_info(dev, "Enabling SiS 96x SMBus\n");
1740 pci_write_config_byte(dev, where: 0x77, val: val & ~0x10);
1741 }
1742}
1743DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1744DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1745DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1746DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1747DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1748DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1749DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1750DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1751
1752/*
1753 * ... This is further complicated by the fact that some SiS96x south
1754 * bridges pretend to be 85C503/5513 instead. In that case see if we
1755 * spotted a compatible north bridge to make sure.
1756 * (pci_find_device() doesn't work yet)
1757 *
1758 * We can also enable the sis96x bit in the discovery register..
1759 */
1760#define SIS_DETECT_REGISTER 0x40
1761
1762static void quirk_sis_503(struct pci_dev *dev)
1763{
1764 u8 reg;
1765 u16 devid;
1766
1767 pci_read_config_byte(dev, SIS_DETECT_REGISTER, val: &reg);
1768 pci_write_config_byte(dev, SIS_DETECT_REGISTER, val: reg | (1 << 6));
1769 pci_read_config_word(dev, PCI_DEVICE_ID, val: &devid);
1770 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1771 pci_write_config_byte(dev, SIS_DETECT_REGISTER, val: reg);
1772 return;
1773 }
1774
1775 /*
1776 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1777 * it has already been processed. (Depends on link order, which is
1778 * apparently not guaranteed)
1779 */
1780 dev->device = devid;
1781 quirk_sis_96x_smbus(dev);
1782}
1783DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1784DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1785
1786/*
1787 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1788 * and MC97 modem controller are disabled when a second PCI soundcard is
1789 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1790 * -- bjd
1791 */
1792static void asus_hides_ac97_lpc(struct pci_dev *dev)
1793{
1794 u8 val;
1795 int asus_hides_ac97 = 0;
1796
1797 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1798 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1799 asus_hides_ac97 = 1;
1800 }
1801
1802 if (!asus_hides_ac97)
1803 return;
1804
1805 pci_read_config_byte(dev, where: 0x50, val: &val);
1806 if (val & 0xc0) {
1807 pci_write_config_byte(dev, where: 0x50, val: val & (~0xc0));
1808 pci_read_config_byte(dev, where: 0x50, val: &val);
1809 if (val & 0xc0)
1810 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1811 val);
1812 else
1813 pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1814 }
1815}
1816DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1817DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1818
1819#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1820
1821/*
1822 * If we are using libata we can drive this chip properly but must do this
1823 * early on to make the additional device appear during the PCI scanning.
1824 */
1825static void quirk_jmicron_ata(struct pci_dev *pdev)
1826{
1827 u32 conf1, conf5, class;
1828 u8 hdr;
1829
1830 /* Only poke fn 0 */
1831 if (PCI_FUNC(pdev->devfn))
1832 return;
1833
1834 pci_read_config_dword(dev: pdev, where: 0x40, val: &conf1);
1835 pci_read_config_dword(dev: pdev, where: 0x80, val: &conf5);
1836
1837 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1838 conf5 &= ~(1 << 24); /* Clear bit 24 */
1839
1840 switch (pdev->device) {
1841 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1842 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1843 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1844 /* The controller should be in single function ahci mode */
1845 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1846 break;
1847
1848 case PCI_DEVICE_ID_JMICRON_JMB365:
1849 case PCI_DEVICE_ID_JMICRON_JMB366:
1850 /* Redirect IDE second PATA port to the right spot */
1851 conf5 |= (1 << 24);
1852 fallthrough;
1853 case PCI_DEVICE_ID_JMICRON_JMB361:
1854 case PCI_DEVICE_ID_JMICRON_JMB363:
1855 case PCI_DEVICE_ID_JMICRON_JMB369:
1856 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1857 /* Set the class codes correctly and then direct IDE 0 */
1858 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1859 break;
1860
1861 case PCI_DEVICE_ID_JMICRON_JMB368:
1862 /* The controller should be in single function IDE mode */
1863 conf1 |= 0x00C00000; /* Set 22, 23 */
1864 break;
1865 }
1866
1867 pci_write_config_dword(dev: pdev, where: 0x40, val: conf1);
1868 pci_write_config_dword(dev: pdev, where: 0x80, val: conf5);
1869
1870 /* Update pdev accordingly */
1871 pci_read_config_byte(dev: pdev, PCI_HEADER_TYPE, val: &hdr);
1872 pdev->hdr_type = hdr & PCI_HEADER_TYPE_MASK;
1873 pdev->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr);
1874
1875 pci_read_config_dword(dev: pdev, PCI_CLASS_REVISION, val: &class);
1876 pdev->class = class >> 8;
1877}
1878DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1879DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1880DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1881DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1882DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1883DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1884DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1885DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1886DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1887DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1888DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1889DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1890DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1891DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1892DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1893DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1894DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1895DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1896
1897#endif
1898
1899static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1900{
1901 if (dev->multifunction) {
1902 device_disable_async_suspend(dev: &dev->dev);
1903 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1904 }
1905}
1906DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1907DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1908DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1909DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1910
1911#ifdef CONFIG_X86_IO_APIC
1912static void quirk_alder_ioapic(struct pci_dev *pdev)
1913{
1914 int i;
1915
1916 if ((pdev->class >> 8) != 0xff00)
1917 return;
1918
1919 /*
1920 * The first BAR is the location of the IO-APIC... we must
1921 * not touch this (and it's already covered by the fixmap), so
1922 * forcibly insert it into the resource tree.
1923 */
1924 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1925 insert_resource(parent: &iomem_resource, new: &pdev->resource[0]);
1926
1927 /*
1928 * The next five BARs all seem to be rubbish, so just clean
1929 * them out.
1930 */
1931 for (i = 1; i < PCI_STD_NUM_BARS; i++)
1932 memset(s: &pdev->resource[i], c: 0, n: sizeof(pdev->resource[i]));
1933}
1934DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1935#endif
1936
1937static void quirk_no_msi(struct pci_dev *dev)
1938{
1939 pci_info(dev, "avoiding MSI to work around a hardware defect\n");
1940 dev->no_msi = 1;
1941}
1942DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi);
1943DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi);
1944DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi);
1945DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi);
1946DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi);
1947DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi);
1948
1949static void quirk_pcie_mch(struct pci_dev *pdev)
1950{
1951 pdev->no_msi = 1;
1952}
1953DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1954DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1955DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1956
1957DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1958
1959/*
1960 * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are
1961 * actually on the AMBA bus. These fake PCI devices can support SVA via
1962 * SMMU stall feature, by setting dma-can-stall for ACPI platforms.
1963 *
1964 * Normally stalling must not be enabled for PCI devices, since it would
1965 * break the PCI requirement for free-flowing writes and may lead to
1966 * deadlock. We expect PCI devices to support ATS and PRI if they want to
1967 * be fault-tolerant, so there's no ACPI binding to describe anything else,
1968 * even when a "PCI" device turns out to be a regular old SoC device
1969 * dressed up as a RCiEP and normal rules don't apply.
1970 */
1971static void quirk_huawei_pcie_sva(struct pci_dev *pdev)
1972{
1973 struct property_entry properties[] = {
1974 PROPERTY_ENTRY_BOOL("dma-can-stall"),
1975 {},
1976 };
1977
1978 if (pdev->revision != 0x21 && pdev->revision != 0x30)
1979 return;
1980
1981 pdev->pasid_no_tlp = 1;
1982
1983 /*
1984 * Set the dma-can-stall property on ACPI platforms. Device tree
1985 * can set it directly.
1986 */
1987 if (!pdev->dev.of_node &&
1988 device_create_managed_software_node(dev: &pdev->dev, properties, NULL))
1989 pci_warn(pdev, "could not add stall property");
1990}
1991DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva);
1992DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva);
1993DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva);
1994DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva);
1995DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva);
1996DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva);
1997
1998/*
1999 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
2000 * together on certain PXH-based systems.
2001 */
2002static void quirk_pcie_pxh(struct pci_dev *dev)
2003{
2004 dev->no_msi = 1;
2005 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
2006}
2007DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
2008DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
2009DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
2010DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
2011DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
2012
2013/*
2014 * Some Intel PCI Express chipsets have trouble with downstream device
2015 * power management.
2016 */
2017static void quirk_intel_pcie_pm(struct pci_dev *dev)
2018{
2019 pci_pm_d3hot_delay = 120;
2020 dev->no_d1d2 = 1;
2021}
2022DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
2023DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
2024DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
2025DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
2026DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
2027DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
2028DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
2029DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
2030DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
2031DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
2032DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
2033DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
2034DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
2035DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
2036DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
2037DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
2038DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
2039DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
2040DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
2041DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
2042DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
2043
2044static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
2045{
2046 if (dev->d3hot_delay >= delay)
2047 return;
2048
2049 dev->d3hot_delay = delay;
2050 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
2051 dev->d3hot_delay);
2052}
2053
2054static void quirk_radeon_pm(struct pci_dev *dev)
2055{
2056 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
2057 dev->subsystem_device == 0x00e2)
2058 quirk_d3hot_delay(dev, delay: 20);
2059}
2060DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
2061
2062/*
2063 * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus
2064 * reset is performed too soon after transition to D0, extend d3hot_delay
2065 * to previous effective default for all NVIDIA HDA controllers.
2066 */
2067static void quirk_nvidia_hda_pm(struct pci_dev *dev)
2068{
2069 quirk_d3hot_delay(dev, delay: 20);
2070}
2071DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
2072 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8,
2073 quirk_nvidia_hda_pm);
2074
2075/*
2076 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.
2077 * https://bugzilla.kernel.org/show_bug.cgi?id=205587
2078 *
2079 * The kernel attempts to transition these devices to D3cold, but that seems
2080 * to be ineffective on the platforms in question; the PCI device appears to
2081 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
2082 * extended delay in order to succeed.
2083 */
2084static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev)
2085{
2086 quirk_d3hot_delay(dev, delay: 20);
2087}
2088DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
2089DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
2090DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot);
2091
2092#ifdef CONFIG_X86_IO_APIC
2093static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
2094{
2095 noioapicreroute = 1;
2096 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
2097
2098 return 0;
2099}
2100
2101static const struct dmi_system_id boot_interrupt_dmi_table[] = {
2102 /*
2103 * Systems to exclude from boot interrupt reroute quirks
2104 */
2105 {
2106 .callback = dmi_disable_ioapicreroute,
2107 .ident = "ASUSTek Computer INC. M2N-LR",
2108 .matches = {
2109 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
2110 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
2111 },
2112 },
2113 {}
2114};
2115
2116/*
2117 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
2118 * remap the original interrupt in the Linux kernel to the boot interrupt, so
2119 * that a PCI device's interrupt handler is installed on the boot interrupt
2120 * line instead.
2121 */
2122static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
2123{
2124 dmi_check_system(list: boot_interrupt_dmi_table);
2125 if (noioapicquirk || noioapicreroute)
2126 return;
2127
2128 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
2129 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
2130 dev->vendor, dev->device);
2131}
2132DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
2133DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
2134DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
2135DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
2136DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
2137DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
2138DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
2139DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
2140DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
2141DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
2142DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
2143DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
2144DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
2145DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
2146DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
2147DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
2148
2149/*
2150 * On some chipsets we can disable the generation of legacy INTx boot
2151 * interrupts.
2152 */
2153
2154/*
2155 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
2156 * 300641-004US, section 5.7.3.
2157 *
2158 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
2159 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
2160 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
2161 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
2162 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
2163 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
2164 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
2165 * Core IO on Xeon D-1500, see Intel order no 332051-001.
2166 * Core IO on Xeon Scalable, see Intel order no 610950.
2167 */
2168#define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
2169#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
2170
2171#define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
2172#define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25)
2173
2174static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
2175{
2176 u16 pci_config_word;
2177 u32 pci_config_dword;
2178
2179 if (noioapicquirk)
2180 return;
2181
2182 switch (dev->device) {
2183 case PCI_DEVICE_ID_INTEL_ESB_10:
2184 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2185 val: &pci_config_word);
2186 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
2187 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2188 val: pci_config_word);
2189 break;
2190 case 0x3c28: /* Xeon E5 1600/2600/4600 */
2191 case 0x0e28: /* Xeon E5/E7 V2 */
2192 case 0x2f28: /* Xeon E5/E7 V3,V4 */
2193 case 0x6f28: /* Xeon D-1500 */
2194 case 0x2034: /* Xeon Scalable Family */
2195 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2196 val: &pci_config_dword);
2197 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH;
2198 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2199 val: pci_config_dword);
2200 break;
2201 default:
2202 return;
2203 }
2204 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2205 dev->vendor, dev->device);
2206}
2207/*
2208 * Device 29 Func 5 Device IDs of IO-APIC
2209 * containing ABAR—APIC1 Alternate Base Address Register
2210 */
2211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2212 quirk_disable_intel_boot_interrupt);
2213DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2214 quirk_disable_intel_boot_interrupt);
2215
2216/*
2217 * Device 5 Func 0 Device IDs of Core IO modules/hubs
2218 * containing Coherent Interface Protocol Interrupt Control
2219 *
2220 * Device IDs obtained from volume 2 datasheets of commented
2221 * families above.
2222 */
2223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
2224 quirk_disable_intel_boot_interrupt);
2225DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
2226 quirk_disable_intel_boot_interrupt);
2227DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
2228 quirk_disable_intel_boot_interrupt);
2229DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
2230 quirk_disable_intel_boot_interrupt);
2231DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
2232 quirk_disable_intel_boot_interrupt);
2233DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
2234 quirk_disable_intel_boot_interrupt);
2235DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
2236 quirk_disable_intel_boot_interrupt);
2237DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
2238 quirk_disable_intel_boot_interrupt);
2239DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
2240 quirk_disable_intel_boot_interrupt);
2241DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
2242 quirk_disable_intel_boot_interrupt);
2243
2244/* Disable boot interrupts on HT-1000 */
2245#define BC_HT1000_FEATURE_REG 0x64
2246#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
2247#define BC_HT1000_MAP_IDX 0xC00
2248#define BC_HT1000_MAP_DATA 0xC01
2249
2250static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
2251{
2252 u32 pci_config_dword;
2253 u8 irq;
2254
2255 if (noioapicquirk)
2256 return;
2257
2258 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, val: &pci_config_dword);
2259 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, val: pci_config_dword |
2260 BC_HT1000_PIC_REGS_ENABLE);
2261
2262 for (irq = 0x10; irq < 0x10 + 32; irq++) {
2263 outb(value: irq, BC_HT1000_MAP_IDX);
2264 outb(value: 0x00, BC_HT1000_MAP_DATA);
2265 }
2266
2267 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, val: pci_config_dword);
2268
2269 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2270 dev->vendor, dev->device);
2271}
2272DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2273DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2274
2275/* Disable boot interrupts on AMD and ATI chipsets */
2276
2277/*
2278 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2279 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2280 * (due to an erratum).
2281 */
2282#define AMD_813X_MISC 0x40
2283#define AMD_813X_NOIOAMODE (1<<0)
2284#define AMD_813X_REV_B1 0x12
2285#define AMD_813X_REV_B2 0x13
2286
2287static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
2288{
2289 u32 pci_config_dword;
2290
2291 if (noioapicquirk)
2292 return;
2293 if ((dev->revision == AMD_813X_REV_B1) ||
2294 (dev->revision == AMD_813X_REV_B2))
2295 return;
2296
2297 pci_read_config_dword(dev, AMD_813X_MISC, val: &pci_config_dword);
2298 pci_config_dword &= ~AMD_813X_NOIOAMODE;
2299 pci_write_config_dword(dev, AMD_813X_MISC, val: pci_config_dword);
2300
2301 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2302 dev->vendor, dev->device);
2303}
2304DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2305DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2306DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2307DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2308
2309#define AMD_8111_PCI_IRQ_ROUTING 0x56
2310
2311static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
2312{
2313 u16 pci_config_word;
2314
2315 if (noioapicquirk)
2316 return;
2317
2318 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, val: &pci_config_word);
2319 if (!pci_config_word) {
2320 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
2321 dev->vendor, dev->device);
2322 return;
2323 }
2324 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, val: 0);
2325 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2326 dev->vendor, dev->device);
2327}
2328DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2329DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2330#endif /* CONFIG_X86_IO_APIC */
2331
2332/*
2333 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2334 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2335 * Re-allocate the region if needed...
2336 */
2337static void quirk_tc86c001_ide(struct pci_dev *dev)
2338{
2339 struct resource *r = &dev->resource[0];
2340
2341 if (r->start & 0x8) {
2342 r->flags |= IORESOURCE_UNSET;
2343 resource_set_range(res: r, start: 0, SZ_16);
2344 }
2345}
2346DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
2347 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
2348 quirk_tc86c001_ide);
2349
2350/*
2351 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2352 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2353 * being read correctly if bit 7 of the base address is set.
2354 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2355 * Re-allocate the regions to a 256-byte boundary if necessary.
2356 */
2357static void quirk_plx_pci9050(struct pci_dev *dev)
2358{
2359 unsigned int bar;
2360
2361 /* Fixed in revision 2 (PCI 9052). */
2362 if (dev->revision >= 2)
2363 return;
2364 for (bar = 0; bar <= 1; bar++)
2365 if (pci_resource_len(dev, bar) == 0x80 &&
2366 (pci_resource_start(dev, bar) & 0x80)) {
2367 struct resource *r = &dev->resource[bar];
2368 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2369 bar);
2370 r->flags |= IORESOURCE_UNSET;
2371 resource_set_range(res: r, start: 0, SZ_256);
2372 }
2373}
2374DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2375 quirk_plx_pci9050);
2376/*
2377 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2378 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2379 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2380 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2381 *
2382 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2383 * driver.
2384 */
2385DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2386DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2387
2388static void quirk_netmos(struct pci_dev *dev)
2389{
2390 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
2391 unsigned int num_serial = dev->subsystem_device & 0xf;
2392
2393 /*
2394 * These Netmos parts are multiport serial devices with optional
2395 * parallel ports. Even when parallel ports are present, they
2396 * are identified as class SERIAL, which means the serial driver
2397 * will claim them. To prevent this, mark them as class OTHER.
2398 * These combo devices should be claimed by parport_serial.
2399 *
2400 * The subdevice ID is of the form 0x00PS, where <P> is the number
2401 * of parallel ports and <S> is the number of serial ports.
2402 */
2403 switch (dev->device) {
2404 case PCI_DEVICE_ID_NETMOS_9835:
2405 /* Well, this rule doesn't hold for the following 9835 device */
2406 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
2407 dev->subsystem_device == 0x0299)
2408 return;
2409 fallthrough;
2410 case PCI_DEVICE_ID_NETMOS_9735:
2411 case PCI_DEVICE_ID_NETMOS_9745:
2412 case PCI_DEVICE_ID_NETMOS_9845:
2413 case PCI_DEVICE_ID_NETMOS_9855:
2414 if (num_parallel) {
2415 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2416 dev->device, num_parallel, num_serial);
2417 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
2418 (dev->class & 0xff);
2419 }
2420 }
2421}
2422DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
2423 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
2424
2425static void quirk_e100_interrupt(struct pci_dev *dev)
2426{
2427 u16 command, pmcsr;
2428 u8 __iomem *csr;
2429 u8 cmd_hi;
2430
2431 switch (dev->device) {
2432 /* PCI IDs taken from drivers/net/e100.c */
2433 case 0x1029:
2434 case 0x1030 ... 0x1034:
2435 case 0x1038 ... 0x103E:
2436 case 0x1050 ... 0x1057:
2437 case 0x1059:
2438 case 0x1064 ... 0x106B:
2439 case 0x1091 ... 0x1095:
2440 case 0x1209:
2441 case 0x1229:
2442 case 0x2449:
2443 case 0x2459:
2444 case 0x245D:
2445 case 0x27DC:
2446 break;
2447 default:
2448 return;
2449 }
2450
2451 /*
2452 * Some firmware hands off the e100 with interrupts enabled,
2453 * which can cause a flood of interrupts if packets are
2454 * received before the driver attaches to the device. So
2455 * disable all e100 interrupts here. The driver will
2456 * re-enable them when it's ready.
2457 */
2458 pci_read_config_word(dev, PCI_COMMAND, val: &command);
2459
2460 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2461 return;
2462
2463 /*
2464 * Check that the device is in the D0 power state. If it's not,
2465 * there is no point to look any further.
2466 */
2467 if (dev->pm_cap) {
2468 pci_read_config_word(dev, where: dev->pm_cap + PCI_PM_CTRL, val: &pmcsr);
2469 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2470 return;
2471 }
2472
2473 /* Convert from PCI bus to resource space. */
2474 csr = ioremap(pci_resource_start(dev, 0), size: 8);
2475 if (!csr) {
2476 pci_warn(dev, "Can't map e100 registers\n");
2477 return;
2478 }
2479
2480 cmd_hi = readb(addr: csr + 3);
2481 if (cmd_hi == 0) {
2482 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2483 writeb(val: 1, addr: csr + 3);
2484 }
2485
2486 iounmap(addr: csr);
2487}
2488DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2489 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2490
2491/*
2492 * The 82575 and 82598 may experience data corruption issues when transitioning
2493 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2494 */
2495static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2496{
2497 pci_info(dev, "Disabling L0s\n");
2498 pci_disable_link_state(pdev: dev, PCIE_LINK_STATE_L0S);
2499}
2500DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2501DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2502DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2503DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2504DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2505DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2506DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2507DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2508DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2509DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2510DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2511DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2512DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2513DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2514
2515static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
2516{
2517 pci_info(dev, "Disabling ASPM L0s/L1\n");
2518 pci_disable_link_state(pdev: dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
2519}
2520
2521/*
2522 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2523 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2524 * disable both L0s and L1 for now to be safe.
2525 */
2526DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2527
2528/*
2529 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2530 * Link bit cleared after starting the link retrain process to allow this
2531 * process to finish.
2532 *
2533 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2534 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2535 */
2536static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
2537{
2538 dev->clear_retrain_link = 1;
2539 pci_info(dev, "Enable PCIe Retrain Link quirk\n");
2540}
2541DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link);
2542DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link);
2543DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link);
2544
2545static void fixup_rev1_53c810(struct pci_dev *dev)
2546{
2547 u32 class = dev->class;
2548
2549 /*
2550 * rev 1 ncr53c810 chips don't set the class at all which means
2551 * they don't get their resources remapped. Fix that here.
2552 */
2553 if (class)
2554 return;
2555
2556 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2557 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2558 class, dev->class);
2559}
2560DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2561
2562/* Enable 1k I/O space granularity on the Intel P64H2 */
2563static void quirk_p64h2_1k_io(struct pci_dev *dev)
2564{
2565 u16 en1k;
2566
2567 pci_read_config_word(dev, where: 0x40, val: &en1k);
2568
2569 if (en1k & 0x200) {
2570 pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2571 dev->io_window_1k = 1;
2572 }
2573}
2574DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2575
2576/*
2577 * Under some circumstances, AER is not linked with extended capabilities.
2578 * Force it to be linked by setting the corresponding control bit in the
2579 * config space.
2580 */
2581static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2582{
2583 uint8_t b;
2584
2585 if (pci_read_config_byte(dev, where: 0xf41, val: &b) == 0) {
2586 if (!(b & 0x20)) {
2587 pci_write_config_byte(dev, where: 0xf41, val: b | 0x20);
2588 pci_info(dev, "Linking AER extended capability\n");
2589 }
2590 }
2591}
2592DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2593 quirk_nvidia_ck804_pcie_aer_ext_cap);
2594DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2595 quirk_nvidia_ck804_pcie_aer_ext_cap);
2596
2597static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2598{
2599 /*
2600 * Disable PCI Bus Parking and PCI Master read caching on CX700
2601 * which causes unspecified timing errors with a VT6212L on the PCI
2602 * bus leading to USB2.0 packet loss.
2603 *
2604 * This quirk is only enabled if a second (on the external PCI bus)
2605 * VT6212L is found -- the CX700 core itself also contains a USB
2606 * host controller with the same PCI ID as the VT6212L.
2607 */
2608
2609 /* Count VT6212L instances */
2610 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2611 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2612 uint8_t b;
2613
2614 /*
2615 * p should contain the first (internal) VT6212L -- see if we have
2616 * an external one by searching again.
2617 */
2618 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, from: p);
2619 if (!p)
2620 return;
2621 pci_dev_put(dev: p);
2622
2623 if (pci_read_config_byte(dev, where: 0x76, val: &b) == 0) {
2624 if (b & 0x40) {
2625 /* Turn off PCI Bus Parking */
2626 pci_write_config_byte(dev, where: 0x76, val: b ^ 0x40);
2627
2628 pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2629 }
2630 }
2631
2632 if (pci_read_config_byte(dev, where: 0x72, val: &b) == 0) {
2633 if (b != 0) {
2634 /* Turn off PCI Master read caching */
2635 pci_write_config_byte(dev, where: 0x72, val: 0x0);
2636
2637 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2638 pci_write_config_byte(dev, where: 0x75, val: 0x1);
2639
2640 /* Disable "Read FIFO Timer" */
2641 pci_write_config_byte(dev, where: 0x77, val: 0x0);
2642
2643 pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2644 }
2645 }
2646}
2647DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2648
2649static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2650{
2651 u32 rev;
2652
2653 pci_read_config_dword(dev, where: 0xf4, val: &rev);
2654
2655 /* Only CAP the MRRS if the device is a 5719 A0 */
2656 if (rev == 0x05719000) {
2657 int readrq = pcie_get_readrq(dev);
2658 if (readrq > 2048)
2659 pcie_set_readrq(dev, rq: 2048);
2660 }
2661}
2662DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2663 PCI_DEVICE_ID_TIGON3_5719,
2664 quirk_brcm_5719_limit_mrrs);
2665
2666/*
2667 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2668 * hide device 6 which configures the overflow device access containing the
2669 * DRBs - this is where we expose device 6.
2670 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2671 */
2672static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2673{
2674 u8 reg;
2675
2676 if (pci_read_config_byte(dev, where: 0xF4, val: &reg) == 0 && !(reg & 0x02)) {
2677 pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2678 pci_write_config_byte(dev, where: 0xF4, val: reg | 0x02);
2679 }
2680}
2681DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2682 quirk_unhide_mch_dev6);
2683DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2684 quirk_unhide_mch_dev6);
2685
2686#ifdef CONFIG_PCI_MSI
2687/*
2688 * Some chipsets do not support MSI. We cannot easily rely on setting
2689 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2690 * other buses controlled by the chipset even if Linux is not aware of it.
2691 * Instead of setting the flag on all buses in the machine, simply disable
2692 * MSI globally.
2693 */
2694static void quirk_disable_all_msi(struct pci_dev *dev)
2695{
2696 pci_no_msi();
2697 pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2698}
2699DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2700DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2701DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2702DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2703DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2704DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2705DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2706DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2707DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi);
2708
2709/* Disable MSI on chipsets that are known to not support it */
2710static void quirk_disable_msi(struct pci_dev *dev)
2711{
2712 if (dev->subordinate) {
2713 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2714 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2715 }
2716}
2717DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2718DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2719DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2720DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RDC, 0x1031, quirk_disable_msi);
2721
2722/*
2723 * The APC bridge device in AMD 780 family northbridges has some random
2724 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2725 * we use the possible vendor/device IDs of the host bridge for the
2726 * declared quirk, and search for the APC bridge by slot number.
2727 */
2728static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2729{
2730 struct pci_dev *apc_bridge;
2731
2732 apc_bridge = pci_get_slot(bus: host_bridge->bus, PCI_DEVFN(1, 0));
2733 if (apc_bridge) {
2734 if (apc_bridge->device == 0x9602)
2735 quirk_disable_msi(dev: apc_bridge);
2736 pci_dev_put(dev: apc_bridge);
2737 }
2738}
2739DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2740DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2741
2742/*
2743 * Go through the list of HyperTransport capabilities and return 1 if a HT
2744 * MSI capability is found and enabled.
2745 */
2746static int msi_ht_cap_enabled(struct pci_dev *dev)
2747{
2748 int pos, ttl = PCI_FIND_CAP_TTL;
2749
2750 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2751 while (pos && ttl--) {
2752 u8 flags;
2753
2754 if (pci_read_config_byte(dev, where: pos + HT_MSI_FLAGS,
2755 val: &flags) == 0) {
2756 pci_info(dev, "Found %s HT MSI Mapping\n",
2757 flags & HT_MSI_FLAGS_ENABLE ?
2758 "enabled" : "disabled");
2759 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2760 }
2761
2762 pos = pci_find_next_ht_capability(dev, pos,
2763 HT_CAPTYPE_MSI_MAPPING);
2764 }
2765 return 0;
2766}
2767
2768/* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2769static void quirk_msi_ht_cap(struct pci_dev *dev)
2770{
2771 if (!msi_ht_cap_enabled(dev))
2772 quirk_disable_msi(dev);
2773}
2774DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2775 quirk_msi_ht_cap);
2776
2777/*
2778 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2779 * if the MSI capability is set in any of these mappings.
2780 */
2781static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2782{
2783 struct pci_dev *pdev;
2784
2785 /*
2786 * Check HT MSI cap on this chipset and the root one. A single one
2787 * having MSI is enough to be sure that MSI is supported.
2788 */
2789 pdev = pci_get_slot(bus: dev->bus, devfn: 0);
2790 if (!pdev)
2791 return;
2792 if (!msi_ht_cap_enabled(dev: pdev))
2793 quirk_msi_ht_cap(dev);
2794 pci_dev_put(dev: pdev);
2795}
2796DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2797 quirk_nvidia_ck804_msi_ht_cap);
2798
2799/* Force enable MSI mapping capability on HT bridges */
2800static void ht_enable_msi_mapping(struct pci_dev *dev)
2801{
2802 int pos, ttl = PCI_FIND_CAP_TTL;
2803
2804 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2805 while (pos && ttl--) {
2806 u8 flags;
2807
2808 if (pci_read_config_byte(dev, where: pos + HT_MSI_FLAGS,
2809 val: &flags) == 0) {
2810 pci_info(dev, "Enabling HT MSI Mapping\n");
2811
2812 pci_write_config_byte(dev, where: pos + HT_MSI_FLAGS,
2813 val: flags | HT_MSI_FLAGS_ENABLE);
2814 }
2815 pos = pci_find_next_ht_capability(dev, pos,
2816 HT_CAPTYPE_MSI_MAPPING);
2817 }
2818}
2819DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2820 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2821 ht_enable_msi_mapping);
2822DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2823 ht_enable_msi_mapping);
2824
2825/*
2826 * The P5N32-SLI motherboards from Asus have a problem with MSI
2827 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2828 * also affects other devices. As for now, turn off MSI for this device.
2829 */
2830static void nvenet_msi_disable(struct pci_dev *dev)
2831{
2832 const char *board_name = dmi_get_system_info(field: DMI_BOARD_NAME);
2833
2834 if (board_name &&
2835 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2836 strstr(board_name, "P5N32-E SLI"))) {
2837 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2838 dev->no_msi = 1;
2839 }
2840}
2841DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2842 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2843 nvenet_msi_disable);
2844
2845/*
2846 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device
2847 * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI
2848 * interrupts for PME and AER events; instead only INTx interrupts are
2849 * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts
2850 * for other events, since PCIe specification doesn't support using a mix of
2851 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2852 * service drivers registering their respective ISRs for MSIs.
2853 */
2854static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
2855{
2856 dev->no_msi = 1;
2857}
2858DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2859 PCI_CLASS_BRIDGE_PCI, 8,
2860 pci_quirk_nvidia_tegra_disable_rp_msi);
2861DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2862 PCI_CLASS_BRIDGE_PCI, 8,
2863 pci_quirk_nvidia_tegra_disable_rp_msi);
2864DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2865 PCI_CLASS_BRIDGE_PCI, 8,
2866 pci_quirk_nvidia_tegra_disable_rp_msi);
2867DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2868 PCI_CLASS_BRIDGE_PCI, 8,
2869 pci_quirk_nvidia_tegra_disable_rp_msi);
2870DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2871 PCI_CLASS_BRIDGE_PCI, 8,
2872 pci_quirk_nvidia_tegra_disable_rp_msi);
2873DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2874 PCI_CLASS_BRIDGE_PCI, 8,
2875 pci_quirk_nvidia_tegra_disable_rp_msi);
2876DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2877 PCI_CLASS_BRIDGE_PCI, 8,
2878 pci_quirk_nvidia_tegra_disable_rp_msi);
2879DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2880 PCI_CLASS_BRIDGE_PCI, 8,
2881 pci_quirk_nvidia_tegra_disable_rp_msi);
2882DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2883 PCI_CLASS_BRIDGE_PCI, 8,
2884 pci_quirk_nvidia_tegra_disable_rp_msi);
2885DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2886 PCI_CLASS_BRIDGE_PCI, 8,
2887 pci_quirk_nvidia_tegra_disable_rp_msi);
2888DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2889 PCI_CLASS_BRIDGE_PCI, 8,
2890 pci_quirk_nvidia_tegra_disable_rp_msi);
2891DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2892 PCI_CLASS_BRIDGE_PCI, 8,
2893 pci_quirk_nvidia_tegra_disable_rp_msi);
2894DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2895 PCI_CLASS_BRIDGE_PCI, 8,
2896 pci_quirk_nvidia_tegra_disable_rp_msi);
2897DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a,
2898 PCI_CLASS_BRIDGE_PCI, 8,
2899 pci_quirk_nvidia_tegra_disable_rp_msi);
2900DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c,
2901 PCI_CLASS_BRIDGE_PCI, 8,
2902 pci_quirk_nvidia_tegra_disable_rp_msi);
2903DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e,
2904 PCI_CLASS_BRIDGE_PCI, 8,
2905 pci_quirk_nvidia_tegra_disable_rp_msi);
2906
2907/*
2908 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2909 * config register. This register controls the routing of legacy
2910 * interrupts from devices that route through the MCP55. If this register
2911 * is misprogrammed, interrupts are only sent to the BSP, unlike
2912 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2913 * having this register set properly prevents kdump from booting up
2914 * properly, so let's make sure that we have it set correctly.
2915 * Note that this is an undocumented register.
2916 */
2917static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2918{
2919 u32 cfg;
2920
2921 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2922 return;
2923
2924 pci_read_config_dword(dev, where: 0x74, val: &cfg);
2925
2926 if (cfg & ((1 << 2) | (1 << 15))) {
2927 pr_info("Rewriting IRQ routing register on MCP55\n");
2928 cfg &= ~((1 << 2) | (1 << 15));
2929 pci_write_config_dword(dev, where: 0x74, val: cfg);
2930 }
2931}
2932DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2933 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2934 nvbridge_check_legacy_irq_routing);
2935DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2936 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2937 nvbridge_check_legacy_irq_routing);
2938
2939static int ht_check_msi_mapping(struct pci_dev *dev)
2940{
2941 int pos, ttl = PCI_FIND_CAP_TTL;
2942 int found = 0;
2943
2944 /* Check if there is HT MSI cap or enabled on this device */
2945 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2946 while (pos && ttl--) {
2947 u8 flags;
2948
2949 if (found < 1)
2950 found = 1;
2951 if (pci_read_config_byte(dev, where: pos + HT_MSI_FLAGS,
2952 val: &flags) == 0) {
2953 if (flags & HT_MSI_FLAGS_ENABLE) {
2954 if (found < 2) {
2955 found = 2;
2956 break;
2957 }
2958 }
2959 }
2960 pos = pci_find_next_ht_capability(dev, pos,
2961 HT_CAPTYPE_MSI_MAPPING);
2962 }
2963
2964 return found;
2965}
2966
2967static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2968{
2969 struct pci_dev *dev;
2970 int pos;
2971 int i, dev_no;
2972 int found = 0;
2973
2974 dev_no = host_bridge->devfn >> 3;
2975 for (i = dev_no + 1; i < 0x20; i++) {
2976 dev = pci_get_slot(bus: host_bridge->bus, PCI_DEVFN(i, 0));
2977 if (!dev)
2978 continue;
2979
2980 /* found next host bridge? */
2981 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2982 if (pos != 0) {
2983 pci_dev_put(dev);
2984 break;
2985 }
2986
2987 if (ht_check_msi_mapping(dev)) {
2988 found = 1;
2989 pci_dev_put(dev);
2990 break;
2991 }
2992 pci_dev_put(dev);
2993 }
2994
2995 return found;
2996}
2997
2998#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2999#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
3000
3001static int is_end_of_ht_chain(struct pci_dev *dev)
3002{
3003 int pos, ctrl_off;
3004 int end = 0;
3005 u16 flags, ctrl;
3006
3007 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
3008
3009 if (!pos)
3010 goto out;
3011
3012 pci_read_config_word(dev, where: pos + PCI_CAP_FLAGS, val: &flags);
3013
3014 ctrl_off = ((flags >> 10) & 1) ?
3015 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
3016 pci_read_config_word(dev, where: pos + ctrl_off, val: &ctrl);
3017
3018 if (ctrl & (1 << 6))
3019 end = 1;
3020
3021out:
3022 return end;
3023}
3024
3025static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
3026{
3027 struct pci_dev *host_bridge;
3028 int pos;
3029 int i, dev_no;
3030 int found = 0;
3031
3032 dev_no = dev->devfn >> 3;
3033 for (i = dev_no; i >= 0; i--) {
3034 host_bridge = pci_get_slot(bus: dev->bus, PCI_DEVFN(i, 0));
3035 if (!host_bridge)
3036 continue;
3037
3038 pos = pci_find_ht_capability(dev: host_bridge, HT_CAPTYPE_SLAVE);
3039 if (pos != 0) {
3040 found = 1;
3041 break;
3042 }
3043 pci_dev_put(dev: host_bridge);
3044 }
3045
3046 if (!found)
3047 return;
3048
3049 /* don't enable end_device/host_bridge with leaf directly here */
3050 if (host_bridge == dev && is_end_of_ht_chain(dev: host_bridge) &&
3051 host_bridge_with_leaf(host_bridge))
3052 goto out;
3053
3054 /* root did that ! */
3055 if (msi_ht_cap_enabled(dev: host_bridge))
3056 goto out;
3057
3058 ht_enable_msi_mapping(dev);
3059
3060out:
3061 pci_dev_put(dev: host_bridge);
3062}
3063
3064static void ht_disable_msi_mapping(struct pci_dev *dev)
3065{
3066 int pos, ttl = PCI_FIND_CAP_TTL;
3067
3068 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
3069 while (pos && ttl--) {
3070 u8 flags;
3071
3072 if (pci_read_config_byte(dev, where: pos + HT_MSI_FLAGS,
3073 val: &flags) == 0) {
3074 pci_info(dev, "Disabling HT MSI Mapping\n");
3075
3076 pci_write_config_byte(dev, where: pos + HT_MSI_FLAGS,
3077 val: flags & ~HT_MSI_FLAGS_ENABLE);
3078 }
3079 pos = pci_find_next_ht_capability(dev, pos,
3080 HT_CAPTYPE_MSI_MAPPING);
3081 }
3082}
3083
3084static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
3085{
3086 struct pci_dev *host_bridge;
3087 int pos;
3088 int found;
3089
3090 if (!pci_msi_enabled())
3091 return;
3092
3093 /* check if there is HT MSI cap or enabled on this device */
3094 found = ht_check_msi_mapping(dev);
3095
3096 /* no HT MSI CAP */
3097 if (found == 0)
3098 return;
3099
3100 /*
3101 * HT MSI mapping should be disabled on devices that are below
3102 * a non-HyperTransport host bridge. Locate the host bridge.
3103 */
3104 host_bridge = pci_get_domain_bus_and_slot(domain: pci_domain_nr(bus: dev->bus), bus: 0,
3105 PCI_DEVFN(0, 0));
3106 if (host_bridge == NULL) {
3107 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
3108 return;
3109 }
3110
3111 pos = pci_find_ht_capability(dev: host_bridge, HT_CAPTYPE_SLAVE);
3112 if (pos != 0) {
3113 /* Host bridge is to HT */
3114 if (found == 1) {
3115 /* it is not enabled, try to enable it */
3116 if (all)
3117 ht_enable_msi_mapping(dev);
3118 else
3119 nv_ht_enable_msi_mapping(dev);
3120 }
3121 goto out;
3122 }
3123
3124 /* HT MSI is not enabled */
3125 if (found == 1)
3126 goto out;
3127
3128 /* Host bridge is not to HT, disable HT MSI mapping on this device */
3129 ht_disable_msi_mapping(dev);
3130
3131out:
3132 pci_dev_put(dev: host_bridge);
3133}
3134
3135static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
3136{
3137 return __nv_msi_ht_cap_quirk(dev, all: 1);
3138}
3139DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
3140DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
3141
3142static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
3143{
3144 return __nv_msi_ht_cap_quirk(dev, all: 0);
3145}
3146DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
3147DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
3148
3149static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
3150{
3151 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3152}
3153
3154static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
3155{
3156 struct pci_dev *p;
3157
3158 /*
3159 * SB700 MSI issue will be fixed at HW level from revision A21;
3160 * we need check PCI REVISION ID of SMBus controller to get SB700
3161 * revision.
3162 */
3163 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3164 NULL);
3165 if (!p)
3166 return;
3167
3168 if ((p->revision < 0x3B) && (p->revision >= 0x30))
3169 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3170 pci_dev_put(dev: p);
3171}
3172
3173static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
3174{
3175 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
3176 if (dev->revision < 0x18) {
3177 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
3178 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3179 }
3180}
3181DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3182 PCI_DEVICE_ID_TIGON3_5780,
3183 quirk_msi_intx_disable_bug);
3184DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3185 PCI_DEVICE_ID_TIGON3_5780S,
3186 quirk_msi_intx_disable_bug);
3187DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3188 PCI_DEVICE_ID_TIGON3_5714,
3189 quirk_msi_intx_disable_bug);
3190DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3191 PCI_DEVICE_ID_TIGON3_5714S,
3192 quirk_msi_intx_disable_bug);
3193DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3194 PCI_DEVICE_ID_TIGON3_5715,
3195 quirk_msi_intx_disable_bug);
3196DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3197 PCI_DEVICE_ID_TIGON3_5715S,
3198 quirk_msi_intx_disable_bug);
3199
3200DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
3201 quirk_msi_intx_disable_ati_bug);
3202DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
3203 quirk_msi_intx_disable_ati_bug);
3204DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
3205 quirk_msi_intx_disable_ati_bug);
3206DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
3207 quirk_msi_intx_disable_ati_bug);
3208DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
3209 quirk_msi_intx_disable_ati_bug);
3210
3211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
3212 quirk_msi_intx_disable_bug);
3213DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
3214 quirk_msi_intx_disable_bug);
3215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
3216 quirk_msi_intx_disable_bug);
3217
3218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
3219 quirk_msi_intx_disable_bug);
3220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
3221 quirk_msi_intx_disable_bug);
3222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
3223 quirk_msi_intx_disable_bug);
3224DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
3225 quirk_msi_intx_disable_bug);
3226DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
3227 quirk_msi_intx_disable_bug);
3228DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
3229 quirk_msi_intx_disable_bug);
3230DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
3231 quirk_msi_intx_disable_qca_bug);
3232DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
3233 quirk_msi_intx_disable_qca_bug);
3234DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
3235 quirk_msi_intx_disable_qca_bug);
3236DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
3237 quirk_msi_intx_disable_qca_bug);
3238DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
3239 quirk_msi_intx_disable_qca_bug);
3240
3241/*
3242 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3243 * should be disabled on platforms where the device (mistakenly) advertises it.
3244 *
3245 * Notice that this quirk also disables MSI (which may work, but hasn't been
3246 * tested), since currently there is no standard way to disable only MSI-X.
3247 *
3248 * The 0031 device id is reused for other non Root Port device types,
3249 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
3250 */
3251static void quirk_al_msi_disable(struct pci_dev *dev)
3252{
3253 dev->no_msi = 1;
3254 pci_warn(dev, "Disabling MSI/MSI-X\n");
3255}
3256DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
3257 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
3258#endif /* CONFIG_PCI_MSI */
3259
3260/*
3261 * Allow manual resource allocation for PCI hotplug bridges via
3262 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3263 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
3264 * allocate resources when hotplug device is inserted and PCI bus is
3265 * rescanned.
3266 */
3267static void quirk_hotplug_bridge(struct pci_dev *dev)
3268{
3269 dev->is_hotplug_bridge = 1;
3270}
3271DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3272
3273/*
3274 * This is a quirk for the Ricoh MMC controller found as a part of some
3275 * multifunction chips.
3276 *
3277 * This is very similar and based on the ricoh_mmc driver written by
3278 * Philip Langdale. Thank you for these magic sequences.
3279 *
3280 * These chips implement the four main memory card controllers (SD, MMC,
3281 * MS, xD) and one or both of CardBus or FireWire.
3282 *
3283 * It happens that they implement SD and MMC support as separate
3284 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3285 * cards but the chip detects MMC cards in hardware and directs them to the
3286 * MMC controller - so the SDHCI driver never sees them.
3287 *
3288 * To get around this, we must disable the useless MMC controller. At that
3289 * point, the SDHCI controller will start seeing them. It seems to be the
3290 * case that the relevant PCI registers to deactivate the MMC controller
3291 * live on PCI function 0, which might be the CardBus controller or the
3292 * FireWire controller, depending on the particular chip in question
3293 *
3294 * This has to be done early, because as soon as we disable the MMC controller
3295 * other PCI functions shift up one level, e.g. function #2 becomes function
3296 * #1, and this will confuse the PCI core.
3297 */
3298#ifdef CONFIG_MMC_RICOH_MMC
3299static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
3300{
3301 u8 write_enable;
3302 u8 write_target;
3303 u8 disable;
3304
3305 /*
3306 * Disable via CardBus interface
3307 *
3308 * This must be done via function #0
3309 */
3310 if (PCI_FUNC(dev->devfn))
3311 return;
3312
3313 pci_read_config_byte(dev, 0xB7, &disable);
3314 if (disable & 0x02)
3315 return;
3316
3317 pci_read_config_byte(dev, 0x8E, &write_enable);
3318 pci_write_config_byte(dev, 0x8E, 0xAA);
3319 pci_read_config_byte(dev, 0x8D, &write_target);
3320 pci_write_config_byte(dev, 0x8D, 0xB7);
3321 pci_write_config_byte(dev, 0xB7, disable | 0x02);
3322 pci_write_config_byte(dev, 0x8E, write_enable);
3323 pci_write_config_byte(dev, 0x8D, write_target);
3324
3325 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3326 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3327}
3328DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3329DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3330
3331static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
3332{
3333 u8 write_enable;
3334 u8 disable;
3335
3336 /*
3337 * Disable via FireWire interface
3338 *
3339 * This must be done via function #0
3340 */
3341 if (PCI_FUNC(dev->devfn))
3342 return;
3343 /*
3344 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3345 * certain types of SD/MMC cards. Lowering the SD base clock
3346 * frequency from 200Mhz to 50Mhz fixes this issue.
3347 *
3348 * 0x150 - SD2.0 mode enable for changing base clock
3349 * frequency to 50Mhz
3350 * 0xe1 - Base clock frequency
3351 * 0x32 - 50Mhz new clock frequency
3352 * 0xf9 - Key register for 0x150
3353 * 0xfc - key register for 0xe1
3354 */
3355 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
3356 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
3357 pci_write_config_byte(dev, 0xf9, 0xfc);
3358 pci_write_config_byte(dev, 0x150, 0x10);
3359 pci_write_config_byte(dev, 0xf9, 0x00);
3360 pci_write_config_byte(dev, 0xfc, 0x01);
3361 pci_write_config_byte(dev, 0xe1, 0x32);
3362 pci_write_config_byte(dev, 0xfc, 0x00);
3363
3364 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
3365 }
3366
3367 pci_read_config_byte(dev, 0xCB, &disable);
3368
3369 if (disable & 0x02)
3370 return;
3371
3372 pci_read_config_byte(dev, 0xCA, &write_enable);
3373 pci_write_config_byte(dev, 0xCA, 0x57);
3374 pci_write_config_byte(dev, 0xCB, disable | 0x02);
3375 pci_write_config_byte(dev, 0xCA, write_enable);
3376
3377 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3378 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3379
3380}
3381DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3382DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3383DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3384DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3385DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3386DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3387#endif /*CONFIG_MMC_RICOH_MMC*/
3388
3389#ifdef CONFIG_DMAR_TABLE
3390#define VTUNCERRMSK_REG 0x1ac
3391#define VTD_MSK_SPEC_ERRORS (1 << 31)
3392/*
3393 * This is a quirk for masking VT-d spec-defined errors to platform error
3394 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3395 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3396 * on the RAS config settings of the platform) when a VT-d fault happens.
3397 * The resulting SMI caused the system to hang.
3398 *
3399 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3400 * need to report the same error through other channels.
3401 */
3402static void vtd_mask_spec_errors(struct pci_dev *dev)
3403{
3404 u32 word;
3405
3406 pci_read_config_dword(dev, VTUNCERRMSK_REG, val: &word);
3407 pci_write_config_dword(dev, VTUNCERRMSK_REG, val: word | VTD_MSK_SPEC_ERRORS);
3408}
3409DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3410DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3411#endif
3412
3413static void fixup_ti816x_class(struct pci_dev *dev)
3414{
3415 u32 class = dev->class;
3416
3417 /* TI 816x devices do not have class code set when in PCIe boot mode */
3418 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3419 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
3420 class, dev->class);
3421}
3422DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3423 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3424
3425/*
3426 * Some PCIe devices do not work reliably with the claimed maximum
3427 * payload size supported.
3428 */
3429static void fixup_mpss_256(struct pci_dev *dev)
3430{
3431 dev->pcie_mpss = 1; /* 256 bytes */
3432}
3433DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3434 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3435DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3436 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3437DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3438 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3439DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
3440
3441/*
3442 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3443 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3444 * Since there is no way of knowing what the PCIe MPS on each fabric will be
3445 * until all of the devices are discovered and buses walked, read completion
3446 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3447 * it is possible to hotplug a device with MPS of 256B.
3448 */
3449static void quirk_intel_mc_errata(struct pci_dev *dev)
3450{
3451 int err;
3452 u16 rcc;
3453
3454 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3455 pcie_bus_config == PCIE_BUS_DEFAULT)
3456 return;
3457
3458 /*
3459 * Intel erratum specifies bits to change but does not say what
3460 * they are. Keeping them magical until such time as the registers
3461 * and values can be explained.
3462 */
3463 err = pci_read_config_word(dev, where: 0x48, val: &rcc);
3464 if (err) {
3465 pci_err(dev, "Error attempting to read the read completion coalescing register\n");
3466 return;
3467 }
3468
3469 if (!(rcc & (1 << 10)))
3470 return;
3471
3472 rcc &= ~(1 << 10);
3473
3474 err = pci_write_config_word(dev, where: 0x48, val: rcc);
3475 if (err) {
3476 pci_err(dev, "Error attempting to write the read completion coalescing register\n");
3477 return;
3478 }
3479
3480 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3481}
3482/* Intel 5000 series memory controllers and ports 2-7 */
3483DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3484DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3485DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3486DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3487DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3488DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3489DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3490DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3491DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3492DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3493DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3494DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3495DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3496DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3497/* Intel 5100 series memory controllers and ports 2-7 */
3498DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3499DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3500DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3501DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3502DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3503DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3504DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3505DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3506DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3507DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3508DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3509
3510/*
3511 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3512 * To work around this, query the size it should be configured to by the
3513 * device and modify the resource end to correspond to this new size.
3514 */
3515static void quirk_intel_ntb(struct pci_dev *dev)
3516{
3517 int rc;
3518 u8 val;
3519
3520 rc = pci_read_config_byte(dev, where: 0x00D0, val: &val);
3521 if (rc)
3522 return;
3523
3524 resource_set_size(res: &dev->resource[2], size: (resource_size_t)1 << val);
3525
3526 rc = pci_read_config_byte(dev, where: 0x00D1, val: &val);
3527 if (rc)
3528 return;
3529
3530 resource_set_size(res: &dev->resource[4], size: (resource_size_t)1 << val);
3531}
3532DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3533DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3534
3535/*
3536 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3537 * though no one is handling them (e.g., if the i915 driver is never
3538 * loaded). Additionally the interrupt destination is not set up properly
3539 * and the interrupt ends up -somewhere-.
3540 *
3541 * These spurious interrupts are "sticky" and the kernel disables the
3542 * (shared) interrupt line after 100,000+ generated interrupts.
3543 *
3544 * Fix it by disabling the still enabled interrupts. This resolves crashes
3545 * often seen on monitor unplug.
3546 */
3547#define I915_DEIER_REG 0x4400c
3548static void disable_igfx_irq(struct pci_dev *dev)
3549{
3550 void __iomem *regs = pci_iomap(dev, bar: 0, max: 0);
3551 if (regs == NULL) {
3552 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3553 return;
3554 }
3555
3556 /* Check if any interrupt line is still enabled */
3557 if (readl(addr: regs + I915_DEIER_REG) != 0) {
3558 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3559
3560 writel(val: 0, addr: regs + I915_DEIER_REG);
3561 }
3562
3563 pci_iounmap(dev, regs);
3564}
3565DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3566DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3567DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3568DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3569DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3571DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3572
3573/*
3574 * PCI devices which are on Intel chips can skip the 10ms delay
3575 * before entering D3 mode.
3576 */
3577static void quirk_remove_d3hot_delay(struct pci_dev *dev)
3578{
3579 dev->d3hot_delay = 0;
3580}
3581/* C600 Series devices do not need 10ms d3hot_delay */
3582DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay);
3583DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay);
3584DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay);
3585/* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3586DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay);
3587DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay);
3588DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay);
3589DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay);
3590DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay);
3591DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay);
3592DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay);
3593DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay);
3594DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay);
3595DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay);
3596DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay);
3597/* Intel Cherrytrail devices do not need 10ms d3hot_delay */
3598DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay);
3599DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay);
3600DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay);
3601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay);
3602DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay);
3603DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay);
3604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay);
3605DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay);
3606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay);
3607
3608/*
3609 * Some devices may pass our check in pci_intx_mask_supported() if
3610 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3611 * support this feature.
3612 */
3613static void quirk_broken_intx_masking(struct pci_dev *dev)
3614{
3615 dev->broken_intx_masking = 1;
3616}
3617DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3618 quirk_broken_intx_masking);
3619DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3620 quirk_broken_intx_masking);
3621DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3622 quirk_broken_intx_masking);
3623DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_20K2,
3624 quirk_broken_intx_masking);
3625
3626/*
3627 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3628 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3629 *
3630 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3631 */
3632DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3633 quirk_broken_intx_masking);
3634
3635/*
3636 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3637 * DisINTx can be set but the interrupt status bit is non-functional.
3638 */
3639DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3640DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3641DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3642DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3643DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3644DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3645DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3646DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3647DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3648DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3649DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3650DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3651DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3652DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3653DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3654DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3655
3656static u16 mellanox_broken_intx_devs[] = {
3657 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3658 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3659 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3660 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3661 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3662 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3663 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3664 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3665 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3666 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3667 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3668 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3669 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3670 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3671};
3672
3673#define CONNECTX_4_CURR_MAX_MINOR 99
3674#define CONNECTX_4_INTX_SUPPORT_MINOR 14
3675
3676/*
3677 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3678 * If so, don't mark it as broken.
3679 * FW minor > 99 means older FW version format and no INTx masking support.
3680 * FW minor < 14 means new FW version format and no INTx masking support.
3681 */
3682static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3683{
3684 __be32 __iomem *fw_ver;
3685 u16 fw_major;
3686 u16 fw_minor;
3687 u16 fw_subminor;
3688 u32 fw_maj_min;
3689 u32 fw_sub_min;
3690 int i;
3691
3692 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3693 if (pdev->device == mellanox_broken_intx_devs[i]) {
3694 pdev->broken_intx_masking = 1;
3695 return;
3696 }
3697 }
3698
3699 /*
3700 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3701 * support so shouldn't be checked further
3702 */
3703 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3704 return;
3705
3706 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3707 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3708 return;
3709
3710 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3711 if (pci_enable_device_mem(dev: pdev)) {
3712 pci_warn(pdev, "Can't enable device memory\n");
3713 return;
3714 }
3715
3716 fw_ver = ioremap(pci_resource_start(pdev, 0), size: 4);
3717 if (!fw_ver) {
3718 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3719 goto out;
3720 }
3721
3722 /* Reading from resource space should be 32b aligned */
3723 fw_maj_min = ioread32be(fw_ver);
3724 fw_sub_min = ioread32be(fw_ver + 1);
3725 fw_major = fw_maj_min & 0xffff;
3726 fw_minor = fw_maj_min >> 16;
3727 fw_subminor = fw_sub_min & 0xffff;
3728 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3729 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3730 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3731 fw_major, fw_minor, fw_subminor, pdev->device ==
3732 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3733 pdev->broken_intx_masking = 1;
3734 }
3735
3736 iounmap(addr: fw_ver);
3737
3738out:
3739 pci_disable_device(dev: pdev);
3740}
3741DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3742 mellanox_check_broken_intx_masking);
3743
3744static void quirk_no_bus_reset(struct pci_dev *dev)
3745{
3746 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3747}
3748
3749/*
3750 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
3751 * prevented for those affected devices.
3752 */
3753static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
3754{
3755 if ((dev->device & 0xffc0) == 0x2340)
3756 quirk_no_bus_reset(dev);
3757}
3758DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
3759 quirk_nvidia_no_bus_reset);
3760
3761/*
3762 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3763 * The device will throw a Link Down error on AER-capable systems and
3764 * regardless of AER, config space of the device is never accessible again
3765 * and typically causes the system to hang or reset when access is attempted.
3766 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
3767 */
3768DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3769DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3770DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3771DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3772DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3773DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
3774
3775/*
3776 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3777 * reset when used with certain child devices. After the reset, config
3778 * accesses to the child may fail.
3779 */
3780DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3781
3782/*
3783 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS
3784 * automatically disables LTSSM when Secondary Bus Reset is received and
3785 * the device stops working. Prevent bus reset for these devices. With
3786 * this change, the device can be assigned to VMs with VFIO, but it will
3787 * leak state between VMs. Reference
3788 * https://e2e.ti.com/support/processors/f/791/t/954382
3789 */
3790DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
3791
3792static void quirk_no_pm_reset(struct pci_dev *dev)
3793{
3794 /*
3795 * We can't do a bus reset on root bus devices, but an ineffective
3796 * PM reset may be better than nothing.
3797 */
3798 if (!pci_is_root_bus(pbus: dev->bus))
3799 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3800}
3801
3802/*
3803 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3804 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3805 * to have no effect on the device: it retains the framebuffer contents and
3806 * monitor sync. Advertising this support makes other layers, like VFIO,
3807 * assume pci_reset_function() is viable for this device. Mark it as
3808 * unavailable to skip it when testing reset methods.
3809 */
3810DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3811 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3812
3813/*
3814 * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset
3815 * (i.e., they advertise NoSoftRst-). However, this transition does not have
3816 * any effect on the device: It continues to be operational and network ports
3817 * remain up. Advertising this support makes it seem as if a PM reset is viable
3818 * for these devices. Mark it as unavailable to skip it when testing reset
3819 * methods.
3820 */
3821DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset);
3822DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset);
3823DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset);
3824DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset);
3825
3826/*
3827 * Thunderbolt controllers with broken MSI hotplug signaling:
3828 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3829 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3830 */
3831static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3832{
3833 if (pdev->is_pciehp &&
3834 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3835 pdev->revision <= 1))
3836 pdev->no_msi = 1;
3837}
3838DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3839 quirk_thunderbolt_hotplug_msi);
3840DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3841 quirk_thunderbolt_hotplug_msi);
3842DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3843 quirk_thunderbolt_hotplug_msi);
3844DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3845 quirk_thunderbolt_hotplug_msi);
3846DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3847 quirk_thunderbolt_hotplug_msi);
3848
3849#ifdef CONFIG_ACPI
3850/*
3851 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3852 *
3853 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3854 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3855 * be present after resume if a device was plugged in before suspend.
3856 *
3857 * The Thunderbolt controller consists of a PCIe switch with downstream
3858 * bridges leading to the NHI and to the tunnel PCI bridges.
3859 *
3860 * This quirk cuts power to the whole chip. Therefore we have to apply it
3861 * during suspend_noirq of the upstream bridge.
3862 *
3863 * Power is automagically restored before resume. No action is needed.
3864 */
3865static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3866{
3867 acpi_handle bridge, SXIO, SXFP, SXLV;
3868
3869 if (!x86_apple_machine)
3870 return;
3871 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3872 return;
3873
3874 /*
3875 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller.
3876 * We don't know how to turn it back on again, but firmware does,
3877 * so we can only use SXIO/SXFP/SXLF if we're suspending via
3878 * firmware.
3879 */
3880 if (!pm_suspend_via_firmware())
3881 return;
3882
3883 bridge = ACPI_HANDLE(&dev->dev);
3884 if (!bridge)
3885 return;
3886
3887 /*
3888 * SXIO and SXLV are present only on machines requiring this quirk.
3889 * Thunderbolt bridges in external devices might have the same
3890 * device ID as those on the host, but they will not have the
3891 * associated ACPI methods. This implicitly checks that we are at
3892 * the right bridge.
3893 */
3894 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3895 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3896 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3897 return;
3898 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
3899
3900 /* magic sequence */
3901 acpi_execute_simple_method(handle: SXIO, NULL, arg: 1);
3902 acpi_execute_simple_method(handle: SXFP, NULL, arg: 0);
3903 msleep(msecs: 300);
3904 acpi_execute_simple_method(handle: SXLV, NULL, arg: 0);
3905 acpi_execute_simple_method(handle: SXIO, NULL, arg: 0);
3906 acpi_execute_simple_method(handle: SXLV, NULL, arg: 0);
3907}
3908DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3909 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3910 quirk_apple_poweroff_thunderbolt);
3911#endif
3912
3913/*
3914 * Following are device-specific reset methods which can be used to
3915 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3916 * not available.
3917 */
3918static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe)
3919{
3920 /*
3921 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3922 *
3923 * The 82599 supports FLR on VFs, but FLR support is reported only
3924 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3925 * Thus we must call pcie_flr() directly without first checking if it is
3926 * supported.
3927 */
3928 if (!probe)
3929 pcie_flr(dev);
3930 return 0;
3931}
3932
3933#define SOUTH_CHICKEN2 0xc2004
3934#define PCH_PP_STATUS 0xc7200
3935#define PCH_PP_CONTROL 0xc7204
3936#define MSG_CTL 0x45010
3937#define NSDE_PWR_STATE 0xd0100
3938#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3939
3940static int reset_ivb_igd(struct pci_dev *dev, bool probe)
3941{
3942 void __iomem *mmio_base;
3943 unsigned long timeout;
3944 u32 val;
3945
3946 if (probe)
3947 return 0;
3948
3949 mmio_base = pci_iomap(dev, bar: 0, max: 0);
3950 if (!mmio_base)
3951 return -ENOMEM;
3952
3953 iowrite32(0x00000002, mmio_base + MSG_CTL);
3954
3955 /*
3956 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3957 * driver loaded sets the right bits. However, this's a reset and
3958 * the bits have been set by i915 previously, so we clobber
3959 * SOUTH_CHICKEN2 register directly here.
3960 */
3961 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3962
3963 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3964 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3965
3966 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3967 do {
3968 val = ioread32(mmio_base + PCH_PP_STATUS);
3969 if ((val & 0xb0000000) == 0)
3970 goto reset_complete;
3971 msleep(msecs: 10);
3972 } while (time_before(jiffies, timeout));
3973 pci_warn(dev, "timeout during reset\n");
3974
3975reset_complete:
3976 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3977
3978 pci_iounmap(dev, mmio_base);
3979 return 0;
3980}
3981
3982/* Device-specific reset method for Chelsio T4-based adapters */
3983static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe)
3984{
3985 u16 old_command;
3986 u16 msix_flags;
3987
3988 /*
3989 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3990 * that we have no device-specific reset method.
3991 */
3992 if ((dev->device & 0xf000) != 0x4000)
3993 return -ENOTTY;
3994
3995 /*
3996 * If this is the "probe" phase, return 0 indicating that we can
3997 * reset this device.
3998 */
3999 if (probe)
4000 return 0;
4001
4002 /*
4003 * T4 can wedge if there are DMAs in flight within the chip and Bus
4004 * Master has been disabled. We need to have it on till the Function
4005 * Level Reset completes. (BUS_MASTER is disabled in
4006 * pci_reset_function()).
4007 */
4008 pci_read_config_word(dev, PCI_COMMAND, val: &old_command);
4009 pci_write_config_word(dev, PCI_COMMAND,
4010 val: old_command | PCI_COMMAND_MASTER);
4011
4012 /*
4013 * Perform the actual device function reset, saving and restoring
4014 * configuration information around the reset.
4015 */
4016 pci_save_state(dev);
4017
4018 /*
4019 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
4020 * are disabled when an MSI-X interrupt message needs to be delivered.
4021 * So we briefly re-enable MSI-X interrupts for the duration of the
4022 * FLR. The pci_restore_state() below will restore the original
4023 * MSI-X state.
4024 */
4025 pci_read_config_word(dev, where: dev->msix_cap+PCI_MSIX_FLAGS, val: &msix_flags);
4026 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
4027 pci_write_config_word(dev, where: dev->msix_cap+PCI_MSIX_FLAGS,
4028 val: msix_flags |
4029 PCI_MSIX_FLAGS_ENABLE |
4030 PCI_MSIX_FLAGS_MASKALL);
4031
4032 pcie_flr(dev);
4033
4034 /*
4035 * Restore the configuration information (BAR values, etc.) including
4036 * the original PCI Configuration Space Command word, and return
4037 * success.
4038 */
4039 pci_restore_state(dev);
4040 pci_write_config_word(dev, PCI_COMMAND, val: old_command);
4041 return 0;
4042}
4043
4044#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
4045#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
4046#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
4047
4048/*
4049 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
4050 * FLR where config space reads from the device return -1. We seem to be
4051 * able to avoid this condition if we disable the NVMe controller prior to
4052 * FLR. This quirk is generic for any NVMe class device requiring similar
4053 * assistance to quiesce the device prior to FLR.
4054 *
4055 * NVMe specification: https://nvmexpress.org/resources/specifications/
4056 * Revision 1.0e:
4057 * Chapter 2: Required and optional PCI config registers
4058 * Chapter 3: NVMe control registers
4059 * Chapter 7.3: Reset behavior
4060 */
4061static int nvme_disable_and_flr(struct pci_dev *dev, bool probe)
4062{
4063 void __iomem *bar;
4064 u16 cmd;
4065 u32 cfg;
4066
4067 if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
4068 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0))
4069 return -ENOTTY;
4070
4071 if (probe)
4072 return 0;
4073
4074 bar = pci_iomap(dev, bar: 0, max: NVME_REG_CC + sizeof(cfg));
4075 if (!bar)
4076 return -ENOTTY;
4077
4078 pci_read_config_word(dev, PCI_COMMAND, val: &cmd);
4079 pci_write_config_word(dev, PCI_COMMAND, val: cmd | PCI_COMMAND_MEMORY);
4080
4081 cfg = readl(addr: bar + NVME_REG_CC);
4082
4083 /* Disable controller if enabled */
4084 if (cfg & NVME_CC_ENABLE) {
4085 u32 cap = readl(addr: bar + NVME_REG_CAP);
4086 unsigned long timeout;
4087
4088 /*
4089 * Per nvme_disable_ctrl() skip shutdown notification as it
4090 * could complete commands to the admin queue. We only intend
4091 * to quiesce the device before reset.
4092 */
4093 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
4094
4095 writel(val: cfg, addr: bar + NVME_REG_CC);
4096
4097 /*
4098 * Some controllers require an additional delay here, see
4099 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
4100 * supported by this quirk.
4101 */
4102
4103 /* Cap register provides max timeout in 500ms increments */
4104 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
4105
4106 for (;;) {
4107 u32 status = readl(addr: bar + NVME_REG_CSTS);
4108
4109 /* Ready status becomes zero on disable complete */
4110 if (!(status & NVME_CSTS_RDY))
4111 break;
4112
4113 msleep(msecs: 100);
4114
4115 if (time_after(jiffies, timeout)) {
4116 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
4117 break;
4118 }
4119 }
4120 }
4121
4122 pci_iounmap(dev, bar);
4123
4124 pcie_flr(dev);
4125
4126 return 0;
4127}
4128
4129/*
4130 * Some NVMe controllers such as Intel DC P3700 and Solidigm P44 Pro will
4131 * timeout waiting for ready status to change after NVMe enable if the driver
4132 * starts interacting with the device too soon after FLR. A 250ms delay after
4133 * FLR has heuristically proven to produce reliably working results for device
4134 * assignment cases.
4135 */
4136static int delay_250ms_after_flr(struct pci_dev *dev, bool probe)
4137{
4138 if (probe)
4139 return pcie_reset_flr(dev, PCI_RESET_PROBE);
4140
4141 pcie_reset_flr(dev, PCI_RESET_DO_RESET);
4142
4143 msleep(msecs: 250);
4144
4145 return 0;
4146}
4147
4148#define PCI_DEVICE_ID_HINIC_VF 0x375E
4149#define HINIC_VF_FLR_TYPE 0x1000
4150#define HINIC_VF_FLR_CAP_BIT (1UL << 30)
4151#define HINIC_VF_OP 0xE80
4152#define HINIC_VF_FLR_PROC_BIT (1UL << 18)
4153#define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */
4154
4155/* Device-specific reset method for Huawei Intelligent NIC virtual functions */
4156static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe)
4157{
4158 unsigned long timeout;
4159 void __iomem *bar;
4160 u32 val;
4161
4162 if (probe)
4163 return 0;
4164
4165 bar = pci_iomap(dev: pdev, bar: 0, max: 0);
4166 if (!bar)
4167 return -ENOTTY;
4168
4169 /* Get and check firmware capabilities */
4170 val = ioread32be(bar + HINIC_VF_FLR_TYPE);
4171 if (!(val & HINIC_VF_FLR_CAP_BIT)) {
4172 pci_iounmap(dev: pdev, bar);
4173 return -ENOTTY;
4174 }
4175
4176 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */
4177 val = ioread32be(bar + HINIC_VF_OP);
4178 val = val | HINIC_VF_FLR_PROC_BIT;
4179 iowrite32be(val, bar + HINIC_VF_OP);
4180
4181 pcie_flr(dev: pdev);
4182
4183 /*
4184 * The device must recapture its Bus and Device Numbers after FLR
4185 * in order generate Completions. Issue a config write to let the
4186 * device capture this information.
4187 */
4188 pci_write_config_word(dev: pdev, PCI_VENDOR_ID, val: 0);
4189
4190 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */
4191 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT);
4192 do {
4193 val = ioread32be(bar + HINIC_VF_OP);
4194 if (!(val & HINIC_VF_FLR_PROC_BIT))
4195 goto reset_complete;
4196 msleep(msecs: 20);
4197 } while (time_before(jiffies, timeout));
4198
4199 val = ioread32be(bar + HINIC_VF_OP);
4200 if (!(val & HINIC_VF_FLR_PROC_BIT))
4201 goto reset_complete;
4202
4203 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val);
4204
4205reset_complete:
4206 pci_iounmap(dev: pdev, bar);
4207
4208 return 0;
4209}
4210
4211static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
4212 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
4213 reset_intel_82599_sfp_virtfn },
4214 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
4215 reset_ivb_igd },
4216 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
4217 reset_ivb_igd },
4218 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
4219 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
4220 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr },
4221 { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr },
4222 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4223 reset_chelsio_generic_dev },
4224 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF,
4225 reset_hinic_vf_dev },
4226 { 0 }
4227};
4228
4229/*
4230 * These device-specific reset methods are here rather than in a driver
4231 * because when a host assigns a device to a guest VM, the host may need
4232 * to reset the device but probably doesn't have a driver for it.
4233 */
4234int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
4235{
4236 const struct pci_dev_reset_methods *i;
4237
4238 for (i = pci_dev_reset_methods; i->reset; i++) {
4239 if ((i->vendor == dev->vendor ||
4240 i->vendor == (u16)PCI_ANY_ID) &&
4241 (i->device == dev->device ||
4242 i->device == (u16)PCI_ANY_ID))
4243 return i->reset(dev, probe);
4244 }
4245
4246 return -ENOTTY;
4247}
4248
4249static void quirk_dma_func0_alias(struct pci_dev *dev)
4250{
4251 if (PCI_FUNC(dev->devfn) != 0)
4252 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), nr_devfns: 1);
4253}
4254
4255/*
4256 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
4257 *
4258 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
4259 */
4260DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
4261DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
4262
4263/* Some Glenfly chips use function 0 as the PCIe Requester ID for DMA */
4264DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d40, quirk_dma_func0_alias);
4265DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d41, quirk_dma_func0_alias);
4266
4267static void quirk_dma_func1_alias(struct pci_dev *dev)
4268{
4269 if (PCI_FUNC(dev->devfn) != 1)
4270 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), nr_devfns: 1);
4271}
4272
4273/*
4274 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
4275 * SKUs function 1 is present and is a legacy IDE controller, in other
4276 * SKUs this function is not present, making this a ghost requester.
4277 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
4278 */
4279DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
4280 quirk_dma_func1_alias);
4281DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
4282 quirk_dma_func1_alias);
4283/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */
4284DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
4285 quirk_dma_func1_alias);
4286DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
4287 quirk_dma_func1_alias);
4288/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
4289DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
4290 quirk_dma_func1_alias);
4291DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
4292 quirk_dma_func1_alias);
4293/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
4294DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
4295 quirk_dma_func1_alias);
4296/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
4297DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
4298 quirk_dma_func1_alias);
4299/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
4300DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
4301 quirk_dma_func1_alias);
4302/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
4303DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
4304 quirk_dma_func1_alias);
4305/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
4306DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
4307 quirk_dma_func1_alias);
4308/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */
4309DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
4310 quirk_dma_func1_alias);
4311/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
4312DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
4313 quirk_dma_func1_alias);
4314/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
4315DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
4316 quirk_dma_func1_alias);
4317DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235,
4318 quirk_dma_func1_alias);
4319DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
4320 quirk_dma_func1_alias);
4321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
4322 quirk_dma_func1_alias);
4323/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
4324DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
4325 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
4326 quirk_dma_func1_alias);
4327/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
4328DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4329 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4330 quirk_dma_func1_alias);
4331
4332/*
4333 * Some devices DMA with the wrong devfn, not just the wrong function.
4334 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4335 * the alias is "fixed" and independent of the device devfn.
4336 *
4337 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4338 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4339 * single device on the secondary bus. In reality, the single exposed
4340 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4341 * that provides a bridge to the internal bus of the I/O processor. The
4342 * controller supports private devices, which can be hidden from PCI config
4343 * space. In the case of the Adaptec 3405, a private device at 01.0
4344 * appears to be the DMA engine, which therefore needs to become a DMA
4345 * alias for the device.
4346 */
4347static const struct pci_device_id fixed_dma_alias_tbl[] = {
4348 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4349 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4350 .driver_data = PCI_DEVFN(1, 0) },
4351 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4352 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4353 .driver_data = PCI_DEVFN(1, 0) },
4354 { 0 }
4355};
4356
4357static void quirk_fixed_dma_alias(struct pci_dev *dev)
4358{
4359 const struct pci_device_id *id;
4360
4361 id = pci_match_id(ids: fixed_dma_alias_tbl, dev);
4362 if (id)
4363 pci_add_dma_alias(dev, devfn_from: id->driver_data, nr_devfns: 1);
4364}
4365DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4366
4367/*
4368 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4369 * using the wrong DMA alias for the device. Some of these devices can be
4370 * used as either forward or reverse bridges, so we need to test whether the
4371 * device is operating in the correct mode. We could probably apply this
4372 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4373 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4374 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4375 */
4376static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
4377{
4378 if (!pci_is_root_bus(pbus: pdev->bus) &&
4379 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4380 !pci_is_pcie(dev: pdev) && pci_is_pcie(dev: pdev->bus->self) &&
4381 pci_pcie_type(dev: pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4382 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4383}
4384/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4385DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4386 quirk_use_pcie_bridge_dma_alias);
4387/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4388DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4389/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4390DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4391/* ITE 8893 has the same problem as the 8892 */
4392DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4393/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4394DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4395
4396/*
4397 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4398 * be added as aliases to the DMA device in order to allow buffer access
4399 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4400 * programmed in the EEPROM.
4401 */
4402static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4403{
4404 pci_add_dma_alias(dev: pdev, PCI_DEVFN(0x10, 0x0), nr_devfns: 1);
4405 pci_add_dma_alias(dev: pdev, PCI_DEVFN(0x11, 0x0), nr_devfns: 1);
4406 pci_add_dma_alias(dev: pdev, PCI_DEVFN(0x12, 0x3), nr_devfns: 1);
4407}
4408DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4409DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4410
4411/*
4412 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4413 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
4414 *
4415 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
4416 * when IOMMU is enabled. These aliases allow computational unit access to
4417 * host memory. These aliases mark the whole VCA device as one IOMMU
4418 * group.
4419 *
4420 * All possible slot numbers (0x20) are used, since we are unable to tell
4421 * what slot is used on other side. This quirk is intended for both host
4422 * and computational unit sides. The VCA devices have up to five functions
4423 * (four for DMA channels and one additional).
4424 */
4425static void quirk_pex_vca_alias(struct pci_dev *pdev)
4426{
4427 const unsigned int num_pci_slots = 0x20;
4428 unsigned int slot;
4429
4430 for (slot = 0; slot < num_pci_slots; slot++)
4431 pci_add_dma_alias(dev: pdev, PCI_DEVFN(slot, 0x0), nr_devfns: 5);
4432}
4433DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4434DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4435DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4436DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4437DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4438DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4439
4440/*
4441 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4442 * associated not at the root bus, but at a bridge below. This quirk avoids
4443 * generating invalid DMA aliases.
4444 */
4445static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4446{
4447 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4448}
4449DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4450 quirk_bridge_cavm_thrx2_pcie_root);
4451DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4452 quirk_bridge_cavm_thrx2_pcie_root);
4453
4454/*
4455 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4456 * class code. Fix it.
4457 */
4458static void quirk_tw686x_class(struct pci_dev *pdev)
4459{
4460 u32 class = pdev->class;
4461
4462 /* Use "Multimedia controller" class */
4463 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4464 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4465 class, pdev->class);
4466}
4467DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4468 quirk_tw686x_class);
4469DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4470 quirk_tw686x_class);
4471DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4472 quirk_tw686x_class);
4473DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4474 quirk_tw686x_class);
4475
4476/*
4477 * Some devices have problems with Transaction Layer Packets with the Relaxed
4478 * Ordering Attribute set. Such devices should mark themselves and other
4479 * device drivers should check before sending TLPs with RO set.
4480 */
4481static void quirk_relaxedordering_disable(struct pci_dev *dev)
4482{
4483 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4484 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4485}
4486
4487/*
4488 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4489 * Complex have a Flow Control Credit issue which can cause performance
4490 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4491 */
4492DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4493 quirk_relaxedordering_disable);
4494DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4495 quirk_relaxedordering_disable);
4496DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4497 quirk_relaxedordering_disable);
4498DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4499 quirk_relaxedordering_disable);
4500DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4501 quirk_relaxedordering_disable);
4502DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4503 quirk_relaxedordering_disable);
4504DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4505 quirk_relaxedordering_disable);
4506DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4507 quirk_relaxedordering_disable);
4508DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4509 quirk_relaxedordering_disable);
4510DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4511 quirk_relaxedordering_disable);
4512DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4513 quirk_relaxedordering_disable);
4514DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4515 quirk_relaxedordering_disable);
4516DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4517 quirk_relaxedordering_disable);
4518DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4519 quirk_relaxedordering_disable);
4520DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4521 quirk_relaxedordering_disable);
4522DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4523 quirk_relaxedordering_disable);
4524DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4525 quirk_relaxedordering_disable);
4526DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4527 quirk_relaxedordering_disable);
4528DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4529 quirk_relaxedordering_disable);
4530DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4531 quirk_relaxedordering_disable);
4532DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4533 quirk_relaxedordering_disable);
4534DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4535 quirk_relaxedordering_disable);
4536DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4537 quirk_relaxedordering_disable);
4538DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4539 quirk_relaxedordering_disable);
4540DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4541 quirk_relaxedordering_disable);
4542DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4543 quirk_relaxedordering_disable);
4544DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4545 quirk_relaxedordering_disable);
4546DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4547 quirk_relaxedordering_disable);
4548
4549/*
4550 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4551 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4552 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4553 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4554 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4555 * November 10, 2010). As a result, on this platform we can't use Relaxed
4556 * Ordering for Upstream TLPs.
4557 */
4558DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4559 quirk_relaxedordering_disable);
4560DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4561 quirk_relaxedordering_disable);
4562DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4563 quirk_relaxedordering_disable);
4564
4565/*
4566 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4567 * values for the Attribute as were supplied in the header of the
4568 * corresponding Request, except as explicitly allowed when IDO is used."
4569 *
4570 * If a non-compliant device generates a completion with a different
4571 * attribute than the request, the receiver may accept it (which itself
4572 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4573 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4574 * device access timeout.
4575 *
4576 * If the non-compliant device generates completions with zero attributes
4577 * (instead of copying the attributes from the request), we can work around
4578 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4579 * upstream devices so they always generate requests with zero attributes.
4580 *
4581 * This affects other devices under the same Root Port, but since these
4582 * attributes are performance hints, there should be no functional problem.
4583 *
4584 * Note that Configuration Space accesses are never supposed to have TLP
4585 * Attributes, so we're safe waiting till after any Configuration Space
4586 * accesses to do the Root Port fixup.
4587 */
4588static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4589{
4590 struct pci_dev *root_port = pcie_find_root_port(dev: pdev);
4591
4592 if (!root_port) {
4593 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4594 return;
4595 }
4596
4597 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4598 dev_name(&pdev->dev));
4599 pcie_capability_clear_word(dev: root_port, PCI_EXP_DEVCTL,
4600 PCI_EXP_DEVCTL_RELAX_EN |
4601 PCI_EXP_DEVCTL_NOSNOOP_EN);
4602}
4603
4604/*
4605 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4606 * Completion it generates.
4607 */
4608static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4609{
4610 /*
4611 * This mask/compare operation selects for Physical Function 4 on a
4612 * T5. We only need to fix up the Root Port once for any of the
4613 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4614 * 0x54xx so we use that one.
4615 */
4616 if ((pdev->device & 0xff00) == 0x5400)
4617 quirk_disable_root_port_attributes(pdev);
4618}
4619DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4620 quirk_chelsio_T5_disable_root_port_attributes);
4621
4622/*
4623 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4624 * by a device
4625 * @acs_ctrl_req: Bitmask of desired ACS controls
4626 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
4627 * the hardware design
4628 *
4629 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
4630 * in @acs_ctrl_ena, i.e., the device provides all the access controls the
4631 * caller desires. Return 0 otherwise.
4632 */
4633static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
4634{
4635 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
4636 return 1;
4637 return 0;
4638}
4639
4640/*
4641 * AMD has indicated that the devices below do not support peer-to-peer
4642 * in any system where they are found in the southbridge with an AMD
4643 * IOMMU in the system. Multifunction devices that do not support
4644 * peer-to-peer between functions can claim to support a subset of ACS.
4645 * Such devices effectively enable request redirect (RR) and completion
4646 * redirect (CR) since all transactions are redirected to the upstream
4647 * root complex.
4648 *
4649 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/
4650 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/
4651 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/
4652 *
4653 * 1002:4385 SBx00 SMBus Controller
4654 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4655 * 1002:4383 SBx00 Azalia (Intel HDA)
4656 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4657 * 1002:4384 SBx00 PCI to PCI Bridge
4658 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4659 *
4660 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4661 *
4662 * 1022:780f [AMD] FCH PCI Bridge
4663 * 1022:7809 [AMD] FCH USB OHCI Controller
4664 */
4665static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4666{
4667#ifdef CONFIG_ACPI
4668 struct acpi_table_header *header = NULL;
4669 acpi_status status;
4670
4671 /* Targeting multifunction devices on the SB (appears on root bus) */
4672 if (!dev->multifunction || !pci_is_root_bus(pbus: dev->bus))
4673 return -ENODEV;
4674
4675 /* The IVRS table describes the AMD IOMMU */
4676 status = acpi_get_table(signature: "IVRS", instance: 0, out_table: &header);
4677 if (ACPI_FAILURE(status))
4678 return -ENODEV;
4679
4680 acpi_put_table(table: header);
4681
4682 /* Filter out flags not applicable to multifunction */
4683 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4684
4685 return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags, PCI_ACS_RR | PCI_ACS_CR);
4686#else
4687 return -ENODEV;
4688#endif
4689}
4690
4691static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4692{
4693 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4694 return false;
4695
4696 switch (dev->device) {
4697 /*
4698 * Effectively selects all downstream ports for whole ThunderX1
4699 * (which represents 8 SoCs).
4700 */
4701 case 0xa000 ... 0xa7ff: /* ThunderX1 */
4702 case 0xaf84: /* ThunderX2 */
4703 case 0xb884: /* ThunderX3 */
4704 return true;
4705 default:
4706 return false;
4707 }
4708}
4709
4710static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4711{
4712 if (!pci_quirk_cavium_acs_match(dev))
4713 return -ENOTTY;
4714
4715 /*
4716 * Cavium Root Ports don't advertise an ACS capability. However,
4717 * the RTL internally implements similar protection as if ACS had
4718 * Source Validation, Request Redirection, Completion Redirection,
4719 * and Upstream Forwarding features enabled. Assert that the
4720 * hardware implements and enables equivalent ACS functionality for
4721 * these flags.
4722 */
4723 return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags,
4724 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4725}
4726
4727static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4728{
4729 /*
4730 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4731 * transactions with others, allowing masking out these bits as if they
4732 * were unimplemented in the ACS capability.
4733 */
4734 return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags,
4735 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4736}
4737
4738/*
4739 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
4740 * But the implementation could block peer-to-peer transactions between them
4741 * and provide ACS-like functionality.
4742 */
4743static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
4744{
4745 if (!pci_is_pcie(dev) ||
4746 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
4747 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
4748 return -ENOTTY;
4749
4750 /*
4751 * Future Zhaoxin Root Ports and Switch Downstream Ports will
4752 * implement ACS capability in accordance with the PCIe Spec.
4753 */
4754 switch (dev->device) {
4755 case 0x0710 ... 0x071e:
4756 case 0x0721:
4757 case 0x0723 ... 0x0752:
4758 return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags,
4759 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4760 }
4761
4762 return false;
4763}
4764
4765/*
4766 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4767 * transactions and validate bus numbers in requests, but do not provide an
4768 * actual PCIe ACS capability. This is the list of device IDs known to fall
4769 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4770 */
4771static const u16 pci_quirk_intel_pch_acs_ids[] = {
4772 /* Ibexpeak PCH */
4773 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4774 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4775 /* Cougarpoint PCH */
4776 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4777 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4778 /* Pantherpoint PCH */
4779 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4780 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4781 /* Lynxpoint-H PCH */
4782 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4783 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4784 /* Lynxpoint-LP PCH */
4785 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4786 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4787 /* Wildcat PCH */
4788 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4789 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4790 /* Patsburg (X79) PCH */
4791 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4792 /* Wellsburg (X99) PCH */
4793 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4794 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4795 /* Lynx Point (9 series) PCH */
4796 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4797};
4798
4799static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4800{
4801 int i;
4802
4803 /* Filter out a few obvious non-matches first */
4804 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4805 return false;
4806
4807 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4808 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4809 return true;
4810
4811 return false;
4812}
4813
4814static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4815{
4816 if (!pci_quirk_intel_pch_acs_match(dev))
4817 return -ENOTTY;
4818
4819 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
4820 return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags,
4821 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4822
4823 return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags, acs_ctrl_ena: 0);
4824}
4825
4826/*
4827 * These QCOM Root Ports do provide ACS-like features to disable peer
4828 * transactions and validate bus numbers in requests, but do not provide an
4829 * actual PCIe ACS capability. Hardware supports source validation but it
4830 * will report the issue as Completer Abort instead of ACS Violation.
4831 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4832 * Complex with unique segment numbers. It is not possible for one Root
4833 * Port to pass traffic to another Root Port. All PCIe transactions are
4834 * terminated inside the Root Port.
4835 */
4836static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4837{
4838 return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags,
4839 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4840}
4841
4842/*
4843 * Each of these NXP Root Ports is in a Root Complex with a unique segment
4844 * number and does provide isolation features to disable peer transactions
4845 * and validate bus numbers in requests, but does not provide an ACS
4846 * capability.
4847 */
4848static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags)
4849{
4850 return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags,
4851 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4852}
4853
4854static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
4855{
4856 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4857 return -ENOTTY;
4858
4859 /*
4860 * Amazon's Annapurna Labs root ports don't include an ACS capability,
4861 * but do include ACS-like functionality. The hardware doesn't support
4862 * peer-to-peer transactions via the root port and each has a unique
4863 * segment number.
4864 *
4865 * Additionally, the root ports cannot send traffic to each other.
4866 */
4867 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4868
4869 return acs_flags ? 0 : 1;
4870}
4871
4872/*
4873 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4874 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4875 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4876 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4877 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4878 * control register is at offset 8 instead of 6 and we should probably use
4879 * dword accesses to them. This applies to the following PCI Device IDs, as
4880 * found in volume 1 of the datasheet[2]:
4881 *
4882 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4883 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4884 *
4885 * N.B. This doesn't fix what lspci shows.
4886 *
4887 * The 100 series chipset specification update includes this as errata #23[3].
4888 *
4889 * The 200 series chipset (Union Point) has the same bug according to the
4890 * specification update (Intel 200 Series Chipset Family Platform Controller
4891 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4892 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4893 * chipset include:
4894 *
4895 * 0xa290-0xa29f PCI Express Root port #{0-16}
4896 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4897 *
4898 * Mobile chipsets are also affected, 7th & 8th Generation
4899 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4900 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4901 * Processor Family I/O for U Quad Core Platforms Specification Update,
4902 * August 2017, Revision 002, Document#: 334660-002)[6]
4903 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4904 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4905 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4906 *
4907 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4908 *
4909 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4910 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4911 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4912 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4913 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4914 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4915 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4916 */
4917static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4918{
4919 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4920 return false;
4921
4922 switch (dev->device) {
4923 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4924 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4925 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4926 return true;
4927 }
4928
4929 return false;
4930}
4931
4932#define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4933
4934static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4935{
4936 int pos;
4937 u32 cap, ctrl;
4938
4939 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4940 return -ENOTTY;
4941
4942 pos = dev->acs_cap;
4943 if (!pos)
4944 return -ENOTTY;
4945
4946 /* see pci_acs_flags_enabled() */
4947 pci_read_config_dword(dev, where: pos + PCI_ACS_CAP, val: &cap);
4948 acs_flags &= (cap | PCI_ACS_EC);
4949
4950 pci_read_config_dword(dev, where: pos + INTEL_SPT_ACS_CTRL, val: &ctrl);
4951
4952 return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags, acs_ctrl_ena: ctrl);
4953}
4954
4955static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4956{
4957 /*
4958 * SV, TB, and UF are not relevant to multifunction endpoints.
4959 *
4960 * Multifunction devices are only required to implement RR, CR, and DT
4961 * in their ACS capability if they support peer-to-peer transactions.
4962 * Devices matching this quirk have been verified by the vendor to not
4963 * perform peer-to-peer with other functions, allowing us to mask out
4964 * these bits as if they were unimplemented in the ACS capability.
4965 */
4966 return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags,
4967 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4968 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4969}
4970
4971static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags)
4972{
4973 /*
4974 * Intel RCiEP's are required to allow p2p only on translated
4975 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16,
4976 * "Root-Complex Peer to Peer Considerations".
4977 */
4978 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)
4979 return -ENOTTY;
4980
4981 return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags,
4982 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4983}
4984
4985static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
4986{
4987 /*
4988 * iProc PAXB Root Ports don't advertise an ACS capability, but
4989 * they do not allow peer-to-peer transactions between Root Ports.
4990 * Allow each Root Port to be in a separate IOMMU group by masking
4991 * SV/RR/CR/UF bits.
4992 */
4993 return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags,
4994 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4995}
4996
4997static int pci_quirk_loongson_acs(struct pci_dev *dev, u16 acs_flags)
4998{
4999 /*
5000 * Loongson PCIe Root Ports don't advertise an ACS capability, but
5001 * they do not allow peer-to-peer transactions between Root Ports.
5002 * Allow each Root Port to be in a separate IOMMU group by masking
5003 * SV/RR/CR/UF bits.
5004 */
5005 return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags,
5006 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
5007}
5008
5009/*
5010 * Wangxun 40G/25G/10G/1G NICs have no ACS capability, but on
5011 * multi-function devices, the hardware isolates the functions by
5012 * directing all peer-to-peer traffic upstream as though PCI_ACS_RR and
5013 * PCI_ACS_CR were set.
5014 * SFxxx 1G NICs(em).
5015 * RP1000/RP2000 10G NICs(sp).
5016 * FF5xxx 40G/25G/10G NICs(aml).
5017 */
5018static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags)
5019{
5020 switch (dev->device) {
5021 case 0x0100 ... 0x010F: /* EM */
5022 case 0x1001: case 0x2001: /* SP */
5023 case 0x5010: case 0x5025: case 0x5040: /* AML */
5024 case 0x5110: case 0x5125: case 0x5140: /* AML */
5025 return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags,
5026 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
5027 }
5028
5029 return false;
5030}
5031
5032static const struct pci_dev_acs_enabled {
5033 u16 vendor;
5034 u16 device;
5035 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
5036} pci_dev_acs_enabled[] = {
5037 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
5038 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
5039 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
5040 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
5041 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
5042 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
5043 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
5044 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
5045 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
5046 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
5047 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
5048 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
5049 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
5050 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
5051 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
5052 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
5053 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
5054 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
5055 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
5056 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
5057 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
5058 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
5059 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
5060 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
5061 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
5062 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
5063 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
5064 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
5065 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
5066 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
5067 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
5068 /* 82580 */
5069 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
5070 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
5071 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
5072 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
5073 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
5074 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
5075 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
5076 /* 82576 */
5077 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
5078 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
5079 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
5080 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
5081 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
5082 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
5083 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
5084 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
5085 /* 82575 */
5086 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
5087 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
5088 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
5089 /* I350 */
5090 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
5091 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
5092 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
5093 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
5094 /* 82571 (Quads omitted due to non-ACS switch) */
5095 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
5096 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
5097 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
5098 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
5099 /* I219 */
5100 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
5101 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
5102 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs },
5103 /* QCOM QDF2xxx root ports */
5104 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
5105 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
5106 /* QCOM SA8775P root port */
5107 { PCI_VENDOR_ID_QCOM, 0x0115, pci_quirk_qcom_rp_acs },
5108 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
5109 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
5110 /* Intel PCH root ports */
5111 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
5112 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
5113 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
5114 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
5115 /* Cavium ThunderX */
5116 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
5117 /* Cavium multi-function devices */
5118 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
5119 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
5120 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
5121 /* APM X-Gene */
5122 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
5123 /* Ampere Computing */
5124 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
5125 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
5126 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
5127 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
5128 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
5129 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
5130 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
5131 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
5132 /* Broadcom multi-function device */
5133 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
5134 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs },
5135 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs },
5136 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs },
5137 { PCI_VENDOR_ID_BROADCOM, 0x1760, pci_quirk_mf_endpoint_acs },
5138 { PCI_VENDOR_ID_BROADCOM, 0x1761, pci_quirk_mf_endpoint_acs },
5139 { PCI_VENDOR_ID_BROADCOM, 0x1762, pci_quirk_mf_endpoint_acs },
5140 { PCI_VENDOR_ID_BROADCOM, 0x1763, pci_quirk_mf_endpoint_acs },
5141 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
5142 /* Loongson PCIe Root Ports */
5143 { PCI_VENDOR_ID_LOONGSON, 0x3C09, pci_quirk_loongson_acs },
5144 { PCI_VENDOR_ID_LOONGSON, 0x3C19, pci_quirk_loongson_acs },
5145 { PCI_VENDOR_ID_LOONGSON, 0x3C29, pci_quirk_loongson_acs },
5146 { PCI_VENDOR_ID_LOONGSON, 0x7A09, pci_quirk_loongson_acs },
5147 { PCI_VENDOR_ID_LOONGSON, 0x7A19, pci_quirk_loongson_acs },
5148 { PCI_VENDOR_ID_LOONGSON, 0x7A29, pci_quirk_loongson_acs },
5149 { PCI_VENDOR_ID_LOONGSON, 0x7A39, pci_quirk_loongson_acs },
5150 { PCI_VENDOR_ID_LOONGSON, 0x7A49, pci_quirk_loongson_acs },
5151 { PCI_VENDOR_ID_LOONGSON, 0x7A59, pci_quirk_loongson_acs },
5152 { PCI_VENDOR_ID_LOONGSON, 0x7A69, pci_quirk_loongson_acs },
5153 /* Amazon Annapurna Labs */
5154 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
5155 /* Zhaoxin multi-function devices */
5156 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
5157 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
5158 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
5159 /* NXP root ports, xx=16, 12, or 08 cores */
5160 /* LX2xx0A : without security features + CAN-FD */
5161 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs },
5162 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs },
5163 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs },
5164 /* LX2xx0C : security features + CAN-FD */
5165 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs },
5166 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs },
5167 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs },
5168 /* LX2xx0E : security features + CAN */
5169 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs },
5170 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs },
5171 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs },
5172 /* LX2xx0N : without security features + CAN */
5173 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs },
5174 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs },
5175 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs },
5176 /* LX2xx2A : without security features + CAN-FD */
5177 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs },
5178 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs },
5179 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs },
5180 /* LX2xx2C : security features + CAN-FD */
5181 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs },
5182 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs },
5183 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs },
5184 /* LX2xx2E : security features + CAN */
5185 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs },
5186 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs },
5187 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs },
5188 /* LX2xx2N : without security features + CAN */
5189 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs },
5190 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs },
5191 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
5192 /* Zhaoxin Root/Downstream Ports */
5193 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
5194 /* Wangxun nics */
5195 { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs },
5196 { 0 }
5197};
5198
5199/*
5200 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
5201 * @dev: PCI device
5202 * @acs_flags: Bitmask of desired ACS controls
5203 *
5204 * Returns:
5205 * -ENOTTY: No quirk applies to this device; we can't tell whether the
5206 * device provides the desired controls
5207 * 0: Device does not provide all the desired controls
5208 * >0: Device provides all the controls in @acs_flags
5209 */
5210int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
5211{
5212 const struct pci_dev_acs_enabled *i;
5213 int ret;
5214
5215 /*
5216 * Allow devices that do not expose standard PCIe ACS capabilities
5217 * or control to indicate their support here. Multi-function express
5218 * devices which do not allow internal peer-to-peer between functions,
5219 * but do not implement PCIe ACS may wish to return true here.
5220 */
5221 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
5222 if ((i->vendor == dev->vendor ||
5223 i->vendor == (u16)PCI_ANY_ID) &&
5224 (i->device == dev->device ||
5225 i->device == (u16)PCI_ANY_ID)) {
5226 ret = i->acs_enabled(dev, acs_flags);
5227 if (ret >= 0)
5228 return ret;
5229 }
5230 }
5231
5232 return -ENOTTY;
5233}
5234
5235/* Config space offset of Root Complex Base Address register */
5236#define INTEL_LPC_RCBA_REG 0xf0
5237/* 31:14 RCBA address */
5238#define INTEL_LPC_RCBA_MASK 0xffffc000
5239/* RCBA Enable */
5240#define INTEL_LPC_RCBA_ENABLE (1 << 0)
5241
5242/* Backbone Scratch Pad Register */
5243#define INTEL_BSPR_REG 0x1104
5244/* Backbone Peer Non-Posted Disable */
5245#define INTEL_BSPR_REG_BPNPD (1 << 8)
5246/* Backbone Peer Posted Disable */
5247#define INTEL_BSPR_REG_BPPD (1 << 9)
5248
5249/* Upstream Peer Decode Configuration Register */
5250#define INTEL_UPDCR_REG 0x1014
5251/* 5:0 Peer Decode Enable bits */
5252#define INTEL_UPDCR_REG_MASK 0x3f
5253
5254static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
5255{
5256 u32 rcba, bspr, updcr;
5257 void __iomem *rcba_mem;
5258
5259 /*
5260 * Read the RCBA register from the LPC (D31:F0). PCH root ports
5261 * are D28:F* and therefore get probed before LPC, thus we can't
5262 * use pci_get_slot()/pci_read_config_dword() here.
5263 */
5264 pci_bus_read_config_dword(bus: dev->bus, PCI_DEVFN(31, 0),
5265 INTEL_LPC_RCBA_REG, val: &rcba);
5266 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
5267 return -EINVAL;
5268
5269 rcba_mem = ioremap(offset: rcba & INTEL_LPC_RCBA_MASK,
5270 PAGE_ALIGN(INTEL_UPDCR_REG));
5271 if (!rcba_mem)
5272 return -ENOMEM;
5273
5274 /*
5275 * The BSPR can disallow peer cycles, but it's set by soft strap and
5276 * therefore read-only. If both posted and non-posted peer cycles are
5277 * disallowed, we're ok. If either are allowed, then we need to use
5278 * the UPDCR to disable peer decodes for each port. This provides the
5279 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
5280 */
5281 bspr = readl(addr: rcba_mem + INTEL_BSPR_REG);
5282 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
5283 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
5284 updcr = readl(addr: rcba_mem + INTEL_UPDCR_REG);
5285 if (updcr & INTEL_UPDCR_REG_MASK) {
5286 pci_info(dev, "Disabling UPDCR peer decodes\n");
5287 updcr &= ~INTEL_UPDCR_REG_MASK;
5288 writel(val: updcr, addr: rcba_mem + INTEL_UPDCR_REG);
5289 }
5290 }
5291
5292 iounmap(addr: rcba_mem);
5293 return 0;
5294}
5295
5296/* Miscellaneous Port Configuration register */
5297#define INTEL_MPC_REG 0xd8
5298/* MPC: Invalid Receive Bus Number Check Enable */
5299#define INTEL_MPC_REG_IRBNCE (1 << 26)
5300
5301static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
5302{
5303 u32 mpc;
5304
5305 /*
5306 * When enabled, the IRBNCE bit of the MPC register enables the
5307 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
5308 * ensures that requester IDs fall within the bus number range
5309 * of the bridge. Enable if not already.
5310 */
5311 pci_read_config_dword(dev, INTEL_MPC_REG, val: &mpc);
5312 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
5313 pci_info(dev, "Enabling MPC IRBNCE\n");
5314 mpc |= INTEL_MPC_REG_IRBNCE;
5315 pci_write_config_word(dev, INTEL_MPC_REG, val: mpc);
5316 }
5317}
5318
5319/*
5320 * Currently this quirk does the equivalent of
5321 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
5322 *
5323 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB,
5324 * if dev->external_facing || dev->untrusted
5325 */
5326static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
5327{
5328 if (!pci_quirk_intel_pch_acs_match(dev))
5329 return -ENOTTY;
5330
5331 if (pci_quirk_enable_intel_lpc_acs(dev)) {
5332 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
5333 return 0;
5334 }
5335
5336 pci_quirk_enable_intel_rp_mpc_acs(dev);
5337
5338 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
5339
5340 pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
5341
5342 return 0;
5343}
5344
5345static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
5346{
5347 int pos;
5348 u32 cap, ctrl;
5349
5350 if (!pci_quirk_intel_spt_pch_acs_match(dev))
5351 return -ENOTTY;
5352
5353 pos = dev->acs_cap;
5354 if (!pos)
5355 return -ENOTTY;
5356
5357 pci_read_config_dword(dev, where: pos + PCI_ACS_CAP, val: &cap);
5358 pci_read_config_dword(dev, where: pos + INTEL_SPT_ACS_CTRL, val: &ctrl);
5359
5360 ctrl |= (cap & PCI_ACS_SV);
5361 ctrl |= (cap & PCI_ACS_RR);
5362 ctrl |= (cap & PCI_ACS_CR);
5363 ctrl |= (cap & PCI_ACS_UF);
5364
5365 if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
5366 ctrl |= (cap & PCI_ACS_TB);
5367
5368 pci_write_config_dword(dev, where: pos + INTEL_SPT_ACS_CTRL, val: ctrl);
5369
5370 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
5371
5372 return 0;
5373}
5374
5375static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
5376{
5377 int pos;
5378 u32 cap, ctrl;
5379
5380 if (!pci_quirk_intel_spt_pch_acs_match(dev))
5381 return -ENOTTY;
5382
5383 pos = dev->acs_cap;
5384 if (!pos)
5385 return -ENOTTY;
5386
5387 pci_read_config_dword(dev, where: pos + PCI_ACS_CAP, val: &cap);
5388 pci_read_config_dword(dev, where: pos + INTEL_SPT_ACS_CTRL, val: &ctrl);
5389
5390 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
5391
5392 pci_write_config_dword(dev, where: pos + INTEL_SPT_ACS_CTRL, val: ctrl);
5393
5394 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
5395
5396 return 0;
5397}
5398
5399static const struct pci_dev_acs_ops {
5400 u16 vendor;
5401 u16 device;
5402 int (*enable_acs)(struct pci_dev *dev);
5403 int (*disable_acs_redir)(struct pci_dev *dev);
5404} pci_dev_acs_ops[] = {
5405 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5406 .enable_acs = pci_quirk_enable_intel_pch_acs,
5407 },
5408 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5409 .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
5410 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
5411 },
5412};
5413
5414int pci_dev_specific_enable_acs(struct pci_dev *dev)
5415{
5416 const struct pci_dev_acs_ops *p;
5417 int i, ret;
5418
5419 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5420 p = &pci_dev_acs_ops[i];
5421 if ((p->vendor == dev->vendor ||
5422 p->vendor == (u16)PCI_ANY_ID) &&
5423 (p->device == dev->device ||
5424 p->device == (u16)PCI_ANY_ID) &&
5425 p->enable_acs) {
5426 ret = p->enable_acs(dev);
5427 if (ret >= 0)
5428 return ret;
5429 }
5430 }
5431
5432 return -ENOTTY;
5433}
5434
5435int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
5436{
5437 const struct pci_dev_acs_ops *p;
5438 int i, ret;
5439
5440 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5441 p = &pci_dev_acs_ops[i];
5442 if ((p->vendor == dev->vendor ||
5443 p->vendor == (u16)PCI_ANY_ID) &&
5444 (p->device == dev->device ||
5445 p->device == (u16)PCI_ANY_ID) &&
5446 p->disable_acs_redir) {
5447 ret = p->disable_acs_redir(dev);
5448 if (ret >= 0)
5449 return ret;
5450 }
5451 }
5452
5453 return -ENOTTY;
5454}
5455
5456/*
5457 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5458 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
5459 * Next Capability pointer in the MSI Capability Structure should point to
5460 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5461 * the list.
5462 */
5463static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
5464{
5465 int pos, i = 0, ret;
5466 u8 next_cap;
5467 u16 reg16, *cap;
5468 struct pci_cap_saved_state *state;
5469
5470 /* Bail if the hardware bug is fixed */
5471 if (pdev->pcie_cap || pci_find_capability(dev: pdev, PCI_CAP_ID_EXP))
5472 return;
5473
5474 /* Bail if MSI Capability Structure is not found for some reason */
5475 pos = pci_find_capability(dev: pdev, PCI_CAP_ID_MSI);
5476 if (!pos)
5477 return;
5478
5479 /*
5480 * Bail if Next Capability pointer in the MSI Capability Structure
5481 * is not the expected incorrect 0x00.
5482 */
5483 pci_read_config_byte(dev: pdev, where: pos + 1, val: &next_cap);
5484 if (next_cap)
5485 return;
5486
5487 /*
5488 * PCIe Capability Structure is expected to be at 0x50 and should
5489 * terminate the list (Next Capability pointer is 0x00). Verify
5490 * Capability Id and Next Capability pointer is as expected.
5491 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
5492 * to correctly set kernel data structures which have already been
5493 * set incorrectly due to the hardware bug.
5494 */
5495 pos = 0x50;
5496 pci_read_config_word(dev: pdev, where: pos, val: &reg16);
5497 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
5498 u32 status;
5499#ifndef PCI_EXP_SAVE_REGS
5500#define PCI_EXP_SAVE_REGS 7
5501#endif
5502 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
5503
5504 pdev->pcie_cap = pos;
5505 pci_read_config_word(dev: pdev, where: pos + PCI_EXP_FLAGS, val: &reg16);
5506 pdev->pcie_flags_reg = reg16;
5507 pci_read_config_word(dev: pdev, where: pos + PCI_EXP_DEVCAP, val: &reg16);
5508 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
5509
5510 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
5511 ret = pci_read_config_dword(dev: pdev, PCI_CFG_SPACE_SIZE, val: &status);
5512 if ((ret != PCIBIOS_SUCCESSFUL) || (PCI_POSSIBLE_ERROR(status)))
5513 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
5514
5515 if (pci_find_saved_cap(dev: pdev, PCI_CAP_ID_EXP))
5516 return;
5517
5518 /* Save PCIe cap */
5519 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
5520 if (!state)
5521 return;
5522
5523 state->cap.cap_nr = PCI_CAP_ID_EXP;
5524 state->cap.cap_extended = 0;
5525 state->cap.size = size;
5526 cap = (u16 *)&state->cap.data[0];
5527 pcie_capability_read_word(dev: pdev, PCI_EXP_DEVCTL, val: &cap[i++]);
5528 pcie_capability_read_word(dev: pdev, PCI_EXP_LNKCTL, val: &cap[i++]);
5529 pcie_capability_read_word(dev: pdev, PCI_EXP_SLTCTL, val: &cap[i++]);
5530 pcie_capability_read_word(dev: pdev, PCI_EXP_RTCTL, val: &cap[i++]);
5531 pcie_capability_read_word(dev: pdev, PCI_EXP_DEVCTL2, val: &cap[i++]);
5532 pcie_capability_read_word(dev: pdev, PCI_EXP_LNKCTL2, val: &cap[i++]);
5533 pcie_capability_read_word(dev: pdev, PCI_EXP_SLTCTL2, val: &cap[i++]);
5534 hlist_add_head(n: &state->next, h: &pdev->saved_cap_space);
5535 }
5536}
5537DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5538
5539/*
5540 * FLR may cause the following to devices to hang:
5541 *
5542 * AMD Starship/Matisse HD Audio Controller 0x1487
5543 * AMD Starship USB 3.0 Host Controller 0x148c
5544 * AMD Matisse USB 3.0 Host Controller 0x149c
5545 * Intel 82579LM Gigabit Ethernet Controller 0x1502
5546 * Intel 82579V Gigabit Ethernet Controller 0x1503
5547 * Mediatek MT7922 802.11ax PCI Express Wireless Network Adapter
5548 */
5549static void quirk_no_flr(struct pci_dev *dev)
5550{
5551 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
5552}
5553DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
5554DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
5555DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
5556DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr);
5557DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
5558DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
5559DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MEDIATEK, 0x0616, quirk_no_flr);
5560
5561/* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */
5562static void quirk_no_flr_snet(struct pci_dev *dev)
5563{
5564 if (dev->revision == 0x1)
5565 quirk_no_flr(dev);
5566}
5567DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet);
5568
5569static void quirk_no_ext_tags(struct pci_dev *pdev)
5570{
5571 struct pci_host_bridge *bridge = pci_find_host_bridge(bus: pdev->bus);
5572
5573 if (!bridge)
5574 return;
5575
5576 bridge->no_ext_tags = 1;
5577 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
5578
5579 pci_walk_bus(top: bridge->bus, cb: pci_configure_extended_tags, NULL);
5580}
5581DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1004, quirk_no_ext_tags);
5582DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5583DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5584DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5585DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5586DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5587DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5588DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5589
5590#ifdef CONFIG_PCI_ATS
5591static void quirk_no_ats(struct pci_dev *pdev)
5592{
5593 pci_info(pdev, "disabling ATS\n");
5594 pdev->ats_cap = 0;
5595}
5596
5597/*
5598 * Some devices require additional driver setup to enable ATS. Don't use
5599 * ATS for those devices as ATS will be enabled before the driver has had a
5600 * chance to load and configure the device.
5601 */
5602static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
5603{
5604 if (pdev->device == 0x15d8) {
5605 if (pdev->revision == 0xcf &&
5606 pdev->subsystem_vendor == 0xea50 &&
5607 (pdev->subsystem_device == 0xce19 ||
5608 pdev->subsystem_device == 0xcc10 ||
5609 pdev->subsystem_device == 0xcc08))
5610 quirk_no_ats(pdev);
5611 } else {
5612 quirk_no_ats(pdev);
5613 }
5614}
5615
5616/* AMD Stoney platform GPU */
5617DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
5618/* AMD Iceland dGPU */
5619DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
5620/* AMD Navi10 dGPU */
5621DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats);
5622DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
5623DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats);
5624DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats);
5625DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats);
5626DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats);
5627DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats);
5628DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats);
5629/* AMD Navi14 dGPU */
5630DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
5631DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
5632DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats);
5633DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats);
5634/* AMD Raven platform iGPU */
5635DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);
5636
5637/*
5638 * Intel IPU E2000 revisions before C0 implement incorrect endianness
5639 * in ATS Invalidate Request message body. Disable ATS for those devices.
5640 */
5641static void quirk_intel_e2000_no_ats(struct pci_dev *pdev)
5642{
5643 if (pdev->revision < 0x20)
5644 quirk_no_ats(pdev);
5645}
5646DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats);
5647DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats);
5648DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats);
5649DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats);
5650DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats);
5651DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats);
5652DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats);
5653DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats);
5654DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats);
5655#endif /* CONFIG_PCI_ATS */
5656
5657/* Freescale PCIe doesn't support MSI in RC mode */
5658static void quirk_fsl_no_msi(struct pci_dev *pdev)
5659{
5660 if (pci_pcie_type(dev: pdev) == PCI_EXP_TYPE_ROOT_PORT)
5661 pdev->no_msi = 1;
5662}
5663DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5664
5665/*
5666 * Although not allowed by the spec, some multi-function devices have
5667 * dependencies of one function (consumer) on another (supplier). For the
5668 * consumer to work in D0, the supplier must also be in D0. Create a
5669 * device link from the consumer to the supplier to enforce this
5670 * dependency. Runtime PM is allowed by default on the consumer to prevent
5671 * it from permanently keeping the supplier awake.
5672 */
5673static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
5674 unsigned int supplier, unsigned int class,
5675 unsigned int class_shift)
5676{
5677 struct pci_dev *supplier_pdev;
5678
5679 if (PCI_FUNC(pdev->devfn) != consumer)
5680 return;
5681
5682 supplier_pdev = pci_get_domain_bus_and_slot(domain: pci_domain_nr(bus: pdev->bus),
5683 bus: pdev->bus->number,
5684 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
5685 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
5686 pci_dev_put(dev: supplier_pdev);
5687 return;
5688 }
5689
5690 if (device_link_add(consumer: &pdev->dev, supplier: &supplier_pdev->dev,
5691 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
5692 pci_info(pdev, "D0 power state depends on %s\n",
5693 pci_name(supplier_pdev));
5694 else
5695 pci_err(pdev, "Cannot enforce power dependency on %s\n",
5696 pci_name(supplier_pdev));
5697
5698 pm_runtime_allow(dev: &pdev->dev);
5699 pci_dev_put(dev: supplier_pdev);
5700}
5701
5702/*
5703 * Create device link for GPUs with integrated HDA controller for streaming
5704 * audio to attached displays.
5705 */
5706static void quirk_gpu_hda(struct pci_dev *hda)
5707{
5708 pci_create_device_link(pdev: hda, consumer: 1, supplier: 0, PCI_BASE_CLASS_DISPLAY, class_shift: 16);
5709}
5710DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5711 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5712DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
5713 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5714DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5715 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5716
5717/*
5718 * Create device link for GPUs with integrated USB xHCI Host
5719 * controller to VGA.
5720 */
5721static void quirk_gpu_usb(struct pci_dev *usb)
5722{
5723 pci_create_device_link(pdev: usb, consumer: 2, supplier: 0, PCI_BASE_CLASS_DISPLAY, class_shift: 16);
5724}
5725DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5726 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5727DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5728 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5729
5730/*
5731 * Create device link for GPUs with integrated Type-C UCSI controller
5732 * to VGA. Currently there is no class code defined for UCSI device over PCI
5733 * so using UNKNOWN class for now and it will be updated when UCSI
5734 * over PCI gets a class code.
5735 */
5736#define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5737static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
5738{
5739 pci_create_device_link(pdev: ucsi, consumer: 3, supplier: 0, PCI_BASE_CLASS_DISPLAY, class_shift: 16);
5740}
5741DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5742 PCI_CLASS_SERIAL_UNKNOWN, 8,
5743 quirk_gpu_usb_typec_ucsi);
5744DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5745 PCI_CLASS_SERIAL_UNKNOWN, 8,
5746 quirk_gpu_usb_typec_ucsi);
5747
5748/*
5749 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5750 * disabled. https://devtalk.nvidia.com/default/topic/1024022
5751 */
5752static void quirk_nvidia_hda(struct pci_dev *gpu)
5753{
5754 u8 hdr_type;
5755 u32 val;
5756
5757 /* There was no integrated HDA controller before MCP89 */
5758 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
5759 return;
5760
5761 /* Bit 25 at offset 0x488 enables the HDA controller */
5762 pci_read_config_dword(dev: gpu, where: 0x488, val: &val);
5763 if (val & BIT(25))
5764 return;
5765
5766 pci_info(gpu, "Enabling HDA controller\n");
5767 pci_write_config_dword(dev: gpu, where: 0x488, val: val | BIT(25));
5768
5769 /* The GPU becomes a multi-function device when the HDA is enabled */
5770 pci_read_config_byte(dev: gpu, PCI_HEADER_TYPE, val: &hdr_type);
5771 gpu->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr_type);
5772}
5773DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5774 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5775DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5776 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5777
5778/*
5779 * Some IDT switches incorrectly flag an ACS Source Validation error on
5780 * completions for config read requests even though PCIe r4.0, sec
5781 * 6.12.1.1, says that completions are never affected by ACS Source
5782 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5783 *
5784 * Item #36 - Downstream port applies ACS Source Validation to Completions
5785 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5786 * completions are never affected by ACS Source Validation. However,
5787 * completions received by a downstream port of the PCIe switch from a
5788 * device that has not yet captured a PCIe bus number are incorrectly
5789 * dropped by ACS Source Validation by the switch downstream port.
5790 *
5791 * The workaround suggested by IDT is to issue a config write to the
5792 * downstream device before issuing the first config read. This allows the
5793 * downstream device to capture its bus and device numbers (see PCIe r4.0,
5794 * sec 2.2.9), thus avoiding the ACS error on the completion.
5795 *
5796 * However, we don't know when the device is ready to accept the config
5797 * write, so we do config reads until we receive a non-Config Request Retry
5798 * Status, then do the config write.
5799 *
5800 * To avoid hitting the erratum when doing the config reads, we disable ACS
5801 * SV around this process.
5802 */
5803int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
5804{
5805 int pos;
5806 u16 ctrl = 0;
5807 bool found;
5808 struct pci_dev *bridge = bus->self;
5809
5810 pos = bridge->acs_cap;
5811
5812 /* Disable ACS SV before initial config reads */
5813 if (pos) {
5814 pci_read_config_word(dev: bridge, where: pos + PCI_ACS_CTRL, val: &ctrl);
5815 if (ctrl & PCI_ACS_SV)
5816 pci_write_config_word(dev: bridge, where: pos + PCI_ACS_CTRL,
5817 val: ctrl & ~PCI_ACS_SV);
5818 }
5819
5820 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, pl: l, rrs_timeout: timeout);
5821
5822 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5823 if (found)
5824 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, val: 0);
5825
5826 /* Re-enable ACS_SV if it was previously enabled */
5827 if (ctrl & PCI_ACS_SV)
5828 pci_write_config_word(dev: bridge, where: pos + PCI_ACS_CTRL, val: ctrl);
5829
5830 return found;
5831}
5832
5833/*
5834 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5835 * NT endpoints via the internal switch fabric. These IDs replace the
5836 * originating Requester ID TLPs which access host memory on peer NTB
5837 * ports. Therefore, all proxy IDs must be aliased to the NTB device
5838 * to permit access when the IOMMU is turned on.
5839 */
5840static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
5841{
5842 void __iomem *mmio;
5843 struct ntb_info_regs __iomem *mmio_ntb;
5844 struct ntb_ctrl_regs __iomem *mmio_ctrl;
5845 u64 partition_map;
5846 u8 partition;
5847 int pp;
5848
5849 if (pci_enable_device(dev: pdev)) {
5850 pci_err(pdev, "Cannot enable Switchtec device\n");
5851 return;
5852 }
5853
5854 mmio = pci_iomap(dev: pdev, bar: 0, max: 0);
5855 if (mmio == NULL) {
5856 pci_disable_device(dev: pdev);
5857 pci_err(pdev, "Cannot iomap Switchtec device\n");
5858 return;
5859 }
5860
5861 pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
5862
5863 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
5864 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
5865
5866 partition = ioread8(&mmio_ntb->partition_id);
5867
5868 partition_map = ioread32(&mmio_ntb->ep_map);
5869 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
5870 partition_map &= ~(1ULL << partition);
5871
5872 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
5873 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
5874 u32 table_sz = 0;
5875 int te;
5876
5877 if (!(partition_map & (1ULL << pp)))
5878 continue;
5879
5880 pci_dbg(pdev, "Processing partition %d\n", pp);
5881
5882 mmio_peer_ctrl = &mmio_ctrl[pp];
5883
5884 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
5885 if (!table_sz) {
5886 pci_warn(pdev, "Partition %d table_sz 0\n", pp);
5887 continue;
5888 }
5889
5890 if (table_sz > 512) {
5891 pci_warn(pdev,
5892 "Invalid Switchtec partition %d table_sz %d\n",
5893 pp, table_sz);
5894 continue;
5895 }
5896
5897 for (te = 0; te < table_sz; te++) {
5898 u32 rid_entry;
5899 u8 devfn;
5900
5901 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
5902 devfn = (rid_entry >> 1) & 0xFF;
5903 pci_dbg(pdev,
5904 "Aliasing Partition %d Proxy ID %02x.%d\n",
5905 pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
5906 pci_add_dma_alias(dev: pdev, devfn_from: devfn, nr_devfns: 1);
5907 }
5908 }
5909
5910 pci_iounmap(dev: pdev, mmio);
5911 pci_disable_device(dev: pdev);
5912}
5913#define SWITCHTEC_QUIRK(vid) \
5914 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5915 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5916
5917SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5918SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5919SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5920SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5921SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5922SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5923SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5924SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5925SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5926SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5927SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5928SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5929SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5930SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5931SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5932SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5933SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5934SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5935SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5936SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5937SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5938SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5939SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5940SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5941SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5942SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5943SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5944SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5945SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5946SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5947SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */
5948SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */
5949SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */
5950SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */
5951SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */
5952SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */
5953SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */
5954SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */
5955SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */
5956SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */
5957SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */
5958SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */
5959SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */
5960SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */
5961SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */
5962SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */
5963SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */
5964SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */
5965SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */
5966SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */
5967SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */
5968SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */
5969SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */
5970SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */
5971SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */
5972SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */
5973SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */
5974SWITCHTEC_QUIRK(0x5000); /* PFX 100XG5 */
5975SWITCHTEC_QUIRK(0x5084); /* PFX 84XG5 */
5976SWITCHTEC_QUIRK(0x5068); /* PFX 68XG5 */
5977SWITCHTEC_QUIRK(0x5052); /* PFX 52XG5 */
5978SWITCHTEC_QUIRK(0x5036); /* PFX 36XG5 */
5979SWITCHTEC_QUIRK(0x5028); /* PFX 28XG5 */
5980SWITCHTEC_QUIRK(0x5100); /* PSX 100XG5 */
5981SWITCHTEC_QUIRK(0x5184); /* PSX 84XG5 */
5982SWITCHTEC_QUIRK(0x5168); /* PSX 68XG5 */
5983SWITCHTEC_QUIRK(0x5152); /* PSX 52XG5 */
5984SWITCHTEC_QUIRK(0x5136); /* PSX 36XG5 */
5985SWITCHTEC_QUIRK(0x5128); /* PSX 28XG5 */
5986SWITCHTEC_QUIRK(0x5200); /* PAX 100XG5 */
5987SWITCHTEC_QUIRK(0x5284); /* PAX 84XG5 */
5988SWITCHTEC_QUIRK(0x5268); /* PAX 68XG5 */
5989SWITCHTEC_QUIRK(0x5252); /* PAX 52XG5 */
5990SWITCHTEC_QUIRK(0x5236); /* PAX 36XG5 */
5991SWITCHTEC_QUIRK(0x5228); /* PAX 28XG5 */
5992SWITCHTEC_QUIRK(0x5300); /* PFXA 100XG5 */
5993SWITCHTEC_QUIRK(0x5384); /* PFXA 84XG5 */
5994SWITCHTEC_QUIRK(0x5368); /* PFXA 68XG5 */
5995SWITCHTEC_QUIRK(0x5352); /* PFXA 52XG5 */
5996SWITCHTEC_QUIRK(0x5336); /* PFXA 36XG5 */
5997SWITCHTEC_QUIRK(0x5328); /* PFXA 28XG5 */
5998SWITCHTEC_QUIRK(0x5400); /* PSXA 100XG5 */
5999SWITCHTEC_QUIRK(0x5484); /* PSXA 84XG5 */
6000SWITCHTEC_QUIRK(0x5468); /* PSXA 68XG5 */
6001SWITCHTEC_QUIRK(0x5452); /* PSXA 52XG5 */
6002SWITCHTEC_QUIRK(0x5436); /* PSXA 36XG5 */
6003SWITCHTEC_QUIRK(0x5428); /* PSXA 28XG5 */
6004SWITCHTEC_QUIRK(0x5500); /* PAXA 100XG5 */
6005SWITCHTEC_QUIRK(0x5584); /* PAXA 84XG5 */
6006SWITCHTEC_QUIRK(0x5568); /* PAXA 68XG5 */
6007SWITCHTEC_QUIRK(0x5552); /* PAXA 52XG5 */
6008SWITCHTEC_QUIRK(0x5536); /* PAXA 36XG5 */
6009SWITCHTEC_QUIRK(0x5528); /* PAXA 28XG5 */
6010
6011#define SWITCHTEC_PCI100X_QUIRK(vid) \
6012 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_EFAR, vid, \
6013 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
6014SWITCHTEC_PCI100X_QUIRK(0x1001); /* PCI1001XG4 */
6015SWITCHTEC_PCI100X_QUIRK(0x1002); /* PCI1002XG4 */
6016SWITCHTEC_PCI100X_QUIRK(0x1003); /* PCI1003XG4 */
6017SWITCHTEC_PCI100X_QUIRK(0x1004); /* PCI1004XG4 */
6018SWITCHTEC_PCI100X_QUIRK(0x1005); /* PCI1005XG4 */
6019SWITCHTEC_PCI100X_QUIRK(0x1006); /* PCI1006XG4 */
6020
6021
6022/*
6023 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints.
6024 * These IDs are used to forward responses to the originator on the other
6025 * side of the NTB. Alias all possible IDs to the NTB to permit access when
6026 * the IOMMU is turned on.
6027 */
6028static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev)
6029{
6030 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n");
6031 /* PLX NTB may use all 256 devfns */
6032 pci_add_dma_alias(dev: pdev, devfn_from: 0, nr_devfns: 256);
6033}
6034DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
6035DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
6036
6037/*
6038 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
6039 * not always reset the secondary Nvidia GPU between reboots if the system
6040 * is configured to use Hybrid Graphics mode. This results in the GPU
6041 * being left in whatever state it was in during the *previous* boot, which
6042 * causes spurious interrupts from the GPU, which in turn causes us to
6043 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
6044 * this also completely breaks nouveau.
6045 *
6046 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
6047 * clean state and fixes all these issues.
6048 *
6049 * When the machine is configured in Dedicated display mode, the issue
6050 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
6051 * mode, so we can detect that and avoid resetting it.
6052 */
6053static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
6054{
6055 void __iomem *map;
6056 int ret;
6057
6058 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
6059 pdev->subsystem_device != 0x222e ||
6060 !pci_reset_supported(dev: pdev))
6061 return;
6062
6063 if (pci_enable_device_mem(dev: pdev))
6064 return;
6065
6066 /*
6067 * Based on nvkm_device_ctor() in
6068 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
6069 */
6070 map = pci_iomap(dev: pdev, bar: 0, max: 0x23000);
6071 if (!map) {
6072 pci_err(pdev, "Can't map MMIO space\n");
6073 goto out_disable;
6074 }
6075
6076 /*
6077 * Make sure the GPU looks like it's been POSTed before resetting
6078 * it.
6079 */
6080 if (ioread32(map + 0x2240c) & 0x2) {
6081 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
6082 ret = pci_reset_bus(dev: pdev);
6083 if (ret < 0)
6084 pci_err(pdev, "Failed to reset GPU: %d\n", ret);
6085 }
6086
6087 iounmap(addr: map);
6088out_disable:
6089 pci_disable_device(dev: pdev);
6090}
6091DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
6092 PCI_CLASS_DISPLAY_VGA, 8,
6093 quirk_reset_lenovo_thinkpad_p50_nvgpu);
6094
6095/*
6096 * Device [1b21:2142]
6097 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device.
6098 */
6099static void pci_fixup_no_d0_pme(struct pci_dev *dev)
6100{
6101 pci_info(dev, "PME# does not work under D0, disabling it\n");
6102 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
6103}
6104DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
6105
6106/*
6107 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI]
6108 *
6109 * These devices advertise PME# support in all power states but don't
6110 * reliably assert it.
6111 *
6112 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf)
6113 * says "The MSI Function is not implemented on this device" in chapters
6114 * 7.3.27, 7.3.29-7.3.31.
6115 */
6116static void pci_fixup_no_msi_no_pme(struct pci_dev *dev)
6117{
6118#ifdef CONFIG_PCI_MSI
6119 pci_info(dev, "MSI is not implemented on this device, disabling it\n");
6120 dev->no_msi = 1;
6121#endif
6122 pci_info(dev, "PME# is unreliable, disabling it\n");
6123 dev->pme_support = 0;
6124}
6125DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme);
6126DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme);
6127
6128static void apex_pci_fixup_class(struct pci_dev *pdev)
6129{
6130 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
6131}
6132DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
6133 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
6134
6135/*
6136 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 -
6137 * ACS P2P Request Redirect is not functional
6138 *
6139 * When ACS P2P Request Redirect is enabled and bandwidth is not balanced
6140 * between upstream and downstream ports, packets are queued in an internal
6141 * buffer until CPLD packet. The workaround is to use the switch in store and
6142 * forward mode.
6143 */
6144#define PI7C9X2Gxxx_MODE_REG 0x74
6145#define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0)
6146static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev)
6147{
6148 struct pci_dev *upstream;
6149 u16 val;
6150
6151 /* Downstream ports only */
6152 if (pci_pcie_type(dev: pdev) != PCI_EXP_TYPE_DOWNSTREAM)
6153 return;
6154
6155 /* Check for ACS P2P Request Redirect use */
6156 if (!pdev->acs_cap)
6157 return;
6158 pci_read_config_word(dev: pdev, where: pdev->acs_cap + PCI_ACS_CTRL, val: &val);
6159 if (!(val & PCI_ACS_RR))
6160 return;
6161
6162 upstream = pci_upstream_bridge(dev: pdev);
6163 if (!upstream)
6164 return;
6165
6166 pci_read_config_word(dev: upstream, PI7C9X2Gxxx_MODE_REG, val: &val);
6167 if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) {
6168 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n");
6169 pci_write_config_word(dev: upstream, PI7C9X2Gxxx_MODE_REG, val: val |
6170 PI7C9X2Gxxx_STORE_FORWARD_MODE);
6171 }
6172}
6173/*
6174 * Apply fixup on enable and on resume, in order to apply the fix up whenever
6175 * ACS configuration changes or switch mode is reset
6176 */
6177DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404,
6178 pci_fixup_pericom_acs_store_forward);
6179DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404,
6180 pci_fixup_pericom_acs_store_forward);
6181DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304,
6182 pci_fixup_pericom_acs_store_forward);
6183DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304,
6184 pci_fixup_pericom_acs_store_forward);
6185DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303,
6186 pci_fixup_pericom_acs_store_forward);
6187DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303,
6188 pci_fixup_pericom_acs_store_forward);
6189
6190static void nvidia_ion_ahci_fixup(struct pci_dev *pdev)
6191{
6192 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
6193}
6194DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
6195
6196static void rom_bar_overlap_defect(struct pci_dev *dev)
6197{
6198 pci_info(dev, "working around ROM BAR overlap defect\n");
6199 dev->rom_bar_overlap = 1;
6200}
6201DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect);
6202DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect);
6203DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect);
6204DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect);
6205
6206#ifdef CONFIG_PCIEASPM
6207/*
6208 * Several Intel DG2 graphics devices advertise that they can only tolerate
6209 * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1
6210 * from being enabled. But in fact these devices can tolerate unlimited
6211 * latency. Override their Device Capabilities value to allow ASPM L1 to
6212 * be enabled.
6213 */
6214static void aspm_l1_acceptable_latency(struct pci_dev *dev)
6215{
6216 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap);
6217
6218 if (l1_lat < 7) {
6219 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7);
6220 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n",
6221 l1_lat);
6222 }
6223}
6224DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency);
6225DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency);
6226DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency);
6227DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency);
6228DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency);
6229DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency);
6230DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency);
6231DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency);
6232DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency);
6233DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency);
6234DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency);
6235DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency);
6236DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency);
6237DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency);
6238DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency);
6239DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency);
6240DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency);
6241DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency);
6242DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency);
6243DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency);
6244DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency);
6245DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency);
6246DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency);
6247DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency);
6248DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
6249DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
6250#endif
6251
6252#ifdef CONFIG_PCIE_DPC
6253/*
6254 * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears
6255 * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root
6256 * Ports.
6257 */
6258static void dpc_log_size(struct pci_dev *dev)
6259{
6260 u16 dpc, val;
6261
6262 dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC);
6263 if (!dpc)
6264 return;
6265
6266 pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val);
6267 if (!(val & PCI_EXP_DPC_CAP_RP_EXT))
6268 return;
6269
6270 if (FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, val) == 0) {
6271 pci_info(dev, "Overriding RP PIO Log Size to %d\n",
6272 PCIE_STD_NUM_TLP_HEADERLOG);
6273 dev->dpc_rp_log_size = PCIE_STD_NUM_TLP_HEADERLOG;
6274 }
6275}
6276DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size);
6277DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size);
6278DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size);
6279DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size);
6280DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size);
6281DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size);
6282DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size);
6283DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size);
6284DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size);
6285DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size);
6286DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size);
6287DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size);
6288DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size);
6289DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size);
6290DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
6291DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
6292DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa72f, dpc_log_size);
6293DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa73f, dpc_log_size);
6294DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size);
6295#endif
6296
6297/*
6298 * For a PCI device with multiple downstream devices, its driver may use
6299 * a flattened device tree to describe the downstream devices.
6300 * To overlay the flattened device tree, the PCI device and all its ancestor
6301 * devices need to have device tree nodes on system base device tree. Thus,
6302 * before driver probing, it might need to add a device tree node as the final
6303 * fixup.
6304 */
6305DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node);
6306DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);
6307DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);
6308DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node);
6309DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RPI, PCI_DEVICE_ID_RPI_RP1_C0, of_pci_make_dev_node);
6310
6311/*
6312 * Devices known to require a longer delay before first config space access
6313 * after reset recovery or resume from D3cold:
6314 *
6315 * VideoPropulsion (aka Genroco) Torrent QN16e MPEG QAM Modulator
6316 */
6317static void pci_fixup_d3cold_delay_1sec(struct pci_dev *pdev)
6318{
6319 pdev->d3cold_delay = 1000;
6320}
6321DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec);
6322
6323#ifdef CONFIG_PCIEAER
6324static void pci_mask_replay_timer_timeout(struct pci_dev *pdev)
6325{
6326 struct pci_dev *parent = pci_upstream_bridge(pdev);
6327 u32 val;
6328
6329 if (!parent || !parent->aer_cap)
6330 return;
6331
6332 pci_info(parent, "mask Replay Timer Timeout Correctable Errors due to %s hardware defect",
6333 pci_name(pdev));
6334
6335 pci_read_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, &val);
6336 val |= PCI_ERR_COR_REP_TIMER;
6337 pci_write_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, val);
6338}
6339DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout);
6340DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout);
6341#endif
6342