1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Support routines for initializing a PCI subsystem
4 *
5 * Extruded from code written by
6 * Dave Rusling (david.rusling@reo.mts.dec.com)
7 * David Mosberger (davidm@cs.arizona.edu)
8 * David Miller (davem@redhat.com)
9 *
10 * Fixed for multiple PCI buses, 1999 Andrea Arcangeli <andrea@suse.de>
11 *
12 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
13 * Resource sorting
14 */
15
16#include <linux/kernel.h>
17#include <linux/export.h>
18#include <linux/pci.h>
19#include <linux/errno.h>
20#include <linux/ioport.h>
21#include <linux/cache.h>
22#include <linux/slab.h>
23#include "pci.h"
24
25static void pci_std_update_resource(struct pci_dev *dev, int resno)
26{
27 struct pci_bus_region region;
28 bool disable;
29 u16 cmd;
30 u32 new, check, mask;
31 int reg;
32 struct resource *res = pci_resource_n(dev, resno);
33 const char *res_name = pci_resource_name(dev, i: resno);
34
35 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
36 if (dev->is_virtfn)
37 return;
38
39 /*
40 * Ignore resources for unimplemented BARs and unused resource slots
41 * for 64 bit BARs.
42 */
43 if (!res->flags)
44 return;
45
46 if (res->flags & IORESOURCE_UNSET)
47 return;
48
49 /*
50 * Ignore non-moveable resources. This might be legacy resources for
51 * which no functional BAR register exists or another important
52 * system resource we shouldn't move around.
53 */
54 if (res->flags & IORESOURCE_PCI_FIXED)
55 return;
56
57 pcibios_resource_to_bus(bus: dev->bus, region: &region, res);
58 new = region.start;
59
60 if (res->flags & IORESOURCE_IO) {
61 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
62 new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
63 } else if (resno == PCI_ROM_RESOURCE) {
64 mask = PCI_ROM_ADDRESS_MASK;
65 } else {
66 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
67 new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
68 }
69
70 if (resno < PCI_ROM_RESOURCE) {
71 reg = PCI_BASE_ADDRESS_0 + 4 * resno;
72 } else if (resno == PCI_ROM_RESOURCE) {
73
74 /*
75 * Apparently some Matrox devices have ROM BARs that read
76 * as zero when disabled, so don't update ROM BARs unless
77 * they're enabled. See
78 * https://lore.kernel.org/r/43147B3D.1030309@vc.cvut.cz/
79 * But we must update ROM BAR for buggy devices where even a
80 * disabled ROM can conflict with other BARs.
81 */
82 if (!(res->flags & IORESOURCE_ROM_ENABLE) &&
83 !dev->rom_bar_overlap)
84 return;
85
86 reg = dev->rom_base_reg;
87 if (res->flags & IORESOURCE_ROM_ENABLE)
88 new |= PCI_ROM_ADDRESS_ENABLE;
89 } else
90 return;
91
92 /*
93 * We can't update a 64-bit BAR atomically, so when possible,
94 * disable decoding so that a half-updated BAR won't conflict
95 * with another device.
96 */
97 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
98 if (disable) {
99 pci_read_config_word(dev, PCI_COMMAND, val: &cmd);
100 pci_write_config_word(dev, PCI_COMMAND,
101 val: cmd & ~PCI_COMMAND_MEMORY);
102 }
103
104 pci_write_config_dword(dev, where: reg, val: new);
105 pci_read_config_dword(dev, where: reg, val: &check);
106
107 if ((new ^ check) & mask) {
108 pci_err(dev, "%s: error updating (%#010x != %#010x)\n",
109 res_name, new, check);
110 }
111
112 if (res->flags & IORESOURCE_MEM_64) {
113 new = region.start >> 16 >> 16;
114 pci_write_config_dword(dev, where: reg + 4, val: new);
115 pci_read_config_dword(dev, where: reg + 4, val: &check);
116 if (check != new) {
117 pci_err(dev, "%s: error updating (high %#010x != %#010x)\n",
118 res_name, new, check);
119 }
120 }
121
122 if (disable)
123 pci_write_config_word(dev, PCI_COMMAND, val: cmd);
124}
125
126void pci_update_resource(struct pci_dev *dev, int resno)
127{
128 if (resno <= PCI_ROM_RESOURCE)
129 pci_std_update_resource(dev, resno);
130 else if (pci_resource_is_iov(resno))
131 pci_iov_update_resource(dev, resno);
132}
133
134int pci_claim_resource(struct pci_dev *dev, int resource)
135{
136 struct resource *res = &dev->resource[resource];
137 const char *res_name = pci_resource_name(dev, i: resource);
138 struct resource *root, *conflict;
139
140 if (res->flags & IORESOURCE_UNSET) {
141 pci_info(dev, "%s %pR: can't claim; no address assigned\n",
142 res_name, res);
143 return -EINVAL;
144 }
145
146 /*
147 * If we have a shadow copy in RAM, the PCI device doesn't respond
148 * to the shadow range, so we don't need to claim it, and upstream
149 * bridges don't need to route the range to the device.
150 */
151 if (res->flags & IORESOURCE_ROM_SHADOW)
152 return 0;
153
154 root = pci_find_parent_resource(dev, res);
155 if (!root) {
156 pci_info(dev, "%s %pR: can't claim; no compatible bridge window\n",
157 res_name, res);
158 res->flags |= IORESOURCE_UNSET;
159 return -EINVAL;
160 }
161
162 conflict = request_resource_conflict(root, new: res);
163 if (conflict) {
164 pci_info(dev, "%s %pR: can't claim; address conflict with %s %pR\n",
165 res_name, res, conflict->name, conflict);
166 res->flags |= IORESOURCE_UNSET;
167 return -EBUSY;
168 }
169
170 return 0;
171}
172EXPORT_SYMBOL(pci_claim_resource);
173
174void pci_disable_bridge_window(struct pci_dev *dev)
175{
176 /* MMIO Base/Limit */
177 pci_write_config_dword(dev, PCI_MEMORY_BASE, val: 0x0000fff0);
178
179 /* Prefetchable MMIO Base/Limit */
180 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, val: 0);
181 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, val: 0x0000fff0);
182 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, val: 0xffffffff);
183}
184
185/*
186 * Generic function that returns a value indicating that the device's
187 * original BIOS BAR address was not saved and so is not available for
188 * reinstatement.
189 *
190 * Can be over-ridden by architecture specific code that implements
191 * reinstatement functionality rather than leaving it disabled when
192 * normal allocation attempts fail.
193 */
194resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
195{
196 return 0;
197}
198
199static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
200 int resno, resource_size_t size)
201{
202 struct resource *root, *conflict;
203 resource_size_t fw_addr, start, end;
204 const char *res_name = pci_resource_name(dev, i: resno);
205
206 fw_addr = pcibios_retrieve_fw_addr(dev, idx: resno);
207 if (!fw_addr)
208 return -ENOMEM;
209
210 start = res->start;
211 end = res->end;
212 resource_set_range(res, start: fw_addr, size);
213 res->flags &= ~IORESOURCE_UNSET;
214
215 root = pci_find_parent_resource(dev, res);
216 if (!root) {
217 /*
218 * If dev is behind a bridge, accesses will only reach it
219 * if res is inside the relevant bridge window.
220 */
221 if (pci_upstream_bridge(dev))
222 return -ENXIO;
223
224 /*
225 * On the root bus, assume the host bridge will forward
226 * everything.
227 */
228 if (res->flags & IORESOURCE_IO)
229 root = &ioport_resource;
230 else
231 root = &iomem_resource;
232 }
233
234 pci_info(dev, "%s: trying firmware assignment %pR\n", res_name, res);
235 conflict = request_resource_conflict(root, new: res);
236 if (conflict) {
237 pci_info(dev, "%s %pR: conflicts with %s %pR\n", res_name, res,
238 conflict->name, conflict);
239 res->start = start;
240 res->end = end;
241 res->flags |= IORESOURCE_UNSET;
242 return -EBUSY;
243 }
244 return 0;
245}
246
247/*
248 * We don't have to worry about legacy ISA devices, so nothing to do here.
249 * This is marked as __weak because multiple architectures define it; it should
250 * eventually go away.
251 */
252resource_size_t __weak pcibios_align_resource(void *data,
253 const struct resource *res,
254 resource_size_t size,
255 resource_size_t align)
256{
257 return res->start;
258}
259
260static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
261 int resno, resource_size_t size, resource_size_t align)
262{
263 struct resource *res = pci_resource_n(dev, resno);
264 resource_size_t min;
265 int ret;
266
267 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
268
269 /*
270 * First, try exact prefetching match. Even if a 64-bit
271 * prefetchable bridge window is below 4GB, we can't put a 32-bit
272 * prefetchable resource in it because pbus_size_mem() assumes a
273 * 64-bit window will contain no 32-bit resources. If we assign
274 * things differently than they were sized, not everything will fit.
275 */
276 ret = pci_bus_alloc_resource(bus, res, size, align, min,
277 IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
278 alignf: pcibios_align_resource, alignf_data: dev);
279 if (ret == 0)
280 return 0;
281
282 /*
283 * If the prefetchable window is only 32 bits wide, we can put
284 * 64-bit prefetchable resources in it.
285 */
286 if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
287 (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
288 ret = pci_bus_alloc_resource(bus, res, size, align, min,
289 IORESOURCE_PREFETCH,
290 alignf: pcibios_align_resource, alignf_data: dev);
291 if (ret == 0)
292 return 0;
293 }
294
295 /*
296 * If we didn't find a better match, we can put any memory resource
297 * in a non-prefetchable window. If this resource is 32 bits and
298 * non-prefetchable, the first call already tried the only possibility
299 * so we don't need to try again.
300 */
301 if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
302 ret = pci_bus_alloc_resource(bus, res, size, align, min, type_mask: 0,
303 alignf: pcibios_align_resource, alignf_data: dev);
304
305 return ret;
306}
307
308static int _pci_assign_resource(struct pci_dev *dev, int resno,
309 resource_size_t size, resource_size_t min_align)
310{
311 struct pci_bus *bus;
312 int ret;
313
314 bus = dev->bus;
315 while ((ret = __pci_assign_resource(bus, dev, resno, size, align: min_align))) {
316 if (!bus->parent || !bus->self->transparent)
317 break;
318 bus = bus->parent;
319 }
320
321 return ret;
322}
323
324int pci_assign_resource(struct pci_dev *dev, int resno)
325{
326 struct resource *res = pci_resource_n(dev, resno);
327 const char *res_name = pci_resource_name(dev, i: resno);
328 resource_size_t align, size;
329 int ret;
330
331 if (res->flags & IORESOURCE_PCI_FIXED)
332 return 0;
333
334 res->flags |= IORESOURCE_UNSET;
335 align = pci_resource_alignment(dev, res);
336 if (!align) {
337 pci_info(dev, "%s %pR: can't assign; bogus alignment\n",
338 res_name, res);
339 return -EINVAL;
340 }
341
342 size = resource_size(res);
343 ret = _pci_assign_resource(dev, resno, size, min_align: align);
344
345 /*
346 * If we failed to assign anything, let's try the address
347 * where firmware left it. That at least has a chance of
348 * working, which is better than just leaving it disabled.
349 */
350 if (ret < 0) {
351 pci_info(dev, "%s %pR: can't assign; no space\n", res_name, res);
352 ret = pci_revert_fw_address(res, dev, resno, size);
353 }
354
355 if (ret < 0) {
356 pci_info(dev, "%s %pR: failed to assign\n", res_name, res);
357 return ret;
358 }
359
360 res->flags &= ~IORESOURCE_UNSET;
361 res->flags &= ~IORESOURCE_STARTALIGN;
362 if (resno >= PCI_BRIDGE_RESOURCES && resno <= PCI_BRIDGE_RESOURCE_END)
363 res->flags &= ~IORESOURCE_DISABLED;
364
365 pci_info(dev, "%s %pR: assigned\n", res_name, res);
366 if (resno < PCI_BRIDGE_RESOURCES)
367 pci_update_resource(dev, resno);
368
369 return 0;
370}
371EXPORT_SYMBOL(pci_assign_resource);
372
373int pci_reassign_resource(struct pci_dev *dev, int resno,
374 resource_size_t addsize, resource_size_t min_align)
375{
376 struct resource *res = pci_resource_n(dev, resno);
377 const char *res_name = pci_resource_name(dev, i: resno);
378 unsigned long flags;
379 resource_size_t new_size;
380 int ret;
381
382 if (res->flags & IORESOURCE_PCI_FIXED)
383 return 0;
384
385 flags = res->flags;
386 res->flags |= IORESOURCE_UNSET;
387 if (!res->parent) {
388 pci_info(dev, "%s %pR: can't reassign; unassigned resource\n",
389 res_name, res);
390 return -EINVAL;
391 }
392
393 new_size = resource_size(res) + addsize;
394 ret = _pci_assign_resource(dev, resno, size: new_size, min_align);
395 if (ret) {
396 res->flags = flags;
397 pci_info(dev, "%s %pR: failed to expand by %#llx\n",
398 res_name, res, (unsigned long long) addsize);
399 return ret;
400 }
401
402 res->flags &= ~IORESOURCE_UNSET;
403 res->flags &= ~IORESOURCE_STARTALIGN;
404 pci_info(dev, "%s %pR: reassigned; expanded by %#llx\n",
405 res_name, res, (unsigned long long) addsize);
406 if (resno < PCI_BRIDGE_RESOURCES)
407 pci_update_resource(dev, resno);
408
409 return 0;
410}
411
412int pci_release_resource(struct pci_dev *dev, int resno)
413{
414 struct resource *res = pci_resource_n(dev, resno);
415 const char *res_name = pci_resource_name(dev, i: resno);
416 int ret;
417
418 if (!res->parent)
419 return 0;
420
421 pci_info(dev, "%s %pR: releasing\n", res_name, res);
422
423 ret = release_resource(new: res);
424 if (ret)
425 return ret;
426 res->end = resource_size(res) - 1;
427 res->start = 0;
428 res->flags |= IORESOURCE_UNSET;
429
430 return 0;
431}
432EXPORT_SYMBOL(pci_release_resource);
433
434static bool pci_resize_is_memory_decoding_enabled(struct pci_dev *dev,
435 int resno)
436{
437 u16 cmd;
438
439 if (pci_resource_is_iov(resno))
440 return pci_iov_is_memory_decoding_enabled(dev);
441
442 pci_read_config_word(dev, PCI_COMMAND, val: &cmd);
443
444 return cmd & PCI_COMMAND_MEMORY;
445}
446
447static void pci_resize_resource_set_size(struct pci_dev *dev, int resno,
448 int size)
449{
450 resource_size_t res_size = pci_rebar_size_to_bytes(size);
451 struct resource *res = pci_resource_n(dev, resno);
452
453 if (!pci_resource_is_iov(resno)) {
454 resource_set_size(res, size: res_size);
455 } else {
456 resource_set_size(res, size: res_size * pci_sriov_get_totalvfs(dev));
457 pci_iov_resource_set_size(dev, resno, size: res_size);
458 }
459}
460
461int pci_resize_resource(struct pci_dev *dev, int resno, int size)
462{
463 struct resource *res = pci_resource_n(dev, resno);
464 struct pci_host_bridge *host;
465 int old, ret;
466 u32 sizes;
467
468 /* Check if we must preserve the firmware's resource assignment */
469 host = pci_find_host_bridge(bus: dev->bus);
470 if (host->preserve_config)
471 return -ENOTSUPP;
472
473 /* Make sure the resource isn't assigned before resizing it. */
474 if (!(res->flags & IORESOURCE_UNSET))
475 return -EBUSY;
476
477 if (pci_resize_is_memory_decoding_enabled(dev, resno))
478 return -EBUSY;
479
480 sizes = pci_rebar_get_possible_sizes(pdev: dev, bar: resno);
481 if (!sizes)
482 return -ENOTSUPP;
483
484 if (!(sizes & BIT(size)))
485 return -EINVAL;
486
487 old = pci_rebar_get_current_size(pdev: dev, bar: resno);
488 if (old < 0)
489 return old;
490
491 ret = pci_rebar_set_size(pdev: dev, bar: resno, size);
492 if (ret)
493 return ret;
494
495 pci_resize_resource_set_size(dev, resno, size);
496
497 /* Check if the new config works by trying to assign everything. */
498 if (dev->bus->self) {
499 ret = pbus_reassign_bridge_resources(bus: dev->bus, res);
500 if (ret)
501 goto error_resize;
502 }
503 return 0;
504
505error_resize:
506 pci_rebar_set_size(pdev: dev, bar: resno, size: old);
507 pci_resize_resource_set_size(dev, resno, size: old);
508 return ret;
509}
510EXPORT_SYMBOL(pci_resize_resource);
511
512int pci_enable_resources(struct pci_dev *dev, int mask)
513{
514 u16 cmd, old_cmd;
515 int i;
516 struct resource *r;
517 const char *r_name;
518
519 pci_read_config_word(dev, PCI_COMMAND, val: &cmd);
520 old_cmd = cmd;
521
522 pci_dev_for_each_resource(dev, r, i) {
523 if (!(mask & (1 << i)))
524 continue;
525
526 r_name = pci_resource_name(dev, i);
527
528 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
529 continue;
530 if (pci_resource_is_optional(dev, resno: i))
531 continue;
532
533 if (i < PCI_BRIDGE_RESOURCES) {
534 if (r->flags & IORESOURCE_UNSET) {
535 pci_err(dev, "%s %pR: not assigned; can't enable device\n",
536 r_name, r);
537 return -EINVAL;
538 }
539
540 if (!r->parent) {
541 pci_err(dev, "%s %pR: not claimed; can't enable device\n",
542 r_name, r);
543 return -EINVAL;
544 }
545 }
546
547 if (r->parent) {
548 if (r->flags & IORESOURCE_IO)
549 cmd |= PCI_COMMAND_IO;
550 if (r->flags & IORESOURCE_MEM)
551 cmd |= PCI_COMMAND_MEMORY;
552 }
553 }
554
555 if (cmd != old_cmd) {
556 pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
557 pci_write_config_word(dev, PCI_COMMAND, val: cmd);
558 }
559 return 0;
560}
561