1// SPDX-License-Identifier: GPL-1.0+
2/*
3 * OHCI HCD (Host Controller Driver) for USB.
4 *
5 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
6 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 *
8 * [ Initialisation is based on Linus' ]
9 * [ uhci code and gregs ohci fragments ]
10 * [ (C) Copyright 1999 Linus Torvalds ]
11 * [ (C) Copyright 1999 Gregory P. Smith]
12 *
13 * PCI Bus Glue
14 *
15 * This file is licenced under the GPL.
16 */
17
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/usb.h>
23#include <linux/usb/hcd.h>
24
25#include "ohci.h"
26#include "pci-quirks.h"
27
28#define DRIVER_DESC "OHCI PCI platform driver"
29
30static const char hcd_name[] = "ohci-pci";
31
32
33/*-------------------------------------------------------------------------*/
34
35static int broken_suspend(struct usb_hcd *hcd)
36{
37 device_init_wakeup(dev: &hcd->self.root_hub->dev, enable: 0);
38 return 0;
39}
40
41/* AMD 756, for most chips (early revs), corrupts register
42 * values on read ... so enable the vendor workaround.
43 */
44static int ohci_quirk_amd756(struct usb_hcd *hcd)
45{
46 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
47
48 ohci->flags = OHCI_QUIRK_AMD756;
49 ohci_dbg (ohci, "AMD756 erratum 4 workaround\n");
50
51 /* also erratum 10 (suspend/resume issues) */
52 return broken_suspend(hcd);
53}
54
55/* Apple's OHCI driver has a lot of bizarre workarounds
56 * for this chip. Evidently control and bulk lists
57 * can get confused. (B&W G3 models, and ...)
58 */
59static int ohci_quirk_opti(struct usb_hcd *hcd)
60{
61 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
62
63 ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n");
64
65 return 0;
66}
67
68/* Check for NSC87560. We have to look at the bridge (fn1) to
69 * identify the USB (fn2). This quirk might apply to more or
70 * even all NSC stuff.
71 */
72static int ohci_quirk_ns(struct usb_hcd *hcd)
73{
74 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
75 struct pci_dev *b;
76
77 b = pci_get_slot (bus: pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1));
78 if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO
79 && b->vendor == PCI_VENDOR_ID_NS) {
80 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
81
82 ohci->flags |= OHCI_QUIRK_SUPERIO;
83 ohci_dbg (ohci, "Using NSC SuperIO setup\n");
84 }
85 pci_dev_put(dev: b);
86
87 return 0;
88}
89
90/* Check for Compaq's ZFMicro chipset, which needs short
91 * delays before control or bulk queues get re-activated
92 * in finish_unlinks()
93 */
94static int ohci_quirk_zfmicro(struct usb_hcd *hcd)
95{
96 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
97
98 ohci->flags |= OHCI_QUIRK_ZFMICRO;
99 ohci_dbg(ohci, "enabled Compaq ZFMicro chipset quirks\n");
100
101 return 0;
102}
103
104/* Check for Toshiba SCC OHCI which has big endian registers
105 * and little endian in memory data structures
106 */
107static int ohci_quirk_toshiba_scc(struct usb_hcd *hcd)
108{
109 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
110
111 /* That chip is only present in the southbridge of some
112 * cell based platforms which are supposed to select
113 * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO. We verify here if
114 * that was the case though.
115 */
116#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
117 ohci->flags |= OHCI_QUIRK_BE_MMIO;
118 ohci_dbg (ohci, "enabled big endian Toshiba quirk\n");
119 return 0;
120#else
121 ohci_err (ohci, "unsupported big endian Toshiba quirk\n");
122 return -ENXIO;
123#endif
124}
125
126/* Check for NEC chip and apply quirk for allegedly lost interrupts.
127 */
128
129static void ohci_quirk_nec_worker(struct work_struct *work)
130{
131 struct ohci_hcd *ohci = container_of(work, struct ohci_hcd, nec_work);
132 int status;
133
134 status = ohci_restart(ohci);
135 if (status != 0)
136 ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
137 "ohci_restart", status);
138}
139
140static int ohci_quirk_nec(struct usb_hcd *hcd)
141{
142 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
143
144 ohci->flags |= OHCI_QUIRK_NEC;
145 INIT_WORK(&ohci->nec_work, ohci_quirk_nec_worker);
146 ohci_dbg (ohci, "enabled NEC chipset lost interrupt quirk\n");
147
148 return 0;
149}
150
151static int ohci_quirk_amd700(struct usb_hcd *hcd)
152{
153 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
154
155 if (usb_amd_quirk_pll_check())
156 ohci->flags |= OHCI_QUIRK_AMD_PLL;
157
158 /* SB800 needs pre-fetch fix */
159 if (usb_amd_prefetch_quirk()) {
160 ohci->flags |= OHCI_QUIRK_AMD_PREFETCH;
161 ohci_dbg(ohci, "enabled AMD prefetch quirk\n");
162 }
163
164 ohci->flags |= OHCI_QUIRK_GLOBAL_SUSPEND;
165 return 0;
166}
167
168static int ohci_quirk_loongson(struct usb_hcd *hcd)
169{
170 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
171
172 /*
173 * Loongson's LS7A OHCI controller (rev 0x02) has a
174 * flaw. MMIO register with offset 0x60/64 is treated
175 * as legacy PS2-compatible keyboard/mouse interface.
176 * Since OHCI only use 4KB BAR resource, LS7A OHCI's
177 * 32KB BAR is wrapped around (the 2nd 4KB BAR space
178 * is the same as the 1st 4KB internally). So add 4KB
179 * offset (0x1000) to the OHCI registers as a quirk.
180 */
181 if (pdev->revision == 0x2)
182 hcd->regs += SZ_4K; /* SZ_4K = 0x1000 */
183
184 return 0;
185}
186
187static int ohci_quirk_qemu(struct usb_hcd *hcd)
188{
189 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
190
191 ohci->flags |= OHCI_QUIRK_QEMU;
192 ohci_dbg(ohci, "enabled qemu quirk\n");
193 return 0;
194}
195
196/* List of quirks for OHCI */
197static const struct pci_device_id ohci_pci_quirks[] = {
198 {
199 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x740c),
200 .driver_data = (unsigned long)ohci_quirk_amd756,
201 },
202 {
203 PCI_DEVICE(PCI_VENDOR_ID_OPTI, 0xc861),
204 .driver_data = (unsigned long)ohci_quirk_opti,
205 },
206 {
207 PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_ANY_ID),
208 .driver_data = (unsigned long)ohci_quirk_ns,
209 },
210 {
211 PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xa0f8),
212 .driver_data = (unsigned long)ohci_quirk_zfmicro,
213 },
214 {
215 PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, 0x01b6),
216 .driver_data = (unsigned long)ohci_quirk_toshiba_scc,
217 },
218 {
219 PCI_DEVICE(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB),
220 .driver_data = (unsigned long)ohci_quirk_nec,
221 },
222 {
223 /* Toshiba portege 4000 */
224 .vendor = PCI_VENDOR_ID_AL,
225 .device = 0x5237,
226 .subvendor = PCI_VENDOR_ID_TOSHIBA,
227 .subdevice = 0x0004,
228 .driver_data = (unsigned long) broken_suspend,
229 },
230 {
231 PCI_DEVICE(PCI_VENDOR_ID_ITE, 0x8152),
232 .driver_data = (unsigned long) broken_suspend,
233 },
234 {
235 PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4397),
236 .driver_data = (unsigned long)ohci_quirk_amd700,
237 },
238 {
239 PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4398),
240 .driver_data = (unsigned long)ohci_quirk_amd700,
241 },
242 {
243 PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4399),
244 .driver_data = (unsigned long)ohci_quirk_amd700,
245 },
246 {
247 PCI_DEVICE(PCI_VENDOR_ID_LOONGSON, 0x7a24),
248 .driver_data = (unsigned long)ohci_quirk_loongson,
249 },
250 {
251 .vendor = PCI_VENDOR_ID_APPLE,
252 .device = 0x003f,
253 .subvendor = PCI_SUBVENDOR_ID_REDHAT_QUMRANET,
254 .subdevice = PCI_SUBDEVICE_ID_QEMU,
255 .driver_data = (unsigned long)ohci_quirk_qemu,
256 },
257
258 {},
259};
260
261static int ohci_pci_reset (struct usb_hcd *hcd)
262{
263 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
264 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
265 int ret = 0;
266
267 if (hcd->self.controller) {
268 const struct pci_device_id *quirk_id;
269
270 quirk_id = pci_match_id(ids: ohci_pci_quirks, dev: pdev);
271 if (quirk_id != NULL) {
272 int (*quirk)(struct usb_hcd *ohci);
273 quirk = (void *)quirk_id->driver_data;
274 ret = quirk(hcd);
275 }
276 }
277
278 if (ret == 0)
279 ret = ohci_setup(hcd);
280 /*
281 * After ohci setup RWC may not be set for add-in PCI cards.
282 * This transfers PCI PM wakeup capabilities.
283 */
284 if (device_can_wakeup(dev: &pdev->dev))
285 ohci->hc_control |= OHCI_CTRL_RWC;
286 return ret;
287}
288
289static struct hc_driver __read_mostly ohci_pci_hc_driver;
290
291static const struct ohci_driver_overrides pci_overrides __initconst = {
292 .product_desc = "OHCI PCI host controller",
293 .reset = ohci_pci_reset,
294};
295
296static const struct pci_device_id pci_ids[] = { {
297 /* handle any USB OHCI controller */
298 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
299 }, {
300 /* The device in the ConneXT I/O hub has no class reg */
301 PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_OHCI),
302 }, { /* end: all zeroes */ }
303};
304MODULE_DEVICE_TABLE (pci, pci_ids);
305
306static int ohci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
307{
308 return usb_hcd_pci_probe(dev, driver: &ohci_pci_hc_driver);
309}
310
311/* pci driver glue; this is a "new style" PCI driver module */
312static struct pci_driver ohci_pci_driver = {
313 .name = hcd_name,
314 .id_table = pci_ids,
315
316 .probe = ohci_pci_probe,
317 .remove = usb_hcd_pci_remove,
318 .shutdown = usb_hcd_pci_shutdown,
319
320#ifdef CONFIG_PM
321 .driver = {
322 .pm = &usb_hcd_pci_pm_ops
323 },
324#endif
325};
326
327#ifdef CONFIG_PM
328static int ohci_pci_resume(struct usb_hcd *hcd, pm_message_t msg)
329{
330 return ohci_resume(hcd, hibernated: msg.event == PM_EVENT_RESTORE);
331}
332#endif
333static int __init ohci_pci_init(void)
334{
335 if (usb_disabled())
336 return -ENODEV;
337
338 ohci_init_driver(drv: &ohci_pci_hc_driver, over: &pci_overrides);
339
340#ifdef CONFIG_PM
341 /* Entries for the PCI suspend/resume callbacks are special */
342 ohci_pci_hc_driver.pci_suspend = ohci_suspend;
343 ohci_pci_hc_driver.pci_resume = ohci_pci_resume;
344#endif
345
346 return pci_register_driver(&ohci_pci_driver);
347}
348module_init(ohci_pci_init);
349
350static void __exit ohci_pci_cleanup(void)
351{
352 pci_unregister_driver(dev: &ohci_pci_driver);
353}
354module_exit(ohci_pci_cleanup);
355
356MODULE_DESCRIPTION(DRIVER_DESC);
357MODULE_LICENSE("GPL");
358MODULE_SOFTDEP("pre: ehci_pci");
359