1/* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
2 * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
3 * derived from Data Sheet, Copyright Motorola 1984 (!).
4 * It was written to be part of the Linux operating system.
5 */
6/* permission is hereby granted to copy, modify and redistribute this code
7 * in terms of the GNU Library General Public License, Version 2 or later,
8 * at your option.
9 */
10
11#ifndef _MC146818RTC_H
12#define _MC146818RTC_H
13
14#include <asm/io.h>
15#include <linux/rtc.h> /* get the user-level API */
16#include <asm/mc146818rtc.h> /* register access macros */
17#include <linux/bcd.h>
18#include <linux/delay.h>
19#include <linux/pm-trace.h>
20
21#ifdef __KERNEL__
22#include <linux/spinlock.h> /* spinlock_t */
23extern spinlock_t rtc_lock; /* serialize CMOS RAM access */
24
25/* Some RTCs extend the mc146818 register set to support alarms of more
26 * than 24 hours in the future; or dates that include a century code.
27 * This platform_data structure can pass this information to the driver.
28 *
29 * Also, some platforms need suspend()/resume() hooks to kick in special
30 * handling of wake alarms, e.g. activating ACPI BIOS hooks or setting up
31 * a separate wakeup alarm used by some almost-clone chips.
32 */
33struct cmos_rtc_board_info {
34 void (*wake_on)(struct device *dev);
35 void (*wake_off)(struct device *dev);
36
37 u32 flags;
38#define CMOS_RTC_FLAGS_NOFREQ (1 << 0)
39 int address_space;
40
41 u8 rtc_day_alarm; /* zero, or register index */
42 u8 rtc_mon_alarm; /* zero, or register index */
43 u8 rtc_century; /* zero, or register index */
44};
45#endif
46
47/**********************************************************************
48 * register summary
49 **********************************************************************/
50#define RTC_SECONDS 0
51#define RTC_SECONDS_ALARM 1
52#define RTC_MINUTES 2
53#define RTC_MINUTES_ALARM 3
54#define RTC_HOURS 4
55#define RTC_HOURS_ALARM 5
56/* RTC_*_alarm is always true if 2 MSBs are set */
57# define RTC_ALARM_DONT_CARE 0xC0
58
59#define RTC_DAY_OF_WEEK 6
60#define RTC_DAY_OF_MONTH 7
61#define RTC_MONTH 8
62#define RTC_YEAR 9
63
64/* control registers - Moto names
65 */
66#define RTC_REG_A 10
67#define RTC_REG_B 11
68#define RTC_REG_C 12
69#define RTC_REG_D 13
70
71/**********************************************************************
72 * register details
73 **********************************************************************/
74#define RTC_FREQ_SELECT RTC_REG_A
75
76/* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus,
77 * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
78 * totalling to a max high interval of 2.228 ms.
79 */
80# define RTC_UIP 0x80
81# define RTC_DIV_CTL 0x70
82 /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
83# define RTC_REF_CLCK_4MHZ 0x00
84# define RTC_REF_CLCK_1MHZ 0x10
85# define RTC_REF_CLCK_32KHZ 0x20
86 /* 2 values for divider stage reset, others for "testing purposes only" */
87# define RTC_DIV_RESET1 0x60
88# define RTC_DIV_RESET2 0x70
89 /* In AMD BKDG bit 5 and 6 are reserved, bit 4 is for select dv0 bank */
90# define RTC_AMD_BANK_SELECT 0x10
91 /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
92# define RTC_RATE_SELECT 0x0F
93
94/**********************************************************************/
95#define RTC_CONTROL RTC_REG_B
96# define RTC_SET 0x80 /* disable updates for clock setting */
97# define RTC_PIE 0x40 /* periodic interrupt enable */
98# define RTC_AIE 0x20 /* alarm interrupt enable */
99# define RTC_UIE 0x10 /* update-finished interrupt enable */
100# define RTC_SQWE 0x08 /* enable square-wave output */
101# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
102# define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
103# define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
104
105/**********************************************************************/
106#define RTC_INTR_FLAGS RTC_REG_C
107/* caution - cleared by read */
108# define RTC_IRQF 0x80 /* any of the following 3 is active */
109# define RTC_PF 0x40
110# define RTC_AF 0x20
111# define RTC_UF 0x10
112
113/**********************************************************************/
114#define RTC_VALID RTC_REG_D
115# define RTC_VRT 0x80 /* valid RAM and time */
116/**********************************************************************/
117
118#ifndef ARCH_RTC_LOCATION /* Override by <asm/mc146818rtc.h>? */
119
120#define RTC_IO_EXTENT 0x8
121#define RTC_IO_EXTENT_USED 0x2
122#define RTC_IOMAPPED 1 /* Default to I/O mapping. */
123
124#else
125#define RTC_IO_EXTENT_USED RTC_IO_EXTENT
126#endif /* ARCH_RTC_LOCATION */
127
128bool mc146818_does_rtc_work(void);
129int mc146818_get_time(struct rtc_time *time, int timeout);
130int mc146818_set_time(struct rtc_time *time);
131
132bool mc146818_avoid_UIP(void (*callback)(unsigned char seconds, void *param),
133 int timeout,
134 void *param);
135
136#endif /* _MC146818RTC_H */
137