1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright 2020,2022 NXP
4 */
5
6#ifndef __PHY_LVDS_H_
7#define __PHY_LVDS_H_
8
9/**
10 * struct phy_configure_opts_lvds - LVDS configuration set
11 * @bits_per_lane_and_dclk_cycle: Number of bits per lane per differential
12 * clock cycle.
13 * @differential_clk_rate: Clock rate, in Hertz, of the LVDS
14 * differential clock.
15 * @lanes: Number of active, consecutive,
16 * data lanes, starting from lane 0,
17 * used for the transmissions.
18 * @is_slave: Boolean, true if the phy is a slave
19 * which works together with a master
20 * phy to support dual link transmission,
21 * otherwise a regular phy or a master phy.
22 *
23 * This structure is used to represent the configuration state of a LVDS phy.
24 */
25struct phy_configure_opts_lvds {
26 unsigned int bits_per_lane_and_dclk_cycle;
27 unsigned long differential_clk_rate;
28 unsigned int lanes;
29 bool is_slave;
30};
31
32#endif /* __PHY_LVDS_H_ */
33