1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * HD-audio stream operations
4 */
5
6#include <linux/kernel.h>
7#include <linux/delay.h>
8#include <linux/export.h>
9#include <linux/clocksource.h>
10#include <sound/compress_driver.h>
11#include <sound/core.h>
12#include <sound/pcm.h>
13#include <sound/hdaudio.h>
14#include <sound/hda_register.h>
15#include "trace.h"
16
17/*
18 * the hdac_stream library is intended to be used with the following
19 * transitions. The states are not formally defined in the code but loosely
20 * inspired by boolean variables. Note that the 'prepared' field is not used
21 * in this library but by the callers during the hw_params/prepare transitions
22 *
23 * |
24 * stream_init() |
25 * v
26 * +--+-------+
27 * | unused |
28 * +--+----+--+
29 * | ^
30 * stream_assign() | | stream_release()
31 * v |
32 * +--+----+--+
33 * | opened |
34 * +--+----+--+
35 * | ^
36 * stream_reset() | |
37 * stream_setup() | | stream_cleanup()
38 * v |
39 * +--+----+--+
40 * | prepared |
41 * +--+----+--+
42 * | ^
43 * stream_start() | | stream_stop()
44 * v |
45 * +--+----+--+
46 * | running |
47 * +----------+
48 */
49
50/**
51 * snd_hdac_get_stream_stripe_ctl - get stripe control value
52 * @bus: HD-audio core bus
53 * @substream: PCM substream
54 */
55int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
56 struct snd_pcm_substream *substream)
57{
58 struct snd_pcm_runtime *runtime = substream->runtime;
59 unsigned int channels = runtime->channels,
60 rate = runtime->rate,
61 bits_per_sample = runtime->sample_bits,
62 max_sdo_lines, value, sdo_line;
63
64 /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
65 max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
66
67 /* following is from HD audio spec */
68 for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
69 if (rate > 48000)
70 value = (channels * bits_per_sample *
71 (rate / 48000)) / sdo_line;
72 else
73 value = (channels * bits_per_sample) / sdo_line;
74
75 if (value >= bus->sdo_limit)
76 break;
77 }
78
79 /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
80 return sdo_line >> 1;
81}
82EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
83
84/**
85 * snd_hdac_stream_init - initialize each stream (aka device)
86 * @bus: HD-audio core bus
87 * @azx_dev: HD-audio core stream object to initialize
88 * @idx: stream index number
89 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
90 * @tag: the tag id to assign
91 *
92 * Assign the starting bdl address to each stream (device) and initialize.
93 */
94void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
95 int idx, int direction, int tag)
96{
97 azx_dev->bus = bus;
98 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
99 azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
100 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
101 azx_dev->sd_int_sta_mask = 1 << idx;
102 azx_dev->index = idx;
103 azx_dev->direction = direction;
104 azx_dev->stream_tag = tag;
105 snd_hdac_dsp_lock_init(azx_dev);
106 list_add_tail(new: &azx_dev->list, head: &bus->stream_list);
107
108 if (bus->spbcap) {
109 azx_dev->spib_addr = bus->spbcap + AZX_SPB_BASE +
110 AZX_SPB_INTERVAL * idx +
111 AZX_SPB_SPIB;
112
113 azx_dev->fifo_addr = bus->spbcap + AZX_SPB_BASE +
114 AZX_SPB_INTERVAL * idx +
115 AZX_SPB_MAXFIFO;
116 }
117
118 if (bus->drsmcap)
119 azx_dev->dpibr_addr = bus->drsmcap + AZX_DRSM_BASE +
120 AZX_DRSM_INTERVAL * idx;
121}
122EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
123
124/**
125 * snd_hdac_stream_start - start a stream
126 * @azx_dev: HD-audio core stream to start
127 *
128 * Start a stream, set start_wallclk and set the running flag.
129 */
130void snd_hdac_stream_start(struct hdac_stream *azx_dev)
131{
132 struct hdac_bus *bus = azx_dev->bus;
133 int stripe_ctl;
134
135 trace_snd_hdac_stream_start(bus, azx_dev);
136
137 azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
138
139 /* enable SIE */
140 snd_hdac_chip_updatel(bus, INTCTL,
141 1 << azx_dev->index,
142 1 << azx_dev->index);
143 /* set stripe control */
144 if (azx_dev->stripe) {
145 if (azx_dev->substream)
146 stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
147 else
148 stripe_ctl = 0;
149 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
150 stripe_ctl);
151 }
152 /* set DMA start and interrupt mask */
153 if (bus->access_sdnctl_in_dword)
154 snd_hdac_stream_updatel(azx_dev, SD_CTL,
155 0, SD_CTL_DMA_START | SD_INT_MASK);
156 else
157 snd_hdac_stream_updateb(azx_dev, SD_CTL,
158 0, SD_CTL_DMA_START | SD_INT_MASK);
159 azx_dev->running = true;
160}
161EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
162
163/**
164 * snd_hdac_stream_clear - helper to clear stream registers and stop DMA transfers
165 * @azx_dev: HD-audio core stream to stop
166 */
167static void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
168{
169 snd_hdac_stream_updateb(azx_dev, SD_CTL,
170 SD_CTL_DMA_START | SD_INT_MASK, 0);
171 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
172 if (azx_dev->stripe)
173 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
174 azx_dev->running = false;
175}
176
177/**
178 * snd_hdac_stream_stop - stop a stream
179 * @azx_dev: HD-audio core stream to stop
180 *
181 * Stop a stream DMA and disable stream interrupt
182 */
183void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
184{
185 trace_snd_hdac_stream_stop(bus: azx_dev->bus, azx_dev);
186
187 snd_hdac_stream_clear(azx_dev);
188 /* disable SIE */
189 snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
190}
191EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
192
193/**
194 * snd_hdac_stop_streams - stop all streams
195 * @bus: HD-audio core bus
196 */
197void snd_hdac_stop_streams(struct hdac_bus *bus)
198{
199 struct hdac_stream *stream;
200
201 list_for_each_entry(stream, &bus->stream_list, list)
202 snd_hdac_stream_stop(stream);
203}
204EXPORT_SYMBOL_GPL(snd_hdac_stop_streams);
205
206/**
207 * snd_hdac_stop_streams_and_chip - stop all streams and chip if running
208 * @bus: HD-audio core bus
209 */
210void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus)
211{
212
213 if (bus->chip_init) {
214 snd_hdac_stop_streams(bus);
215 snd_hdac_bus_stop_chip(bus);
216 }
217}
218EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_chip);
219
220/**
221 * snd_hdac_stream_reset - reset a stream
222 * @azx_dev: HD-audio core stream to reset
223 */
224void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
225{
226 unsigned char val;
227 int dma_run_state;
228
229 snd_hdac_stream_clear(azx_dev);
230
231 dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START;
232
233 snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
234
235 /* wait for hardware to report that the stream entered reset */
236 snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, (val & SD_CTL_STREAM_RESET), 3, 300);
237
238 if (azx_dev->bus->dma_stop_delay && dma_run_state)
239 udelay(usec: azx_dev->bus->dma_stop_delay);
240
241 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_CTL_STREAM_RESET, 0);
242
243 /* wait for hardware to report that the stream is out of reset */
244 snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, !(val & SD_CTL_STREAM_RESET), 3, 300);
245
246 /* reset first position - may not be synced with hw at this time */
247 if (azx_dev->posbuf)
248 *azx_dev->posbuf = 0;
249}
250EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
251
252/**
253 * snd_hdac_stream_setup - set up the SD for streaming
254 * @azx_dev: HD-audio core stream to set up
255 * @code_loading: Whether the stream is for PCM or code-loading.
256 */
257int snd_hdac_stream_setup(struct hdac_stream *azx_dev, bool code_loading)
258{
259 struct hdac_bus *bus = azx_dev->bus;
260 struct snd_pcm_runtime *runtime;
261 unsigned int val;
262 u16 reg;
263 int ret;
264
265 if (azx_dev->substream)
266 runtime = azx_dev->substream->runtime;
267 else
268 runtime = NULL;
269 /* make sure the run bit is zero for SD */
270 snd_hdac_stream_clear(azx_dev);
271 /* program the stream_tag */
272 val = snd_hdac_stream_readl(azx_dev, SD_CTL);
273 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
274 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
275 if (!bus->snoop)
276 val |= SD_CTL_TRAFFIC_PRIO;
277 snd_hdac_stream_writel(azx_dev, SD_CTL, val);
278
279 /* program the length of samples in cyclic buffer */
280 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
281
282 /* program the stream format */
283 /* this value needs to be the same as the one programmed */
284 snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
285
286 /* program the stream LVI (last valid index) of the BDL */
287 snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
288
289 /* program the BDL address */
290 /* lower BDL address */
291 snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
292 /* upper BDL address */
293 snd_hdac_stream_writel(azx_dev, SD_BDLPU,
294 upper_32_bits(azx_dev->bdl.addr));
295
296 /* enable the position buffer */
297 if (bus->use_posbuf && bus->posbuf.addr) {
298 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
299 snd_hdac_chip_writel(bus, DPLBASE,
300 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
301 }
302
303 /* set the interrupt enable bits in the descriptor control register */
304 snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
305
306 if (!code_loading) {
307 /* Once SDxFMT is set, the controller programs SDxFIFOS to non-zero value. */
308 ret = snd_hdac_stream_readw_poll(azx_dev, SD_FIFOSIZE, reg,
309 reg & AZX_SD_FIFOSIZE_MASK, 3, 300);
310 if (ret)
311 dev_dbg(bus->dev, "polling SD_FIFOSIZE 0x%04x failed: %d\n",
312 AZX_REG_SD_FIFOSIZE, ret);
313 azx_dev->fifo_size = reg;
314 }
315
316 /* when LPIB delay correction gives a small negative value,
317 * we ignore it; currently set the threshold statically to
318 * 64 frames
319 */
320 if (runtime && runtime->period_size > 64)
321 azx_dev->delay_negative_threshold =
322 -frames_to_bytes(runtime, size: 64);
323 else
324 azx_dev->delay_negative_threshold = 0;
325
326 /* wallclk has 24Mhz clock source */
327 if (runtime)
328 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
329 runtime->rate) * 1000);
330
331 return 0;
332}
333EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
334
335/**
336 * snd_hdac_stream_cleanup - cleanup a stream
337 * @azx_dev: HD-audio core stream to clean up
338 */
339void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
340{
341 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
342 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
343 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
344 azx_dev->bufsize = 0;
345 azx_dev->period_bytes = 0;
346 azx_dev->format_val = 0;
347}
348EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
349
350/**
351 * snd_hdac_stream_assign - assign a stream for the PCM
352 * @bus: HD-audio core bus
353 * @substream: PCM substream to assign
354 *
355 * Look for an unused stream for the given PCM substream, assign it
356 * and return the stream object. If no stream is free, returns NULL.
357 * The function tries to keep using the same stream object when it's used
358 * beforehand. Also, when bus->reverse_assign flag is set, the last free
359 * or matching entry is returned. This is needed for some strange codecs.
360 */
361struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
362 struct snd_pcm_substream *substream)
363{
364 struct hdac_stream *azx_dev;
365 struct hdac_stream *res = NULL;
366
367 /* make a non-zero unique key for the substream */
368 int key = (substream->number << 2) | (substream->stream + 1);
369
370 if (substream->pcm)
371 key |= (substream->pcm->device << 16);
372
373 guard(spinlock_irq)(l: &bus->reg_lock);
374 list_for_each_entry(azx_dev, &bus->stream_list, list) {
375 if (azx_dev->direction != substream->stream)
376 continue;
377 if (azx_dev->opened)
378 continue;
379 if (azx_dev->assigned_key == key) {
380 res = azx_dev;
381 break;
382 }
383 if (!res || bus->reverse_assign)
384 res = azx_dev;
385 }
386 if (res) {
387 res->opened = 1;
388 res->running = 0;
389 res->assigned_key = key;
390 res->substream = substream;
391 }
392 return res;
393}
394EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
395
396/**
397 * snd_hdac_stream_release_locked - release the assigned stream
398 * @azx_dev: HD-audio core stream to release
399 *
400 * Release the stream that has been assigned by snd_hdac_stream_assign().
401 * The bus->reg_lock needs to be taken at a higher level
402 */
403void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev)
404{
405 azx_dev->opened = 0;
406 azx_dev->running = 0;
407 azx_dev->substream = NULL;
408}
409EXPORT_SYMBOL_GPL(snd_hdac_stream_release_locked);
410
411/**
412 * snd_hdac_stream_release - release the assigned stream
413 * @azx_dev: HD-audio core stream to release
414 *
415 * Release the stream that has been assigned by snd_hdac_stream_assign().
416 */
417void snd_hdac_stream_release(struct hdac_stream *azx_dev)
418{
419 struct hdac_bus *bus = azx_dev->bus;
420
421 guard(spinlock_irq)(l: &bus->reg_lock);
422 snd_hdac_stream_release_locked(azx_dev);
423}
424EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
425
426/**
427 * snd_hdac_get_stream - return hdac_stream based on stream_tag and
428 * direction
429 *
430 * @bus: HD-audio core bus
431 * @dir: direction for the stream to be found
432 * @stream_tag: stream tag for stream to be found
433 */
434struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
435 int dir, int stream_tag)
436{
437 struct hdac_stream *s;
438
439 list_for_each_entry(s, &bus->stream_list, list) {
440 if (s->direction == dir && s->stream_tag == stream_tag)
441 return s;
442 }
443
444 return NULL;
445}
446EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
447
448/*
449 * set up a BDL entry
450 */
451static int setup_bdle(struct hdac_bus *bus,
452 struct snd_dma_buffer *dmab,
453 struct hdac_stream *azx_dev, __le32 **bdlp,
454 int ofs, int size, int with_ioc)
455{
456 __le32 *bdl = *bdlp;
457
458 while (size > 0) {
459 dma_addr_t addr;
460 int chunk;
461
462 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
463 return -EINVAL;
464
465 addr = snd_sgbuf_get_addr(dmab, offset: ofs);
466 /* program the address field of the BDL entry */
467 bdl[0] = cpu_to_le32((u32)addr);
468 bdl[1] = cpu_to_le32(upper_32_bits(addr));
469 /* program the size field of the BDL entry */
470 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
471 /* one BDLE cannot cross 4K boundary on CTHDA chips */
472 if (bus->align_bdle_4k) {
473 u32 remain = 0x1000 - (ofs & 0xfff);
474
475 if (chunk > remain)
476 chunk = remain;
477 }
478 bdl[2] = cpu_to_le32(chunk);
479 /* program the IOC to enable interrupt
480 * only when the whole fragment is processed
481 */
482 size -= chunk;
483 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
484 bdl += 4;
485 azx_dev->frags++;
486 ofs += chunk;
487 }
488 *bdlp = bdl;
489 return ofs;
490}
491
492/**
493 * snd_hdac_stream_setup_bdle - set up BDL entries
494 * @azx_dev: HD-audio core stream to set up
495 * @dmab: allocated DMA buffer
496 * @runtime: substream runtime, optional
497 *
498 * Set up the buffer descriptor table of the given stream based on the
499 * period and buffer sizes of the assigned PCM substream.
500 */
501static int snd_hdac_stream_setup_bdle(struct hdac_stream *azx_dev, struct snd_dma_buffer *dmab,
502 struct snd_pcm_runtime *runtime)
503{
504 struct hdac_bus *bus = azx_dev->bus;
505 int i, ofs, periods, period_bytes;
506 int pos_adj, pos_align;
507 __le32 *bdl;
508
509 /* reset BDL address */
510 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
511 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
512
513 period_bytes = azx_dev->period_bytes;
514 periods = azx_dev->bufsize / period_bytes;
515
516 /* program the initial BDL entries */
517 bdl = (__le32 *)azx_dev->bdl.area;
518 ofs = 0;
519 azx_dev->frags = 0;
520
521 pos_adj = bus->bdl_pos_adj;
522 if (runtime && !azx_dev->no_period_wakeup && pos_adj > 0) {
523 pos_align = pos_adj;
524 pos_adj = DIV_ROUND_UP(pos_adj * runtime->rate, 48000);
525 if (!pos_adj)
526 pos_adj = pos_align;
527 else
528 pos_adj = roundup(pos_adj, pos_align);
529 pos_adj = frames_to_bytes(runtime, size: pos_adj);
530 if (pos_adj >= period_bytes) {
531 dev_warn(bus->dev, "Too big adjustment %d\n",
532 pos_adj);
533 pos_adj = 0;
534 } else {
535 ofs = setup_bdle(bus, dmab, azx_dev,
536 bdlp: &bdl, ofs, size: pos_adj, with_ioc: true);
537 if (ofs < 0)
538 goto error;
539 }
540 } else
541 pos_adj = 0;
542
543 for (i = 0; i < periods; i++) {
544 if (i == periods - 1 && pos_adj)
545 ofs = setup_bdle(bus, dmab, azx_dev,
546 bdlp: &bdl, ofs, size: period_bytes - pos_adj, with_ioc: 0);
547 else
548 ofs = setup_bdle(bus, dmab, azx_dev,
549 bdlp: &bdl, ofs, size: period_bytes,
550 with_ioc: !azx_dev->no_period_wakeup);
551 if (ofs < 0)
552 goto error;
553 }
554 return 0;
555
556 error:
557 dev_dbg(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
558 azx_dev->bufsize, period_bytes);
559 return -EINVAL;
560}
561
562/**
563 * snd_hdac_stream_setup_periods - set up BDL entries
564 * @azx_dev: HD-audio core stream to set up
565 *
566 * Set up the buffer descriptor table of the given stream based on the
567 * period and buffer sizes of the assigned PCM substream.
568 */
569int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
570{
571 struct snd_pcm_substream *substream = azx_dev->substream;
572 struct snd_compr_stream *cstream = azx_dev->cstream;
573 struct snd_pcm_runtime *runtime = NULL;
574 struct snd_dma_buffer *dmab;
575
576 if (substream) {
577 runtime = substream->runtime;
578 dmab = snd_pcm_get_dma_buf(substream);
579 } else if (cstream) {
580 dmab = snd_pcm_get_dma_buf(cstream);
581 } else {
582 WARN(1, "No substream or cstream assigned\n");
583 return -EINVAL;
584 }
585
586 return snd_hdac_stream_setup_bdle(azx_dev, dmab, runtime);
587}
588EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
589
590/**
591 * snd_hdac_stream_set_params - set stream parameters
592 * @azx_dev: HD-audio core stream for which parameters are to be set
593 * @format_val: format value parameter
594 *
595 * Setup the HD-audio core stream parameters from substream of the stream
596 * and passed format value
597 */
598int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
599 unsigned int format_val)
600{
601 struct snd_pcm_substream *substream = azx_dev->substream;
602 struct snd_compr_stream *cstream = azx_dev->cstream;
603 unsigned int bufsize, period_bytes;
604 unsigned int no_period_wakeup;
605 int err;
606
607 if (substream) {
608 bufsize = snd_pcm_lib_buffer_bytes(substream);
609 period_bytes = snd_pcm_lib_period_bytes(substream);
610 no_period_wakeup = substream->runtime->no_period_wakeup;
611 } else if (cstream) {
612 bufsize = cstream->runtime->buffer_size;
613 period_bytes = cstream->runtime->fragment_size;
614 no_period_wakeup = 0;
615 } else {
616 return -EINVAL;
617 }
618
619 if (bufsize != azx_dev->bufsize ||
620 period_bytes != azx_dev->period_bytes ||
621 format_val != azx_dev->format_val ||
622 no_period_wakeup != azx_dev->no_period_wakeup) {
623 azx_dev->bufsize = bufsize;
624 azx_dev->period_bytes = period_bytes;
625 azx_dev->format_val = format_val;
626 azx_dev->no_period_wakeup = no_period_wakeup;
627 err = snd_hdac_stream_setup_periods(azx_dev);
628 if (err < 0)
629 return err;
630 }
631 return 0;
632}
633EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
634
635static u64 azx_cc_read(struct cyclecounter *cc)
636{
637 struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
638
639 return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
640}
641
642static void azx_timecounter_init(struct hdac_stream *azx_dev,
643 bool force, u64 last)
644{
645 struct timecounter *tc = &azx_dev->tc;
646 struct cyclecounter *cc = &azx_dev->cc;
647 u64 nsec;
648
649 cc->read = azx_cc_read;
650 cc->mask = CLOCKSOURCE_MASK(32);
651
652 /*
653 * Calculate the optimal mult/shift values. The counter wraps
654 * around after ~178.9 seconds.
655 */
656 clocks_calc_mult_shift(mult: &cc->mult, shift: &cc->shift, from: 24000000,
657 NSEC_PER_SEC, minsec: 178);
658
659 nsec = 0; /* audio time is elapsed time since trigger */
660 timecounter_init(tc, cc, start_tstamp: nsec);
661 if (force) {
662 /*
663 * force timecounter to use predefined value,
664 * used for synchronized starts
665 */
666 tc->cycle_last = last;
667 }
668}
669
670/**
671 * snd_hdac_stream_timecounter_init - initialize time counter
672 * @azx_dev: HD-audio core stream (master stream)
673 * @streams: bit flags of streams to set up
674 * @start: true for PCM trigger start, false for other cases
675 *
676 * Initializes the time counter of streams marked by the bit flags (each
677 * bit corresponds to the stream index).
678 * The trigger timestamp of PCM substream assigned to the given stream is
679 * updated accordingly, too.
680 */
681void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
682 unsigned int streams, bool start)
683{
684 struct hdac_bus *bus = azx_dev->bus;
685 struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
686 struct hdac_stream *s;
687 bool inited = false;
688 u64 cycle_last = 0;
689
690 if (!start)
691 goto skip;
692
693 list_for_each_entry(s, &bus->stream_list, list) {
694 if ((streams & (1 << s->index))) {
695 azx_timecounter_init(azx_dev: s, force: inited, last: cycle_last);
696 if (!inited) {
697 inited = true;
698 cycle_last = s->tc.cycle_last;
699 }
700 }
701 }
702
703skip:
704 snd_pcm_gettime(runtime, tv: &runtime->trigger_tstamp);
705 runtime->trigger_tstamp_latched = true;
706}
707EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
708
709/**
710 * snd_hdac_stream_sync_trigger - turn on/off stream sync register
711 * @azx_dev: HD-audio core stream (master stream)
712 * @set: true = set, false = clear
713 * @streams: bit flags of streams to sync
714 * @reg: the stream sync register address
715 */
716void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
717 unsigned int streams, unsigned int reg)
718{
719 struct hdac_bus *bus = azx_dev->bus;
720 unsigned int val;
721
722 if (!reg)
723 reg = AZX_REG_SSYNC;
724 val = _snd_hdac_chip_readl(bus, reg);
725 if (set)
726 val |= streams;
727 else
728 val &= ~streams;
729 _snd_hdac_chip_writel(bus, reg, val);
730}
731EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
732
733/**
734 * snd_hdac_stream_sync - sync with start/stop trigger operation
735 * @azx_dev: HD-audio core stream (master stream)
736 * @start: true = start, false = stop
737 * @streams: bit flags of streams to sync
738 *
739 * For @start = true, wait until all FIFOs get ready.
740 * For @start = false, wait until all RUN bits are cleared.
741 */
742void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
743 unsigned int streams)
744{
745 struct hdac_bus *bus = azx_dev->bus;
746 int nwait, timeout;
747 struct hdac_stream *s;
748
749 for (timeout = 5000; timeout; timeout--) {
750 nwait = 0;
751 list_for_each_entry(s, &bus->stream_list, list) {
752 if (!(streams & (1 << s->index)))
753 continue;
754
755 if (start) {
756 /* check FIFO gets ready */
757 if (!(snd_hdac_stream_readb(s, SD_STS) &
758 SD_STS_FIFO_READY))
759 nwait++;
760 } else {
761 /* check RUN bit is cleared */
762 if (snd_hdac_stream_readb(s, SD_CTL) &
763 SD_CTL_DMA_START) {
764 nwait++;
765 /*
766 * Perform stream reset if DMA RUN
767 * bit not cleared within given timeout
768 */
769 if (timeout == 1)
770 snd_hdac_stream_reset(s);
771 }
772 }
773 }
774 if (!nwait)
775 break;
776 cpu_relax();
777 }
778}
779EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
780
781/**
782 * snd_hdac_stream_spbcap_enable - enable SPIB for a stream
783 * @bus: HD-audio core bus
784 * @enable: flag to enable/disable SPIB
785 * @index: stream index for which SPIB need to be enabled
786 */
787void snd_hdac_stream_spbcap_enable(struct hdac_bus *bus,
788 bool enable, int index)
789{
790 u32 mask = 0;
791
792 if (!bus->spbcap) {
793 dev_err(bus->dev, "Address of SPB capability is NULL\n");
794 return;
795 }
796
797 mask |= (1 << index);
798
799 if (enable)
800 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, mask);
801 else
802 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, 0);
803}
804EXPORT_SYMBOL_GPL(snd_hdac_stream_spbcap_enable);
805
806/**
807 * snd_hdac_stream_set_spib - sets the spib value of a stream
808 * @bus: HD-audio core bus
809 * @azx_dev: hdac_stream
810 * @value: spib value to set
811 */
812int snd_hdac_stream_set_spib(struct hdac_bus *bus,
813 struct hdac_stream *azx_dev, u32 value)
814{
815 if (!bus->spbcap) {
816 dev_err(bus->dev, "Address of SPB capability is NULL\n");
817 return -EINVAL;
818 }
819
820 writel(val: value, addr: azx_dev->spib_addr);
821
822 return 0;
823}
824EXPORT_SYMBOL_GPL(snd_hdac_stream_set_spib);
825
826/**
827 * snd_hdac_stream_drsm_enable - enable DMA resume for a stream
828 * @bus: HD-audio core bus
829 * @enable: flag to enable/disable DRSM
830 * @index: stream index for which DRSM need to be enabled
831 */
832void snd_hdac_stream_drsm_enable(struct hdac_bus *bus,
833 bool enable, int index)
834{
835 u32 mask = 0;
836
837 if (!bus->drsmcap) {
838 dev_err(bus->dev, "Address of DRSM capability is NULL\n");
839 return;
840 }
841
842 mask |= (1 << index);
843
844 if (enable)
845 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, mask);
846 else
847 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, 0);
848}
849EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable);
850
851/*
852 * snd_hdac_stream_wait_drsm - wait for HW to clear RSM for a stream
853 * @azx_dev: HD-audio core stream to await RSM for
854 *
855 * Returns 0 on success and -ETIMEDOUT upon a timeout.
856 */
857int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev)
858{
859 struct hdac_bus *bus = azx_dev->bus;
860 u32 mask, reg;
861 int ret;
862
863 mask = 1 << azx_dev->index;
864
865 ret = read_poll_timeout(snd_hdac_reg_readl, reg, !(reg & mask), 250, 2000, false, bus,
866 bus->drsmcap + AZX_REG_DRSM_CTL);
867 if (ret)
868 dev_dbg(bus->dev, "polling RSM 0x%08x failed: %d\n", mask, ret);
869 return ret;
870}
871EXPORT_SYMBOL_GPL(snd_hdac_stream_wait_drsm);
872
873/**
874 * snd_hdac_stream_set_dpibr - sets the dpibr value of a stream
875 * @bus: HD-audio core bus
876 * @azx_dev: hdac_stream
877 * @value: dpib value to set
878 */
879int snd_hdac_stream_set_dpibr(struct hdac_bus *bus,
880 struct hdac_stream *azx_dev, u32 value)
881{
882 if (!bus->drsmcap) {
883 dev_err(bus->dev, "Address of DRSM capability is NULL\n");
884 return -EINVAL;
885 }
886
887 writel(val: value, addr: azx_dev->dpibr_addr);
888
889 return 0;
890}
891EXPORT_SYMBOL_GPL(snd_hdac_stream_set_dpibr);
892
893/**
894 * snd_hdac_stream_set_lpib - sets the lpib value of a stream
895 * @azx_dev: hdac_stream
896 * @value: lpib value to set
897 */
898int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value)
899{
900 snd_hdac_stream_writel(azx_dev, SD_LPIB, value);
901
902 return 0;
903}
904EXPORT_SYMBOL_GPL(snd_hdac_stream_set_lpib);
905
906#ifdef CONFIG_SND_HDA_DSP_LOADER
907/**
908 * snd_hdac_dsp_prepare - prepare for DSP loading
909 * @azx_dev: HD-audio core stream used for DSP loading
910 * @format: HD-audio stream format
911 * @byte_size: data chunk byte size
912 * @bufp: allocated buffer
913 *
914 * Allocate the buffer for the given size and set up the given stream for
915 * DSP loading. Returns the stream tag (>= 0), or a negative error code.
916 */
917int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
918 unsigned int byte_size, struct snd_dma_buffer *bufp)
919{
920 struct hdac_bus *bus = azx_dev->bus;
921 int err;
922
923 guard(snd_hdac_dsp_lock)(azx_dev);
924 scoped_guard(spinlock_irq, &bus->reg_lock) {
925 if (azx_dev->running || azx_dev->locked)
926 return -EBUSY;
927 azx_dev->locked = true;
928 }
929
930 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
931 byte_size, bufp);
932 if (err < 0)
933 goto err_alloc;
934
935 azx_dev->substream = NULL;
936 azx_dev->bufsize = byte_size;
937 /* It is recommended to transfer the firmware in two or more chunks. */
938 azx_dev->period_bytes = byte_size / 2;
939 azx_dev->format_val = format;
940 azx_dev->no_period_wakeup = 1;
941
942 snd_hdac_stream_reset(azx_dev);
943
944 err = snd_hdac_stream_setup_bdle(azx_dev, bufp, NULL);
945 if (err < 0)
946 goto error;
947
948 snd_hdac_stream_setup(azx_dev, true);
949 return azx_dev->stream_tag;
950
951 error:
952 snd_dma_free_pages(bufp);
953 err_alloc:
954 scoped_guard(spinlock_irq, &bus->reg_lock) {
955 azx_dev->locked = false;
956 }
957 return err;
958}
959EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
960
961/**
962 * snd_hdac_dsp_trigger - start / stop DSP loading
963 * @azx_dev: HD-audio core stream used for DSP loading
964 * @start: trigger start or stop
965 */
966void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
967{
968 if (start)
969 snd_hdac_stream_start(azx_dev);
970 else
971 snd_hdac_stream_stop(azx_dev);
972}
973EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
974
975/**
976 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
977 * @azx_dev: HD-audio core stream used for DSP loading
978 * @dmab: buffer used by DSP loading
979 */
980void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
981 struct snd_dma_buffer *dmab)
982{
983 struct hdac_bus *bus = azx_dev->bus;
984
985 if (!dmab->area || !azx_dev->locked)
986 return;
987
988 guard(snd_hdac_dsp_lock)(azx_dev);
989 /* reset BDL address */
990 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
991 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
992 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
993 azx_dev->bufsize = 0;
994 azx_dev->period_bytes = 0;
995 azx_dev->format_val = 0;
996
997 snd_dma_free_pages(dmab);
998 dmab->area = NULL;
999
1000 guard(spinlock_irq)(&bus->reg_lock);
1001 azx_dev->locked = false;
1002}
1003EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
1004#endif /* CONFIG_SND_HDA_DSP_LOADER */
1005