1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Common interrupt code for 32 and 64 bit
4 */
5#include <linux/cpu.h>
6#include <linux/interrupt.h>
7#include <linux/kernel_stat.h>
8#include <linux/of.h>
9#include <linux/seq_file.h>
10#include <linux/smp.h>
11#include <linux/ftrace.h>
12#include <linux/delay.h>
13#include <linux/export.h>
14#include <linux/irq.h>
15
16#include <asm/irq_stack.h>
17#include <asm/apic.h>
18#include <asm/io_apic.h>
19#include <asm/irq.h>
20#include <asm/mce.h>
21#include <asm/hw_irq.h>
22#include <asm/desc.h>
23#include <asm/traps.h>
24#include <asm/thermal.h>
25#include <asm/posted_intr.h>
26#include <asm/irq_remapping.h>
27
28#if defined(CONFIG_X86_LOCAL_APIC) || defined(CONFIG_X86_THERMAL_VECTOR)
29#define CREATE_TRACE_POINTS
30#include <asm/trace/irq_vectors.h>
31#endif
32
33DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
34EXPORT_PER_CPU_SYMBOL(irq_stat);
35
36DEFINE_PER_CPU_CACHE_HOT(u16, __softirq_pending);
37EXPORT_PER_CPU_SYMBOL(__softirq_pending);
38
39DEFINE_PER_CPU_CACHE_HOT(struct irq_stack *, hardirq_stack_ptr);
40
41atomic_t irq_err_count;
42
43/*
44 * 'what should we do if we get a hw irq event on an illegal vector'.
45 * each architecture has to answer this themselves.
46 */
47void ack_bad_irq(unsigned int irq)
48{
49 if (printk_ratelimit())
50 pr_err("unexpected IRQ trap at vector %02x\n", irq);
51
52 /*
53 * Currently unexpected vectors happen only on SMP and APIC.
54 * We _must_ ack these because every local APIC has only N
55 * irq slots per priority level, and a 'hanging, unacked' IRQ
56 * holds up an irq slot - in excessive cases (when multiple
57 * unexpected vectors occur) that might lock up the APIC
58 * completely.
59 * But only ack when the APIC is enabled -AK
60 */
61 apic_eoi();
62}
63
64#define irq_stats(x) (&per_cpu(irq_stat, x))
65/*
66 * /proc/interrupts printing for arch specific interrupts
67 */
68int arch_show_interrupts(struct seq_file *p, int prec)
69{
70 int j;
71
72 seq_printf(m: p, fmt: "%*s: ", prec, "NMI");
73 for_each_online_cpu(j)
74 seq_printf(m: p, fmt: "%10u ", irq_stats(j)->__nmi_count);
75 seq_puts(m: p, s: " Non-maskable interrupts\n");
76#ifdef CONFIG_X86_LOCAL_APIC
77 seq_printf(m: p, fmt: "%*s: ", prec, "LOC");
78 for_each_online_cpu(j)
79 seq_printf(m: p, fmt: "%10u ", irq_stats(j)->apic_timer_irqs);
80 seq_puts(m: p, s: " Local timer interrupts\n");
81
82 seq_printf(m: p, fmt: "%*s: ", prec, "SPU");
83 for_each_online_cpu(j)
84 seq_printf(m: p, fmt: "%10u ", irq_stats(j)->irq_spurious_count);
85 seq_puts(m: p, s: " Spurious interrupts\n");
86 seq_printf(m: p, fmt: "%*s: ", prec, "PMI");
87 for_each_online_cpu(j)
88 seq_printf(m: p, fmt: "%10u ", irq_stats(j)->apic_perf_irqs);
89 seq_puts(m: p, s: " Performance monitoring interrupts\n");
90 seq_printf(m: p, fmt: "%*s: ", prec, "IWI");
91 for_each_online_cpu(j)
92 seq_printf(m: p, fmt: "%10u ", irq_stats(j)->apic_irq_work_irqs);
93 seq_puts(m: p, s: " IRQ work interrupts\n");
94 seq_printf(m: p, fmt: "%*s: ", prec, "RTR");
95 for_each_online_cpu(j)
96 seq_printf(m: p, fmt: "%10u ", irq_stats(j)->icr_read_retry_count);
97 seq_puts(m: p, s: " APIC ICR read retries\n");
98 if (x86_platform_ipi_callback) {
99 seq_printf(m: p, fmt: "%*s: ", prec, "PLT");
100 for_each_online_cpu(j)
101 seq_printf(m: p, fmt: "%10u ", irq_stats(j)->x86_platform_ipis);
102 seq_puts(m: p, s: " Platform interrupts\n");
103 }
104#endif
105#ifdef CONFIG_SMP
106 seq_printf(m: p, fmt: "%*s: ", prec, "RES");
107 for_each_online_cpu(j)
108 seq_printf(m: p, fmt: "%10u ", irq_stats(j)->irq_resched_count);
109 seq_puts(m: p, s: " Rescheduling interrupts\n");
110 seq_printf(m: p, fmt: "%*s: ", prec, "CAL");
111 for_each_online_cpu(j)
112 seq_printf(m: p, fmt: "%10u ", irq_stats(j)->irq_call_count);
113 seq_puts(m: p, s: " Function call interrupts\n");
114 seq_printf(m: p, fmt: "%*s: ", prec, "TLB");
115 for_each_online_cpu(j)
116 seq_printf(m: p, fmt: "%10u ", irq_stats(j)->irq_tlb_count);
117 seq_puts(m: p, s: " TLB shootdowns\n");
118#endif
119#ifdef CONFIG_X86_THERMAL_VECTOR
120 seq_printf(m: p, fmt: "%*s: ", prec, "TRM");
121 for_each_online_cpu(j)
122 seq_printf(m: p, fmt: "%10u ", irq_stats(j)->irq_thermal_count);
123 seq_puts(m: p, s: " Thermal event interrupts\n");
124#endif
125#ifdef CONFIG_X86_MCE_THRESHOLD
126 seq_printf(m: p, fmt: "%*s: ", prec, "THR");
127 for_each_online_cpu(j)
128 seq_printf(m: p, fmt: "%10u ", irq_stats(j)->irq_threshold_count);
129 seq_puts(m: p, s: " Threshold APIC interrupts\n");
130#endif
131#ifdef CONFIG_X86_MCE_AMD
132 seq_printf(m: p, fmt: "%*s: ", prec, "DFR");
133 for_each_online_cpu(j)
134 seq_printf(m: p, fmt: "%10u ", irq_stats(j)->irq_deferred_error_count);
135 seq_puts(m: p, s: " Deferred Error APIC interrupts\n");
136#endif
137#ifdef CONFIG_X86_MCE
138 seq_printf(m: p, fmt: "%*s: ", prec, "MCE");
139 for_each_online_cpu(j)
140 seq_printf(m: p, fmt: "%10u ", per_cpu(mce_exception_count, j));
141 seq_puts(m: p, s: " Machine check exceptions\n");
142 seq_printf(m: p, fmt: "%*s: ", prec, "MCP");
143 for_each_online_cpu(j)
144 seq_printf(m: p, fmt: "%10u ", per_cpu(mce_poll_count, j));
145 seq_puts(m: p, s: " Machine check polls\n");
146#endif
147#ifdef CONFIG_X86_HV_CALLBACK_VECTOR
148 if (test_bit(HYPERVISOR_CALLBACK_VECTOR, system_vectors)) {
149 seq_printf(m: p, fmt: "%*s: ", prec, "HYP");
150 for_each_online_cpu(j)
151 seq_printf(m: p, fmt: "%10u ",
152 irq_stats(j)->irq_hv_callback_count);
153 seq_puts(m: p, s: " Hypervisor callback interrupts\n");
154 }
155#endif
156#if IS_ENABLED(CONFIG_HYPERV)
157 if (test_bit(HYPERV_REENLIGHTENMENT_VECTOR, system_vectors)) {
158 seq_printf(p, "%*s: ", prec, "HRE");
159 for_each_online_cpu(j)
160 seq_printf(p, "%10u ",
161 irq_stats(j)->irq_hv_reenlightenment_count);
162 seq_puts(p, " Hyper-V reenlightenment interrupts\n");
163 }
164 if (test_bit(HYPERV_STIMER0_VECTOR, system_vectors)) {
165 seq_printf(p, "%*s: ", prec, "HVS");
166 for_each_online_cpu(j)
167 seq_printf(p, "%10u ",
168 irq_stats(j)->hyperv_stimer0_count);
169 seq_puts(p, " Hyper-V stimer0 interrupts\n");
170 }
171#endif
172 seq_printf(m: p, fmt: "%*s: %10u\n", prec, "ERR", atomic_read(v: &irq_err_count));
173#if defined(CONFIG_X86_IO_APIC)
174 seq_printf(m: p, fmt: "%*s: %10u\n", prec, "MIS", atomic_read(v: &irq_mis_count));
175#endif
176#if IS_ENABLED(CONFIG_KVM)
177 seq_printf(p, "%*s: ", prec, "PIN");
178 for_each_online_cpu(j)
179 seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
180 seq_puts(p, " Posted-interrupt notification event\n");
181
182 seq_printf(p, "%*s: ", prec, "NPI");
183 for_each_online_cpu(j)
184 seq_printf(p, "%10u ",
185 irq_stats(j)->kvm_posted_intr_nested_ipis);
186 seq_puts(p, " Nested posted-interrupt event\n");
187
188 seq_printf(p, "%*s: ", prec, "PIW");
189 for_each_online_cpu(j)
190 seq_printf(p, "%10u ",
191 irq_stats(j)->kvm_posted_intr_wakeup_ipis);
192 seq_puts(p, " Posted-interrupt wakeup event\n");
193#endif
194#ifdef CONFIG_X86_POSTED_MSI
195 seq_printf(p, "%*s: ", prec, "PMN");
196 for_each_online_cpu(j)
197 seq_printf(p, "%10u ",
198 irq_stats(j)->posted_msi_notification_count);
199 seq_puts(p, " Posted MSI notification event\n");
200#endif
201 return 0;
202}
203
204/*
205 * /proc/stat helpers
206 */
207u64 arch_irq_stat_cpu(unsigned int cpu)
208{
209 u64 sum = irq_stats(cpu)->__nmi_count;
210
211#ifdef CONFIG_X86_LOCAL_APIC
212 sum += irq_stats(cpu)->apic_timer_irqs;
213 sum += irq_stats(cpu)->irq_spurious_count;
214 sum += irq_stats(cpu)->apic_perf_irqs;
215 sum += irq_stats(cpu)->apic_irq_work_irqs;
216 sum += irq_stats(cpu)->icr_read_retry_count;
217 if (x86_platform_ipi_callback)
218 sum += irq_stats(cpu)->x86_platform_ipis;
219#endif
220#ifdef CONFIG_SMP
221 sum += irq_stats(cpu)->irq_resched_count;
222 sum += irq_stats(cpu)->irq_call_count;
223#endif
224#ifdef CONFIG_X86_THERMAL_VECTOR
225 sum += irq_stats(cpu)->irq_thermal_count;
226#endif
227#ifdef CONFIG_X86_MCE_THRESHOLD
228 sum += irq_stats(cpu)->irq_threshold_count;
229#endif
230#ifdef CONFIG_X86_HV_CALLBACK_VECTOR
231 sum += irq_stats(cpu)->irq_hv_callback_count;
232#endif
233#if IS_ENABLED(CONFIG_HYPERV)
234 sum += irq_stats(cpu)->irq_hv_reenlightenment_count;
235 sum += irq_stats(cpu)->hyperv_stimer0_count;
236#endif
237#ifdef CONFIG_X86_MCE
238 sum += per_cpu(mce_exception_count, cpu);
239 sum += per_cpu(mce_poll_count, cpu);
240#endif
241 return sum;
242}
243
244u64 arch_irq_stat(void)
245{
246 u64 sum = atomic_read(v: &irq_err_count);
247 return sum;
248}
249
250static __always_inline void handle_irq(struct irq_desc *desc,
251 struct pt_regs *regs)
252{
253 if (IS_ENABLED(CONFIG_X86_64))
254 generic_handle_irq_desc(desc);
255 else
256 __handle_irq(desc, regs);
257}
258
259static struct irq_desc *reevaluate_vector(int vector)
260{
261 struct irq_desc *desc = __this_cpu_read(vector_irq[vector]);
262
263 if (!IS_ERR_OR_NULL(ptr: desc))
264 return desc;
265
266 if (desc == VECTOR_UNUSED)
267 pr_emerg_ratelimited("No irq handler for %d.%u\n", smp_processor_id(), vector);
268 else
269 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
270 return NULL;
271}
272
273static __always_inline bool call_irq_handler(int vector, struct pt_regs *regs)
274{
275 struct irq_desc *desc = __this_cpu_read(vector_irq[vector]);
276
277 if (likely(!IS_ERR_OR_NULL(desc))) {
278 handle_irq(desc, regs);
279 return true;
280 }
281
282 /*
283 * Reevaluate with vector_lock held to prevent a race against
284 * request_irq() setting up the vector:
285 *
286 * CPU0 CPU1
287 * interrupt is raised in APIC IRR
288 * but not handled
289 * free_irq()
290 * per_cpu(vector_irq, CPU1)[vector] = VECTOR_SHUTDOWN;
291 *
292 * request_irq() common_interrupt()
293 * d = this_cpu_read(vector_irq[vector]);
294 *
295 * per_cpu(vector_irq, CPU1)[vector] = desc;
296 *
297 * if (d == VECTOR_SHUTDOWN)
298 * this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
299 *
300 * This requires that the same vector on the same target CPU is
301 * handed out or that a spurious interrupt hits that CPU/vector.
302 */
303 lock_vector_lock();
304 desc = reevaluate_vector(vector);
305 unlock_vector_lock();
306
307 if (!desc)
308 return false;
309
310 handle_irq(desc, regs);
311 return true;
312}
313
314/*
315 * common_interrupt() handles all normal device IRQ's (the special SMP
316 * cross-CPU interrupts have their own entry points).
317 */
318DEFINE_IDTENTRY_IRQ(common_interrupt)
319{
320 struct pt_regs *old_regs = set_irq_regs(regs);
321
322 /* entry code tells RCU that we're not quiescent. Check it. */
323 RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
324
325 if (unlikely(!call_irq_handler(vector, regs)))
326 apic_eoi();
327
328 set_irq_regs(old_regs);
329}
330
331#ifdef CONFIG_X86_LOCAL_APIC
332/* Function pointer for generic interrupt vector handling */
333void (*x86_platform_ipi_callback)(void) = NULL;
334/*
335 * Handler for X86_PLATFORM_IPI_VECTOR.
336 */
337DEFINE_IDTENTRY_SYSVEC(sysvec_x86_platform_ipi)
338{
339 struct pt_regs *old_regs = set_irq_regs(regs);
340
341 apic_eoi();
342 trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
343 inc_irq_stat(x86_platform_ipis);
344 if (x86_platform_ipi_callback)
345 x86_platform_ipi_callback();
346 trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
347 set_irq_regs(old_regs);
348}
349#endif
350
351#if IS_ENABLED(CONFIG_KVM)
352static void dummy_handler(void) {}
353static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
354
355void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
356{
357 if (handler)
358 kvm_posted_intr_wakeup_handler = handler;
359 else {
360 kvm_posted_intr_wakeup_handler = dummy_handler;
361 synchronize_rcu();
362 }
363}
364EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
365
366/*
367 * Handler for POSTED_INTERRUPT_VECTOR.
368 */
369DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_ipi)
370{
371 apic_eoi();
372 inc_irq_stat(kvm_posted_intr_ipis);
373}
374
375/*
376 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
377 */
378DEFINE_IDTENTRY_SYSVEC(sysvec_kvm_posted_intr_wakeup_ipi)
379{
380 apic_eoi();
381 inc_irq_stat(kvm_posted_intr_wakeup_ipis);
382 kvm_posted_intr_wakeup_handler();
383}
384
385/*
386 * Handler for POSTED_INTERRUPT_NESTED_VECTOR.
387 */
388DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_nested_ipi)
389{
390 apic_eoi();
391 inc_irq_stat(kvm_posted_intr_nested_ipis);
392}
393#endif
394
395#ifdef CONFIG_X86_POSTED_MSI
396
397/* Posted Interrupt Descriptors for coalesced MSIs to be posted */
398DEFINE_PER_CPU_ALIGNED(struct pi_desc, posted_msi_pi_desc);
399
400void intel_posted_msi_init(void)
401{
402 u32 destination;
403 u32 apic_id;
404
405 this_cpu_write(posted_msi_pi_desc.nv, POSTED_MSI_NOTIFICATION_VECTOR);
406
407 /*
408 * APIC destination ID is stored in bit 8:15 while in XAPIC mode.
409 * VT-d spec. CH 9.11
410 */
411 apic_id = this_cpu_read(x86_cpu_to_apicid);
412 destination = x2apic_enabled() ? apic_id : apic_id << 8;
413 this_cpu_write(posted_msi_pi_desc.ndst, destination);
414}
415
416static __always_inline bool handle_pending_pir(unsigned long *pir, struct pt_regs *regs)
417{
418 unsigned long pir_copy[NR_PIR_WORDS];
419 int vec = FIRST_EXTERNAL_VECTOR;
420
421 if (!pi_harvest_pir(pir, pir_copy))
422 return false;
423
424 for_each_set_bit_from(vec, pir_copy, FIRST_SYSTEM_VECTOR)
425 call_irq_handler(vec, regs);
426
427 return true;
428}
429
430/*
431 * Performance data shows that 3 is good enough to harvest 90+% of the benefit
432 * on high IRQ rate workload.
433 */
434#define MAX_POSTED_MSI_COALESCING_LOOP 3
435
436/*
437 * For MSIs that are delivered as posted interrupts, the CPU notifications
438 * can be coalesced if the MSIs arrive in high frequency bursts.
439 */
440DEFINE_IDTENTRY_SYSVEC(sysvec_posted_msi_notification)
441{
442 struct pt_regs *old_regs = set_irq_regs(regs);
443 struct pi_desc *pid;
444 int i = 0;
445
446 pid = this_cpu_ptr(&posted_msi_pi_desc);
447
448 inc_irq_stat(posted_msi_notification_count);
449 irq_enter();
450
451 /*
452 * Max coalescing count includes the extra round of handle_pending_pir
453 * after clearing the outstanding notification bit. Hence, at most
454 * MAX_POSTED_MSI_COALESCING_LOOP - 1 loops are executed here.
455 */
456 while (++i < MAX_POSTED_MSI_COALESCING_LOOP) {
457 if (!handle_pending_pir(pid->pir, regs))
458 break;
459 }
460
461 /*
462 * Clear outstanding notification bit to allow new IRQ notifications,
463 * do this last to maximize the window of interrupt coalescing.
464 */
465 pi_clear_on(pid);
466
467 /*
468 * There could be a race of PI notification and the clearing of ON bit,
469 * process PIR bits one last time such that handling the new interrupts
470 * are not delayed until the next IRQ.
471 */
472 handle_pending_pir(pid->pir, regs);
473
474 apic_eoi();
475 irq_exit();
476 set_irq_regs(old_regs);
477}
478#endif /* X86_POSTED_MSI */
479
480#ifdef CONFIG_HOTPLUG_CPU
481/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
482void fixup_irqs(void)
483{
484 unsigned int vector;
485 struct irq_desc *desc;
486 struct irq_data *data;
487 struct irq_chip *chip;
488
489 irq_migrate_all_off_this_cpu();
490
491 /*
492 * We can remove mdelay() and then send spurious interrupts to
493 * new cpu targets for all the irqs that were handled previously by
494 * this cpu. While it works, I have seen spurious interrupt messages
495 * (nothing wrong but still...).
496 *
497 * So for now, retain mdelay(1) and check the IRR and then send those
498 * interrupts to new targets as this cpu is already offlined...
499 */
500 mdelay(1);
501
502 /*
503 * We can walk the vector array of this cpu without holding
504 * vector_lock because the cpu is already marked !online, so
505 * nothing else will touch it.
506 */
507 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
508 if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector])))
509 continue;
510
511 if (is_vector_pending(vector)) {
512 desc = __this_cpu_read(vector_irq[vector]);
513
514 raw_spin_lock(&desc->lock);
515 data = irq_desc_get_irq_data(desc);
516 chip = irq_data_get_irq_chip(d: data);
517 if (chip->irq_retrigger) {
518 chip->irq_retrigger(data);
519 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
520 }
521 raw_spin_unlock(&desc->lock);
522 }
523 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
524 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
525 }
526}
527#endif
528
529#ifdef CONFIG_X86_THERMAL_VECTOR
530static void smp_thermal_vector(void)
531{
532 if (x86_thermal_enabled())
533 intel_thermal_interrupt();
534 else
535 pr_err("CPU%d: Unexpected LVT thermal interrupt!\n",
536 smp_processor_id());
537}
538
539DEFINE_IDTENTRY_SYSVEC(sysvec_thermal)
540{
541 trace_thermal_apic_entry(THERMAL_APIC_VECTOR);
542 inc_irq_stat(irq_thermal_count);
543 smp_thermal_vector();
544 trace_thermal_apic_exit(THERMAL_APIC_VECTOR);
545 apic_eoi();
546}
547#endif
548