1// SPDX-License-Identifier: GPL-2.0
2#include <linux/linkage.h>
3#include <linux/errno.h>
4#include <linux/signal.h>
5#include <linux/sched.h>
6#include <linux/ioport.h>
7#include <linux/interrupt.h>
8#include <linux/irq.h>
9#include <linux/timex.h>
10#include <linux/random.h>
11#include <linux/kprobes.h>
12#include <linux/init.h>
13#include <linux/kernel_stat.h>
14#include <linux/device.h>
15#include <linux/bitops.h>
16#include <linux/acpi.h>
17#include <linux/io.h>
18#include <linux/delay.h>
19#include <linux/pgtable.h>
20
21#include <linux/atomic.h>
22#include <asm/timer.h>
23#include <asm/hw_irq.h>
24#include <asm/desc.h>
25#include <asm/io_apic.h>
26#include <asm/acpi.h>
27#include <asm/apic.h>
28#include <asm/setup.h>
29#include <asm/i8259.h>
30#include <asm/traps.h>
31#include <asm/fred.h>
32#include <asm/prom.h>
33
34/*
35 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
36 * (these are usually mapped to vectors 0x30-0x3f)
37 */
38
39/*
40 * The IO-APIC gives us many more interrupt sources. Most of these
41 * are unused but an SMP system is supposed to have enough memory ...
42 * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
43 * across the spectrum, so we really want to be prepared to get all
44 * of these. Plus, more powerful systems might have more than 64
45 * IO-APIC registers.
46 *
47 * (these are usually mapped into the 0x30-0xff vector range)
48 */
49
50DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
51 [0 ... NR_VECTORS - 1] = VECTOR_UNUSED,
52};
53
54void __init init_ISA_irqs(void)
55{
56 struct irq_chip *chip = legacy_pic->chip;
57 int i;
58
59 /*
60 * Try to set up the through-local-APIC virtual wire mode earlier.
61 *
62 * On some 32-bit UP machines, whose APIC has been disabled by BIOS
63 * and then got re-enabled by "lapic", it hangs at boot time without this.
64 */
65 init_bsp_APIC();
66
67 legacy_pic->init(0);
68
69 for (i = 0; i < nr_legacy_irqs(); i++) {
70 irq_set_chip_and_handler(irq: i, chip, handle: handle_level_irq);
71 irq_set_status_flags(irq: i, set: IRQ_LEVEL);
72 }
73}
74
75void __init init_IRQ(void)
76{
77 int i;
78
79 /*
80 * On cpu 0, Assign ISA_IRQ_VECTOR(irq) to IRQ 0..15.
81 * If these IRQ's are handled by legacy interrupt-controllers like PIC,
82 * then this configuration will likely be static after the boot. If
83 * these IRQs are handled by more modern controllers like IO-APIC,
84 * then this vector space can be freed and re-used dynamically as the
85 * irq's migrate etc.
86 */
87 for (i = 0; i < nr_legacy_irqs(); i++)
88 per_cpu(vector_irq, 0)[ISA_IRQ_VECTOR(i)] = irq_to_desc(irq: i);
89
90 BUG_ON(irq_init_percpu_irqstack(smp_processor_id()));
91
92 x86_init.irqs.intr_init();
93}
94
95void __init native_init_IRQ(void)
96{
97 /* Execute any quirks before the call gates are initialised: */
98 x86_init.irqs.pre_vector_init();
99
100 /* FRED's IRQ path may be used even if FRED isn't fully enabled. */
101 if (IS_ENABLED(CONFIG_X86_FRED))
102 fred_complete_exception_setup();
103
104 if (!cpu_feature_enabled(X86_FEATURE_FRED))
105 idt_setup_apic_and_irq_gates();
106
107 lapic_assign_system_vectors();
108
109 if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs()) {
110 /* IRQ2 is cascade interrupt to second interrupt controller */
111 if (request_irq(irq: 2, handler: no_action, IRQF_NO_THREAD, name: "cascade", NULL))
112 pr_err("%s: request_irq() failed\n", "cascade");
113 }
114}
115