1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2023 Intel Corporation
4 */
5
6#ifndef __INTEL_DISPLAY_DEVICE_H__
7#define __INTEL_DISPLAY_DEVICE_H__
8
9#include <linux/bitops.h>
10#include <linux/types.h>
11
12#include "intel_display_limits.h"
13
14struct drm_printer;
15struct intel_display;
16struct pci_dev;
17
18/*
19 * Display platforms and subplatforms. Keep platforms in display version based
20 * order, chronological order within a version, and subplatforms next to the
21 * platform.
22 */
23#define INTEL_DISPLAY_PLATFORMS(func) \
24 /* Platform group aliases */ \
25 func(g4x) /* g45 and gm45 */ \
26 func(mobile) /* mobile platforms */ \
27 func(dgfx) /* discrete graphics */ \
28 /* Display ver 2 */ \
29 func(i830) \
30 func(i845g) \
31 func(i85x) \
32 func(i865g) \
33 /* Display ver 3 */ \
34 func(i915g) \
35 func(i915gm) \
36 func(i945g) \
37 func(i945gm) \
38 func(g33) \
39 func(pineview) \
40 /* Display ver 4 */ \
41 func(i965g) \
42 func(i965gm) \
43 func(g45) \
44 func(gm45) \
45 /* Display ver 5 */ \
46 func(ironlake) \
47 /* Display ver 6 */ \
48 func(sandybridge) \
49 /* Display ver 7 */ \
50 func(ivybridge) \
51 func(valleyview) \
52 func(haswell) \
53 func(haswell_ult) \
54 func(haswell_ulx) \
55 /* Display ver 8 */ \
56 func(broadwell) \
57 func(broadwell_ult) \
58 func(broadwell_ulx) \
59 func(cherryview) \
60 /* Display ver 9 */ \
61 func(skylake) \
62 func(skylake_ult) \
63 func(skylake_ulx) \
64 func(broxton) \
65 func(kabylake) \
66 func(kabylake_ult) \
67 func(kabylake_ulx) \
68 func(geminilake) \
69 func(coffeelake) \
70 func(coffeelake_ult) \
71 func(coffeelake_ulx) \
72 func(cometlake) \
73 func(cometlake_ult) \
74 func(cometlake_ulx) \
75 /* Display ver 11 */ \
76 func(icelake) \
77 func(icelake_port_f) \
78 func(jasperlake) \
79 func(elkhartlake) \
80 /* Display ver 12 */ \
81 func(tigerlake) \
82 func(tigerlake_uy) \
83 func(rocketlake) \
84 func(dg1) \
85 func(alderlake_s) \
86 func(alderlake_s_raptorlake_s) \
87 /* Display ver 13 */ \
88 func(alderlake_p) \
89 func(alderlake_p_alderlake_n) \
90 func(alderlake_p_raptorlake_p) \
91 func(alderlake_p_raptorlake_u) \
92 func(dg2) \
93 func(dg2_g10) \
94 func(dg2_g11) \
95 func(dg2_g12) \
96 /* Display ver 14 (based on GMD ID) */ \
97 func(meteorlake) \
98 func(meteorlake_u) \
99 /* Display ver 20 (based on GMD ID) */ \
100 func(lunarlake) \
101 /* Display ver 14.1 (based on GMD ID) */ \
102 func(battlemage) \
103 /* Display ver 30 (based on GMD ID) */ \
104 func(pantherlake)
105
106#define __MEMBER(name) unsigned long name:1;
107#define __COUNT(x) 1 +
108
109#define __NUM_PLATFORMS (INTEL_DISPLAY_PLATFORMS(__COUNT) 0)
110
111struct intel_display_platforms {
112 union {
113 struct {
114 INTEL_DISPLAY_PLATFORMS(__MEMBER);
115 };
116 DECLARE_BITMAP(bitmap, __NUM_PLATFORMS);
117 };
118};
119
120#undef __MEMBER
121#undef __COUNT
122#undef __NUM_PLATFORMS
123
124#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
125 /* Keep in alphabetical order */ \
126 func(cursor_needs_physical); \
127 func(has_cdclk_crawl); \
128 func(has_cdclk_squash); \
129 func(has_ddi); \
130 func(has_dp_mst); \
131 func(has_dsb); \
132 func(has_fpga_dbg); \
133 func(has_gmch); \
134 func(has_hotplug); \
135 func(has_hti); \
136 func(has_ipc); \
137 func(has_overlay); \
138 func(has_psr); \
139 func(has_psr_hw_tracking); \
140 func(overlay_needs_physical); \
141 func(supports_tv);
142
143#define HAS_4TILE(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
144#define HAS_ASYNC_FLIPS(__display) (DISPLAY_VER(__display) >= 5)
145#define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13)
146#define HAS_BIGJOINER(__display) (DISPLAY_VER(__display) >= 11 && HAS_DSC(__display))
147#define HAS_CDCLK_CRAWL(__display) (DISPLAY_INFO(__display)->has_cdclk_crawl)
148#define HAS_CDCLK_SQUASH(__display) (DISPLAY_INFO(__display)->has_cdclk_squash)
149#define HAS_CMRR(__display) (DISPLAY_VER(__display) >= 20)
150#define HAS_CMTG(__display) (!(__display)->platform.dg2 && DISPLAY_VER(__display) >= 13)
151#define HAS_CUR_FBC(__display) (!HAS_GMCH(__display) && IS_DISPLAY_VER(__display, 7, 13))
152#define HAS_D12_PLANE_MINIMIZATION(__display) ((__display)->platform.rocketlake || (__display)->platform.alderlake_s)
153#define HAS_DBUF_OVERLAP_DETECTION(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dbuf_overlap_detection)
154#define HAS_DDI(__display) (DISPLAY_INFO(__display)->has_ddi)
155#define HAS_DISPLAY(__display) (DISPLAY_RUNTIME_INFO(__display)->pipe_mask != 0)
156#define HAS_DMC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dmc)
157#define HAS_DMC_WAKELOCK(__display) (DISPLAY_VER(__display) >= 20)
158#define HAS_DOUBLE_BUFFERED_M_N(__display) (DISPLAY_VER(__display) >= 9 || (__display)->platform.broadwell)
159#define HAS_DOUBLE_BUFFERED_LUT(__display) (DISPLAY_VER(__display) >= 30)
160#define HAS_DOUBLE_WIDE(__display) (DISPLAY_VER(__display) < 4)
161#define HAS_DP20(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
162#define HAS_DPT(__display) (DISPLAY_VER(__display) >= 13)
163#define HAS_DP_MST(__display) (DISPLAY_INFO(__display)->has_dp_mst)
164#define HAS_DSB(__display) (DISPLAY_INFO(__display)->has_dsb)
165#define HAS_DSC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dsc)
166#define HAS_DSC_3ENGINES(__display) (DISPLAY_VERx100(__display) == 1401 && HAS_DSC(__display))
167#define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
168#define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
169#define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30)
170#define HAS_FPGA_DBG_UNCLAIMED(__display) (DISPLAY_INFO(__display)->has_fpga_dbg)
171#define HAS_FW_BLC(__display) (DISPLAY_VER(__display) >= 3)
172#define HAS_GMBUS_BURST_READ(__display) (DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)
173#define HAS_GMBUS_IRQ(__display) (DISPLAY_VER(__display) >= 4)
174#define HAS_GMCH(__display) (DISPLAY_INFO(__display)->has_gmch)
175#define HAS_FDI(__display) (IS_DISPLAY_VER((__display), 5, 8) && !HAS_GMCH(__display))
176#define HAS_HOTPLUG(__display) (DISPLAY_INFO(__display)->has_hotplug)
177#define HAS_HW_SAGV_WM(__display) (DISPLAY_VER(__display) >= 13 && !(__display)->platform.dgfx)
178#define HAS_IPC(__display) (DISPLAY_INFO(__display)->has_ipc)
179#define HAS_IPS(__display) ((__display)->platform.haswell_ult || (__display)->platform.broadwell)
180#define HAS_LRR(__display) (DISPLAY_VER(__display) >= 12)
181#define HAS_LSPCON(__display) (IS_DISPLAY_VER(__display, 9, 10))
182#define HAS_MBUS_JOINING(__display) ((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14)
183#define HAS_MSO(__display) (DISPLAY_VER(__display) >= 12)
184#define HAS_OVERLAY(__display) (DISPLAY_INFO(__display)->has_overlay)
185#define HAS_PIPEDMC(__display) (DISPLAY_VER(__display) >= 12)
186#define HAS_PSR(__display) (DISPLAY_INFO(__display)->has_psr)
187#define HAS_PSR_HW_TRACKING(__display) (DISPLAY_INFO(__display)->has_psr_hw_tracking)
188#define HAS_PSR2_SEL_FETCH(__display) (DISPLAY_VER(__display) >= 12)
189#define HAS_SAGV(__display) (DISPLAY_VER(__display) >= 9 && \
190 !(__display)->platform.broxton && !(__display)->platform.geminilake)
191#define HAS_TRANSCODER(__display, trans) ((DISPLAY_RUNTIME_INFO(__display)->cpu_transcoder_mask & \
192 BIT(trans)) != 0)
193#define HAS_UNCOMPRESSED_JOINER(__display) (DISPLAY_VER(__display) >= 13)
194#define HAS_ULTRAJOINER(__display) (((__display)->platform.dgfx && \
195 DISPLAY_VER(__display) == 14) && HAS_DSC(__display))
196#define HAS_VRR(__display) (DISPLAY_VER(__display) >= 11)
197#define INTEL_NUM_PIPES(__display) (hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask))
198#define OVERLAY_NEEDS_PHYSICAL(__display) (DISPLAY_INFO(__display)->overlay_needs_physical)
199#define SUPPORTS_TV(__display) (DISPLAY_INFO(__display)->supports_tv)
200
201/* Check that device has a display IP version within the specific range. */
202#define IS_DISPLAY_VERx100(__display, from, until) ( \
203 BUILD_BUG_ON_ZERO((from) < 200) + \
204 (DISPLAY_VERx100(__display) >= (from) && \
205 DISPLAY_VERx100(__display) <= (until)))
206
207/*
208 * Check if a device has a specific IP version as well as a stepping within the
209 * specified range [from, until). The lower bound is inclusive, the upper
210 * bound is exclusive. The most common use-case of this macro is for checking
211 * bounds for workarounds, which usually have a stepping ("from") at which the
212 * hardware issue is first present and another stepping ("until") at which a
213 * hardware fix is present and the software workaround is no longer necessary.
214 * E.g.,
215 *
216 * IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B2)
217 * IS_DISPLAY_VERx100_STEP(display, 1400, STEP_C0, STEP_FOREVER)
218 *
219 * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper
220 * stepping bound for the specified IP version.
221 */
222#define IS_DISPLAY_VERx100_STEP(__display, ipver, from, until) \
223 (IS_DISPLAY_VERx100((__display), (ipver), (ipver)) && \
224 IS_DISPLAY_STEP((__display), (from), (until)))
225
226#define DISPLAY_INFO(__display) ((__display)->info.__device_info)
227#define DISPLAY_RUNTIME_INFO(__display) (&(__display)->info.__runtime_info)
228
229#define DISPLAY_VER(__display) (DISPLAY_RUNTIME_INFO(__display)->ip.ver)
230#define DISPLAY_VERx100(__display) (DISPLAY_RUNTIME_INFO(__display)->ip.ver * 100 + \
231 DISPLAY_RUNTIME_INFO(__display)->ip.rel)
232#define IS_DISPLAY_VER(__display, from, until) \
233 (DISPLAY_VER(__display) >= (from) && DISPLAY_VER(__display) <= (until))
234
235#define INTEL_DISPLAY_STEP(__display) (DISPLAY_RUNTIME_INFO(__display)->step)
236
237#define IS_DISPLAY_STEP(__display, since, until) \
238 (drm_WARN_ON((__display)->drm, INTEL_DISPLAY_STEP(__display) == STEP_NONE), \
239 INTEL_DISPLAY_STEP(__display) >= (since) && INTEL_DISPLAY_STEP(__display) < (until))
240
241#define ARLS_HOST_BRIDGE_PCI_ID1 0x7D1C
242#define ARLS_HOST_BRIDGE_PCI_ID2 0x7D2D
243#define ARLS_HOST_BRIDGE_PCI_ID3 0x7D2E
244#define ARLS_HOST_BRIDGE_PCI_ID4 0x7D2F
245
246#define IS_ARROWLAKE_S_BY_HOST_BRIDGE_ID(id) \
247 (((id) == ARLS_HOST_BRIDGE_PCI_ID1) || \
248 ((id) == ARLS_HOST_BRIDGE_PCI_ID2) || \
249 ((id) == ARLS_HOST_BRIDGE_PCI_ID3) || \
250 ((id) == ARLS_HOST_BRIDGE_PCI_ID4))
251
252struct intel_display_runtime_info {
253 struct intel_display_ip_ver {
254 u16 ver;
255 u16 rel;
256 u16 step; /* hardware */
257 } ip;
258 int step; /* symbolic */
259
260 u32 rawclk_freq;
261
262 u8 pipe_mask;
263 u8 cpu_transcoder_mask;
264 u16 port_mask;
265
266 u8 num_sprites[I915_MAX_PIPES];
267 u8 num_scalers[I915_MAX_PIPES];
268
269 u8 fbc_mask;
270
271 bool has_hdcp;
272 bool has_dmc;
273 bool has_dsc;
274 bool edp_typec_support;
275 bool has_dbuf_overlap_detection;
276};
277
278struct intel_display_device_info {
279 /* Initial runtime info. */
280 const struct intel_display_runtime_info __runtime_defaults;
281
282 u8 abox_mask;
283
284 struct {
285 u16 size; /* in blocks */
286 u8 slice_mask;
287 } dbuf;
288
289#define DEFINE_FLAG(name) u8 name:1
290 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
291#undef DEFINE_FLAG
292
293 /* Global register offset for the display engine */
294 u32 mmio_offset;
295
296 /* Register offsets for the various display pipes and transcoders */
297 u32 pipe_offsets[I915_MAX_TRANSCODERS];
298 u32 trans_offsets[I915_MAX_TRANSCODERS];
299 u32 cursor_offsets[I915_MAX_PIPES];
300
301 struct {
302 u32 degamma_lut_size;
303 u32 gamma_lut_size;
304 u32 degamma_lut_tests;
305 u32 gamma_lut_tests;
306 } color;
307};
308
309bool intel_display_device_present(struct intel_display *display);
310bool intel_display_device_enabled(struct intel_display *display);
311struct intel_display *intel_display_device_probe(struct pci_dev *pdev);
312void intel_display_device_remove(struct intel_display *display);
313void intel_display_device_info_runtime_init(struct intel_display *display);
314
315void intel_display_device_info_print(const struct intel_display_device_info *info,
316 const struct intel_display_runtime_info *runtime,
317 struct drm_printer *p);
318
319#endif
320