| 1 | /* SPDX-License-Identifier: MIT */ | 
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| 2 | /* | 
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| 3 | * Copyright © 2024 Intel Corporation | 
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| 4 | */ | 
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| 5 |  | 
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| 6 | #ifndef __INTEL_TDF_H__ | 
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| 7 | #define __INTEL_TDF_H__ | 
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| 8 |  | 
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| 9 | /* | 
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| 10 | * TDF (Transient-Data-Flush) is needed for Xe2+ where special L3:XD caching can | 
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| 11 | * be enabled through various PAT index modes. Idea is to use this caching mode | 
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| 12 | * when for example rendering onto the display surface, with the promise that | 
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| 13 | * KMD will ensure transient cache entries are always flushed by the time we do | 
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| 14 | * the display flip, since display engine is never coherent with CPU/GPU caches. | 
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| 15 | */ | 
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| 16 |  | 
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| 17 | struct intel_display; | 
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| 18 |  | 
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| 19 | #ifdef I915 | 
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| 20 | static inline void intel_td_flush(struct intel_display *display) {} | 
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| 21 | #else | 
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| 22 | void intel_td_flush(struct intel_display *display); | 
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| 23 | #endif | 
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| 24 |  | 
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| 25 | #endif | 
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| 26 |  | 
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