1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27#include <linux/dma-resv.h>
28#include <linux/i2c.h>
29#include <linux/input.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/slab.h>
33#include <linux/string_helpers.h>
34
35#include <drm/display/drm_dp_helper.h>
36#include <drm/display/drm_dp_tunnel.h>
37#include <drm/drm_atomic.h>
38#include <drm/drm_atomic_helper.h>
39#include <drm/drm_atomic_uapi.h>
40#include <drm/drm_damage_helper.h>
41#include <drm/drm_edid.h>
42#include <drm/drm_fixed.h>
43#include <drm/drm_fourcc.h>
44#include <drm/drm_probe_helper.h>
45#include <drm/drm_rect.h>
46#include <drm/drm_vblank.h>
47
48#include "g4x_dp.h"
49#include "g4x_hdmi.h"
50#include "hsw_ips.h"
51#include "i915_config.h"
52#include "i915_drv.h"
53#include "i915_reg.h"
54#include "i915_utils.h"
55#include "i9xx_plane.h"
56#include "i9xx_plane_regs.h"
57#include "i9xx_wm.h"
58#include "intel_alpm.h"
59#include "intel_atomic.h"
60#include "intel_audio.h"
61#include "intel_bo.h"
62#include "intel_bw.h"
63#include "intel_cdclk.h"
64#include "intel_clock_gating.h"
65#include "intel_color.h"
66#include "intel_crt.h"
67#include "intel_crtc.h"
68#include "intel_crtc_state_dump.h"
69#include "intel_cursor.h"
70#include "intel_cursor_regs.h"
71#include "intel_cx0_phy.h"
72#include "intel_ddi.h"
73#include "intel_de.h"
74#include "intel_display_driver.h"
75#include "intel_display_power.h"
76#include "intel_display_regs.h"
77#include "intel_display_rpm.h"
78#include "intel_display_types.h"
79#include "intel_display_wa.h"
80#include "intel_dmc.h"
81#include "intel_dp.h"
82#include "intel_dp_link_training.h"
83#include "intel_dp_mst.h"
84#include "intel_dp_tunnel.h"
85#include "intel_dpll.h"
86#include "intel_dpll_mgr.h"
87#include "intel_dpt.h"
88#include "intel_dpt_common.h"
89#include "intel_drrs.h"
90#include "intel_dsb.h"
91#include "intel_dsi.h"
92#include "intel_dvo.h"
93#include "intel_fb.h"
94#include "intel_fbc.h"
95#include "intel_fdi.h"
96#include "intel_fifo_underrun.h"
97#include "intel_flipq.h"
98#include "intel_frontbuffer.h"
99#include "intel_hdmi.h"
100#include "intel_hotplug.h"
101#include "intel_link_bw.h"
102#include "intel_lvds.h"
103#include "intel_lvds_regs.h"
104#include "intel_modeset_setup.h"
105#include "intel_modeset_verify.h"
106#include "intel_overlay.h"
107#include "intel_panel.h"
108#include "intel_pch_display.h"
109#include "intel_pch_refclk.h"
110#include "intel_pfit.h"
111#include "intel_pipe_crc.h"
112#include "intel_plane.h"
113#include "intel_plane_initial.h"
114#include "intel_pmdemand.h"
115#include "intel_pps.h"
116#include "intel_psr.h"
117#include "intel_psr_regs.h"
118#include "intel_sdvo.h"
119#include "intel_snps_phy.h"
120#include "intel_tc.h"
121#include "intel_tdf.h"
122#include "intel_tv.h"
123#include "intel_vblank.h"
124#include "intel_vdsc.h"
125#include "intel_vdsc_regs.h"
126#include "intel_vga.h"
127#include "intel_vrr.h"
128#include "intel_wm.h"
129#include "skl_scaler.h"
130#include "skl_universal_plane.h"
131#include "skl_watermark.h"
132#include "vlv_dpio_phy_regs.h"
133#include "vlv_dsi.h"
134#include "vlv_dsi_pll.h"
135#include "vlv_dsi_regs.h"
136#include "vlv_sideband.h"
137
138static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
139static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
140static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
141static void bdw_set_pipe_misc(struct intel_dsb *dsb,
142 const struct intel_crtc_state *crtc_state);
143
144/* returns HPLL frequency in kHz */
145int vlv_get_hpll_vco(struct drm_device *drm)
146{
147 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
148
149 /* Obtain SKU information */
150 hpll_freq = vlv_cck_read(drm, CCK_FUSE_REG) &
151 CCK_FUSE_HPLL_FREQ_MASK;
152
153 return vco_freq[hpll_freq] * 1000;
154}
155
156int vlv_get_cck_clock(struct drm_device *drm,
157 const char *name, u32 reg, int ref_freq)
158{
159 u32 val;
160 int divider;
161
162 val = vlv_cck_read(drm, reg);
163 divider = val & CCK_FREQUENCY_VALUES;
164
165 drm_WARN(drm, (val & CCK_FREQUENCY_STATUS) !=
166 (divider << CCK_FREQUENCY_STATUS_SHIFT),
167 "%s change in progress\n", name);
168
169 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
170}
171
172int vlv_get_cck_clock_hpll(struct drm_device *drm,
173 const char *name, u32 reg)
174{
175 struct drm_i915_private *dev_priv = to_i915(dev: drm);
176 int hpll;
177
178 vlv_cck_get(drm);
179
180 if (dev_priv->hpll_freq == 0)
181 dev_priv->hpll_freq = vlv_get_hpll_vco(drm);
182
183 hpll = vlv_get_cck_clock(drm, name, reg, ref_freq: dev_priv->hpll_freq);
184
185 vlv_cck_put(drm);
186
187 return hpll;
188}
189
190void intel_update_czclk(struct intel_display *display)
191{
192 struct drm_i915_private *dev_priv = to_i915(dev: display->drm);
193
194 if (!display->platform.valleyview && !display->platform.cherryview)
195 return;
196
197 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(drm: display->drm, name: "czclk",
198 CCK_CZ_CLOCK_CONTROL);
199
200 drm_dbg_kms(display->drm, "CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
201}
202
203static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
204{
205 return (crtc_state->active_planes &
206 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
207}
208
209/* WA Display #0827: Gen9:all */
210static void
211skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable)
212{
213 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),
214 DUPS1_GATING_DIS | DUPS2_GATING_DIS,
215 set: enable ? DUPS1_GATING_DIS | DUPS2_GATING_DIS : 0);
216}
217
218/* Wa_2006604312:icl,ehl */
219static void
220icl_wa_scalerclkgating(struct intel_display *display, enum pipe pipe,
221 bool enable)
222{
223 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),
224 DPFR_GATING_DIS,
225 set: enable ? DPFR_GATING_DIS : 0);
226}
227
228/* Wa_1604331009:icl,jsl,ehl */
229static void
230icl_wa_cursorclkgating(struct intel_display *display, enum pipe pipe,
231 bool enable)
232{
233 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),
234 CURSOR_GATING_DIS,
235 set: enable ? CURSOR_GATING_DIS : 0);
236}
237
238static bool
239is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
240{
241 return crtc_state->master_transcoder != INVALID_TRANSCODER;
242}
243
244bool
245is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
246{
247 return crtc_state->sync_mode_slaves_mask != 0;
248}
249
250bool
251is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
252{
253 return is_trans_port_sync_master(crtc_state) ||
254 is_trans_port_sync_slave(crtc_state);
255}
256
257static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state)
258{
259 return ffs(crtc_state->joiner_pipes) - 1;
260}
261
262/*
263 * The following helper functions, despite being named for bigjoiner,
264 * are applicable to both bigjoiner and uncompressed joiner configurations.
265 */
266static bool is_bigjoiner(const struct intel_crtc_state *crtc_state)
267{
268 return hweight8(crtc_state->joiner_pipes) >= 2;
269}
270
271static u8 bigjoiner_primary_pipes(const struct intel_crtc_state *crtc_state)
272{
273 if (!is_bigjoiner(crtc_state))
274 return 0;
275
276 return crtc_state->joiner_pipes & (0b01010101 << joiner_primary_pipe(crtc_state));
277}
278
279static unsigned int bigjoiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
280{
281 if (!is_bigjoiner(crtc_state))
282 return 0;
283
284 return crtc_state->joiner_pipes & (0b10101010 << joiner_primary_pipe(crtc_state));
285}
286
287bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state)
288{
289 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
290
291 if (!is_bigjoiner(crtc_state))
292 return false;
293
294 return BIT(crtc->pipe) & bigjoiner_primary_pipes(crtc_state);
295}
296
297bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state)
298{
299 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
300
301 if (!is_bigjoiner(crtc_state))
302 return false;
303
304 return BIT(crtc->pipe) & bigjoiner_secondary_pipes(crtc_state);
305}
306
307u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state)
308{
309 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
310
311 if (!is_bigjoiner(crtc_state))
312 return BIT(crtc->pipe);
313
314 return bigjoiner_primary_pipes(crtc_state);
315}
316
317u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state)
318{
319 return bigjoiner_secondary_pipes(crtc_state);
320}
321
322bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state)
323{
324 return intel_crtc_num_joined_pipes(crtc_state) >= 4;
325}
326
327static u8 ultrajoiner_primary_pipes(const struct intel_crtc_state *crtc_state)
328{
329 if (!intel_crtc_is_ultrajoiner(crtc_state))
330 return 0;
331
332 return crtc_state->joiner_pipes & (0b00010001 << joiner_primary_pipe(crtc_state));
333}
334
335bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state)
336{
337 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
338
339 return intel_crtc_is_ultrajoiner(crtc_state) &&
340 BIT(crtc->pipe) & ultrajoiner_primary_pipes(crtc_state);
341}
342
343/*
344 * The ultrajoiner enable bit doesn't seem to follow primary/secondary logic or
345 * any other logic, so lets just add helper function to
346 * at least hide this hassle..
347 */
348static u8 ultrajoiner_enable_pipes(const struct intel_crtc_state *crtc_state)
349{
350 if (!intel_crtc_is_ultrajoiner(crtc_state))
351 return 0;
352
353 return crtc_state->joiner_pipes & (0b01110111 << joiner_primary_pipe(crtc_state));
354}
355
356bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state)
357{
358 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
359
360 return intel_crtc_is_ultrajoiner(crtc_state) &&
361 BIT(crtc->pipe) & ultrajoiner_enable_pipes(crtc_state);
362}
363
364u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
365{
366 if (crtc_state->joiner_pipes)
367 return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state));
368 else
369 return 0;
370}
371
372bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state)
373{
374 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
375
376 return crtc_state->joiner_pipes &&
377 crtc->pipe != joiner_primary_pipe(crtc_state);
378}
379
380bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state)
381{
382 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
383
384 return crtc_state->joiner_pipes &&
385 crtc->pipe == joiner_primary_pipe(crtc_state);
386}
387
388int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state)
389{
390 return hweight8(intel_crtc_joined_pipe_mask(crtc_state));
391}
392
393u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state)
394{
395 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
396
397 return BIT(crtc->pipe) | crtc_state->joiner_pipes;
398}
399
400struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state)
401{
402 struct intel_display *display = to_intel_display(crtc_state);
403
404 if (intel_crtc_is_joiner_secondary(crtc_state))
405 return intel_crtc_for_pipe(display, pipe: joiner_primary_pipe(crtc_state));
406 else
407 return to_intel_crtc(crtc_state->uapi.crtc);
408}
409
410static void
411intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
412{
413 struct intel_display *display = to_intel_display(old_crtc_state);
414 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
415
416 if (DISPLAY_VER(display) >= 4) {
417 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
418
419 /* Wait for the Pipe State to go off */
420 if (intel_de_wait_for_clear(display, TRANSCONF(display, cpu_transcoder),
421 TRANSCONF_STATE_ENABLE, timeout_ms: 100))
422 drm_WARN(display->drm, 1, "pipe_off wait timed out\n");
423 } else {
424 intel_wait_for_pipe_scanline_stopped(crtc);
425 }
426}
427
428void assert_transcoder(struct intel_display *display,
429 enum transcoder cpu_transcoder, bool state)
430{
431 bool cur_state;
432 enum intel_display_power_domain power_domain;
433 intel_wakeref_t wakeref;
434
435 /* we keep both pipes enabled on 830 */
436 if (display->platform.i830)
437 state = true;
438
439 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
440 wakeref = intel_display_power_get_if_enabled(display, domain: power_domain);
441 if (wakeref) {
442 u32 val = intel_de_read(display,
443 TRANSCONF(display, cpu_transcoder));
444 cur_state = !!(val & TRANSCONF_ENABLE);
445
446 intel_display_power_put(display, domain: power_domain, wakeref);
447 } else {
448 cur_state = false;
449 }
450
451 INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
452 "transcoder %s assertion failure (expected %s, current %s)\n",
453 transcoder_name(cpu_transcoder), str_on_off(state),
454 str_on_off(cur_state));
455}
456
457static void assert_plane(struct intel_plane *plane, bool state)
458{
459 struct intel_display *display = to_intel_display(plane->base.dev);
460 enum pipe pipe;
461 bool cur_state;
462
463 cur_state = plane->get_hw_state(plane, &pipe);
464
465 INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
466 "%s assertion failure (expected %s, current %s)\n",
467 plane->base.name, str_on_off(state),
468 str_on_off(cur_state));
469}
470
471#define assert_plane_enabled(p) assert_plane(p, true)
472#define assert_plane_disabled(p) assert_plane(p, false)
473
474static void assert_planes_disabled(struct intel_crtc *crtc)
475{
476 struct intel_display *display = to_intel_display(crtc);
477 struct intel_plane *plane;
478
479 for_each_intel_plane_on_crtc(display->drm, crtc, plane)
480 assert_plane_disabled(plane);
481}
482
483void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
484{
485 struct intel_display *display = to_intel_display(new_crtc_state);
486 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
487 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
488 enum pipe pipe = crtc->pipe;
489 u32 val;
490
491 drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe));
492
493 assert_planes_disabled(crtc);
494
495 /*
496 * A pipe without a PLL won't actually be able to drive bits from
497 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
498 * need the check.
499 */
500 if (HAS_GMCH(display)) {
501 if (intel_crtc_has_type(crtc_state: new_crtc_state, type: INTEL_OUTPUT_DSI))
502 assert_dsi_pll_enabled(display);
503 else
504 assert_pll_enabled(display, pipe);
505 } else {
506 if (new_crtc_state->has_pch_encoder) {
507 /* if driving the PCH, we need FDI enabled */
508 assert_fdi_rx_pll_enabled(display,
509 pipe: intel_crtc_pch_transcoder(crtc));
510 assert_fdi_tx_pll_enabled(display,
511 pipe: (enum pipe) cpu_transcoder);
512 }
513 /* FIXME: assert CPU port conditions for SNB+ */
514 }
515
516 /* Wa_22012358565:adl-p */
517 if (DISPLAY_VER(display) == 13)
518 intel_de_rmw(display, PIPE_ARB_CTL(display, pipe),
519 clear: 0, PIPE_ARB_USE_PROG_SLOTS);
520
521 if (DISPLAY_VER(display) >= 14) {
522 u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA;
523 u32 set = 0;
524
525 if (DISPLAY_VER(display) == 14)
526 set |= DP_FEC_BS_JITTER_WA;
527
528 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
529 clear, set);
530 }
531
532 val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
533 if (val & TRANSCONF_ENABLE) {
534 /* we keep both pipes enabled on 830 */
535 drm_WARN_ON(display->drm, !display->platform.i830);
536 return;
537 }
538
539 /* Wa_1409098942:adlp+ */
540 if (DISPLAY_VER(display) >= 13 &&
541 new_crtc_state->dsc.compression_enable) {
542 val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
543 val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
544 TRANSCONF_PIXEL_COUNT_SCALING_X4);
545 }
546
547 intel_de_write(display, TRANSCONF(display, cpu_transcoder),
548 val: val | TRANSCONF_ENABLE);
549 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
550
551 /*
552 * Until the pipe starts PIPEDSL reads will return a stale value,
553 * which causes an apparent vblank timestamp jump when PIPEDSL
554 * resets to its proper value. That also messes up the frame count
555 * when it's derived from the timestamps. So let's wait for the
556 * pipe to start properly before we call drm_crtc_vblank_on()
557 */
558 if (intel_crtc_max_vblank_count(crtc_state: new_crtc_state) == 0)
559 intel_wait_for_pipe_scanline_moving(crtc);
560}
561
562void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
563{
564 struct intel_display *display = to_intel_display(old_crtc_state);
565 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
566 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
567 enum pipe pipe = crtc->pipe;
568 u32 val;
569
570 drm_dbg_kms(display->drm, "disabling pipe %c\n", pipe_name(pipe));
571
572 /*
573 * Make sure planes won't keep trying to pump pixels to us,
574 * or we might hang the display.
575 */
576 assert_planes_disabled(crtc);
577
578 val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
579 if ((val & TRANSCONF_ENABLE) == 0)
580 return;
581
582 /*
583 * Double wide has implications for planes
584 * so best keep it disabled when not needed.
585 */
586 if (old_crtc_state->double_wide)
587 val &= ~TRANSCONF_DOUBLE_WIDE;
588
589 /* Don't disable pipe or pipe PLLs if needed */
590 if (!display->platform.i830)
591 val &= ~TRANSCONF_ENABLE;
592
593 /* Wa_1409098942:adlp+ */
594 if (DISPLAY_VER(display) >= 13 &&
595 old_crtc_state->dsc.compression_enable)
596 val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
597
598 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
599
600 if (DISPLAY_VER(display) >= 12)
601 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
602 FECSTALL_DIS_DPTSTREAM_DPTTG, set: 0);
603
604 if ((val & TRANSCONF_ENABLE) == 0)
605 intel_wait_for_pipe_off(old_crtc_state);
606}
607
608u32 intel_plane_fb_max_stride(struct drm_device *drm,
609 u32 pixel_format, u64 modifier)
610{
611 struct intel_display *display = to_intel_display(drm);
612 struct intel_crtc *crtc;
613 struct intel_plane *plane;
614
615 if (!HAS_DISPLAY(display))
616 return 0;
617
618 /*
619 * We assume the primary plane for pipe A has
620 * the highest stride limits of them all,
621 * if in case pipe A is disabled, use the first pipe from pipe_mask.
622 */
623 crtc = intel_first_crtc(display);
624 if (!crtc)
625 return 0;
626
627 plane = to_intel_plane(crtc->base.primary);
628
629 return plane->max_stride(plane, pixel_format, modifier,
630 DRM_MODE_ROTATE_0);
631}
632
633void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
634 struct intel_plane_state *plane_state,
635 bool visible)
636{
637 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
638
639 plane_state->uapi.visible = visible;
640
641 if (visible)
642 crtc_state->uapi.plane_mask |= drm_plane_mask(plane: &plane->base);
643 else
644 crtc_state->uapi.plane_mask &= ~drm_plane_mask(plane: &plane->base);
645}
646
647void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
648{
649 struct intel_display *display = to_intel_display(crtc_state);
650 struct drm_plane *plane;
651
652 /*
653 * Active_planes aliases if multiple "primary" or cursor planes
654 * have been used on the same (or wrong) pipe. plane_mask uses
655 * unique ids, hence we can use that to reconstruct active_planes.
656 */
657 crtc_state->enabled_planes = 0;
658 crtc_state->active_planes = 0;
659
660 drm_for_each_plane_mask(plane, display->drm,
661 crtc_state->uapi.plane_mask) {
662 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
663 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
664 }
665}
666
667void intel_plane_disable_noatomic(struct intel_crtc *crtc,
668 struct intel_plane *plane)
669{
670 struct intel_display *display = to_intel_display(crtc);
671 struct intel_crtc_state *crtc_state =
672 to_intel_crtc_state(crtc->base.state);
673 struct intel_plane_state *plane_state =
674 to_intel_plane_state(plane->base.state);
675
676 drm_dbg_kms(display->drm,
677 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
678 plane->base.base.id, plane->base.name,
679 crtc->base.base.id, crtc->base.name);
680
681 intel_plane_set_invisible(crtc_state, plane_state);
682 intel_set_plane_visible(crtc_state, plane_state, visible: false);
683 intel_plane_fixup_bitmasks(crtc_state);
684
685 skl_wm_plane_disable_noatomic(crtc, plane);
686
687 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
688 hsw_ips_disable(crtc_state)) {
689 crtc_state->ips_enabled = false;
690 intel_plane_initial_vblank_wait(crtc);
691 }
692
693 /*
694 * Vblank time updates from the shadow to live plane control register
695 * are blocked if the memory self-refresh mode is active at that
696 * moment. So to make sure the plane gets truly disabled, disable
697 * first the self-refresh mode. The self-refresh enable bit in turn
698 * will be checked/applied by the HW only at the next frame start
699 * event which is after the vblank start event, so we need to have a
700 * wait-for-vblank between disabling the plane and the pipe.
701 */
702 if (HAS_GMCH(display) &&
703 intel_set_memory_cxsr(display, enable: false))
704 intel_plane_initial_vblank_wait(crtc);
705
706 /*
707 * Gen2 reports pipe underruns whenever all planes are disabled.
708 * So disable underrun reporting before all the planes get disabled.
709 */
710 if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes)
711 intel_set_cpu_fifo_underrun_reporting(display, pipe: crtc->pipe, enable: false);
712
713 intel_plane_disable_arm(NULL, plane, crtc_state);
714 intel_plane_initial_vblank_wait(crtc);
715}
716
717unsigned int
718intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
719{
720 int x = 0, y = 0;
721
722 intel_plane_adjust_aligned_offset(x: &x, y: &y, plane_state, color_plane: 0,
723 old_offset: plane_state->view.color_plane[0].offset, new_offset: 0);
724
725 return y;
726}
727
728static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
729{
730 struct intel_display *display = to_intel_display(crtc_state);
731 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
732 enum pipe pipe = crtc->pipe;
733 u32 tmp;
734
735 tmp = intel_de_read(display, PIPE_CHICKEN(pipe));
736
737 /*
738 * Display WA #1153: icl
739 * enable hardware to bypass the alpha math
740 * and rounding for per-pixel values 00 and 0xff
741 */
742 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
743 /*
744 * Display WA # 1605353570: icl
745 * Set the pixel rounding bit to 1 for allowing
746 * passthrough of Frame buffer pixels unmodified
747 * across pipe
748 */
749 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
750
751 /*
752 * Underrun recovery must always be disabled on display 13+.
753 * DG2 chicken bit meaning is inverted compared to other platforms.
754 */
755 if (display->platform.dg2)
756 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
757 else if ((DISPLAY_VER(display) >= 13) && (DISPLAY_VER(display) < 30))
758 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
759
760 /* Wa_14010547955:dg2 */
761 if (display->platform.dg2)
762 tmp |= DG2_RENDER_CCSTAG_4_3_EN;
763
764 intel_de_write(display, PIPE_CHICKEN(pipe), val: tmp);
765}
766
767bool intel_has_pending_fb_unpin(struct intel_display *display)
768{
769 struct drm_crtc *crtc;
770 bool cleanup_done;
771
772 drm_for_each_crtc(crtc, display->drm) {
773 struct drm_crtc_commit *commit;
774 spin_lock(lock: &crtc->commit_lock);
775 commit = list_first_entry_or_null(&crtc->commit_list,
776 struct drm_crtc_commit, commit_entry);
777 cleanup_done = commit ?
778 try_wait_for_completion(x: &commit->cleanup_done) : true;
779 spin_unlock(lock: &crtc->commit_lock);
780
781 if (cleanup_done)
782 continue;
783
784 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
785
786 return true;
787 }
788
789 return false;
790}
791
792/*
793 * Finds the encoder associated with the given CRTC. This can only be
794 * used when we know that the CRTC isn't feeding multiple encoders!
795 */
796struct intel_encoder *
797intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
798 const struct intel_crtc_state *crtc_state)
799{
800 const struct drm_connector_state *connector_state;
801 const struct drm_connector *connector;
802 struct intel_encoder *encoder = NULL;
803 struct intel_crtc *primary_crtc;
804 int num_encoders = 0;
805 int i;
806
807 primary_crtc = intel_primary_crtc(crtc_state);
808
809 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
810 if (connector_state->crtc != &primary_crtc->base)
811 continue;
812
813 encoder = to_intel_encoder(connector_state->best_encoder);
814 num_encoders++;
815 }
816
817 drm_WARN(state->base.dev, num_encoders != 1,
818 "%d encoders for pipe %c\n",
819 num_encoders, pipe_name(primary_crtc->pipe));
820
821 return encoder;
822}
823
824static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
825{
826 if (crtc->overlay)
827 (void) intel_overlay_switch_off(overlay: crtc->overlay);
828
829 /* Let userspace switch the overlay on again. In most cases userspace
830 * has to recompute where to put it anyway.
831 */
832}
833
834static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
835{
836 struct intel_display *display = to_intel_display(crtc_state);
837
838 if (!crtc_state->nv12_planes)
839 return false;
840
841 /* WA Display #0827: Gen9:all */
842 if (DISPLAY_VER(display) == 9)
843 return true;
844
845 return false;
846}
847
848static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
849{
850 struct intel_display *display = to_intel_display(crtc_state);
851
852 /* Wa_2006604312:icl,ehl */
853 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(display) == 11)
854 return true;
855
856 return false;
857}
858
859static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
860{
861 struct intel_display *display = to_intel_display(crtc_state);
862
863 /* Wa_1604331009:icl,jsl,ehl */
864 if (is_hdr_mode(crtc_state) &&
865 crtc_state->active_planes & BIT(PLANE_CURSOR) &&
866 DISPLAY_VER(display) == 11)
867 return true;
868
869 return false;
870}
871
872static void intel_async_flip_vtd_wa(struct intel_display *display,
873 enum pipe pipe, bool enable)
874{
875 if (DISPLAY_VER(display) == 9) {
876 /*
877 * "Plane N stretch max must be programmed to 11b (x1)
878 * when Async flips are enabled on that plane."
879 */
880 intel_de_rmw(display, CHICKEN_PIPESL_1(pipe),
881 SKL_PLANE1_STRETCH_MAX_MASK,
882 set: enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
883 } else {
884 /* Also needed on HSW/BDW albeit undocumented */
885 intel_de_rmw(display, CHICKEN_PIPESL_1(pipe),
886 HSW_PRI_STRETCH_MAX_MASK,
887 set: enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
888 }
889}
890
891static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
892{
893 struct intel_display *display = to_intel_display(crtc_state);
894 struct drm_i915_private *i915 = to_i915(dev: crtc_state->uapi.crtc->dev);
895
896 return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&
897 (DISPLAY_VER(display) == 9 || display->platform.broadwell ||
898 display->platform.haswell);
899}
900
901static void intel_encoders_audio_enable(struct intel_atomic_state *state,
902 struct intel_crtc *crtc)
903{
904 const struct intel_crtc_state *crtc_state =
905 intel_atomic_get_new_crtc_state(state, crtc);
906 const struct drm_connector_state *conn_state;
907 struct drm_connector *conn;
908 int i;
909
910 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
911 struct intel_encoder *encoder =
912 to_intel_encoder(conn_state->best_encoder);
913
914 if (conn_state->crtc != &crtc->base)
915 continue;
916
917 if (encoder->audio_enable)
918 encoder->audio_enable(encoder, crtc_state, conn_state);
919 }
920}
921
922static void intel_encoders_audio_disable(struct intel_atomic_state *state,
923 struct intel_crtc *crtc)
924{
925 const struct intel_crtc_state *old_crtc_state =
926 intel_atomic_get_old_crtc_state(state, crtc);
927 const struct drm_connector_state *old_conn_state;
928 struct drm_connector *conn;
929 int i;
930
931 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
932 struct intel_encoder *encoder =
933 to_intel_encoder(old_conn_state->best_encoder);
934
935 if (old_conn_state->crtc != &crtc->base)
936 continue;
937
938 if (encoder->audio_disable)
939 encoder->audio_disable(encoder, old_crtc_state, old_conn_state);
940 }
941}
942
943#define is_enabling(feature, old_crtc_state, new_crtc_state) \
944 ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
945 (new_crtc_state)->feature)
946#define is_disabling(feature, old_crtc_state, new_crtc_state) \
947 ((old_crtc_state)->feature && \
948 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
949
950static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
951 const struct intel_crtc_state *new_crtc_state)
952{
953 if (!new_crtc_state->hw.active)
954 return false;
955
956 return is_enabling(active_planes, old_crtc_state, new_crtc_state);
957}
958
959static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
960 const struct intel_crtc_state *new_crtc_state)
961{
962 if (!old_crtc_state->hw.active)
963 return false;
964
965 return is_disabling(active_planes, old_crtc_state, new_crtc_state);
966}
967
968static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
969 const struct intel_crtc_state *new_crtc_state)
970{
971 return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||
972 old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||
973 old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||
974 old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||
975 old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full ||
976 old_crtc_state->vrr.vsync_start != new_crtc_state->vrr.vsync_start ||
977 old_crtc_state->vrr.vsync_end != new_crtc_state->vrr.vsync_end;
978}
979
980static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
981 const struct intel_crtc_state *new_crtc_state)
982{
983 return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
984 old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
985}
986
987static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
988 struct intel_crtc *crtc)
989{
990 const struct intel_crtc_state *old_crtc_state =
991 intel_atomic_get_old_crtc_state(state, crtc);
992 const struct intel_crtc_state *new_crtc_state =
993 intel_atomic_get_new_crtc_state(state, crtc);
994
995 if (!new_crtc_state->hw.active)
996 return false;
997
998 return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
999 (new_crtc_state->vrr.enable &&
1000 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
1001 vrr_params_changed(old_crtc_state, new_crtc_state)));
1002}
1003
1004bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
1005 struct intel_crtc *crtc)
1006{
1007 const struct intel_crtc_state *old_crtc_state =
1008 intel_atomic_get_old_crtc_state(state, crtc);
1009 const struct intel_crtc_state *new_crtc_state =
1010 intel_atomic_get_new_crtc_state(state, crtc);
1011
1012 if (!old_crtc_state->hw.active)
1013 return false;
1014
1015 return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
1016 (old_crtc_state->vrr.enable &&
1017 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
1018 vrr_params_changed(old_crtc_state, new_crtc_state)));
1019}
1020
1021static bool audio_enabling(const struct intel_crtc_state *old_crtc_state,
1022 const struct intel_crtc_state *new_crtc_state)
1023{
1024 if (!new_crtc_state->hw.active)
1025 return false;
1026
1027 return is_enabling(has_audio, old_crtc_state, new_crtc_state) ||
1028 (new_crtc_state->has_audio &&
1029 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);
1030}
1031
1032static bool audio_disabling(const struct intel_crtc_state *old_crtc_state,
1033 const struct intel_crtc_state *new_crtc_state)
1034{
1035 if (!old_crtc_state->hw.active)
1036 return false;
1037
1038 return is_disabling(has_audio, old_crtc_state, new_crtc_state) ||
1039 (old_crtc_state->has_audio &&
1040 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);
1041}
1042
1043#undef is_disabling
1044#undef is_enabling
1045
1046static void intel_post_plane_update(struct intel_atomic_state *state,
1047 struct intel_crtc *crtc)
1048{
1049 struct intel_display *display = to_intel_display(state);
1050 const struct intel_crtc_state *old_crtc_state =
1051 intel_atomic_get_old_crtc_state(state, crtc);
1052 const struct intel_crtc_state *new_crtc_state =
1053 intel_atomic_get_new_crtc_state(state, crtc);
1054 enum pipe pipe = crtc->pipe;
1055
1056 intel_frontbuffer_flip(display, frontbuffer_bits: new_crtc_state->fb_bits);
1057
1058 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
1059 intel_update_watermarks(display);
1060
1061 intel_fbc_post_update(state, crtc);
1062
1063 if (needs_async_flip_vtd_wa(crtc_state: old_crtc_state) &&
1064 !needs_async_flip_vtd_wa(crtc_state: new_crtc_state))
1065 intel_async_flip_vtd_wa(display, pipe, enable: false);
1066
1067 if (needs_nv12_wa(crtc_state: old_crtc_state) &&
1068 !needs_nv12_wa(crtc_state: new_crtc_state))
1069 skl_wa_827(display, pipe, enable: false);
1070
1071 if (needs_scalerclk_wa(crtc_state: old_crtc_state) &&
1072 !needs_scalerclk_wa(crtc_state: new_crtc_state))
1073 icl_wa_scalerclkgating(display, pipe, enable: false);
1074
1075 if (needs_cursorclk_wa(crtc_state: old_crtc_state) &&
1076 !needs_cursorclk_wa(crtc_state: new_crtc_state))
1077 icl_wa_cursorclkgating(display, pipe, enable: false);
1078
1079 if (intel_crtc_needs_color_update(crtc_state: new_crtc_state))
1080 intel_color_post_update(crtc_state: new_crtc_state);
1081
1082 if (audio_enabling(old_crtc_state, new_crtc_state))
1083 intel_encoders_audio_enable(state, crtc);
1084
1085 if (intel_display_wa(display, 14011503117)) {
1086 if (old_crtc_state->pch_pfit.enabled != new_crtc_state->pch_pfit.enabled)
1087 adl_scaler_ecc_unmask(crtc_state: new_crtc_state);
1088 }
1089
1090 intel_alpm_post_plane_update(state, crtc);
1091
1092 intel_psr_post_plane_update(state, crtc);
1093}
1094
1095static void intel_post_plane_update_after_readout(struct intel_atomic_state *state,
1096 struct intel_crtc *crtc)
1097{
1098 const struct intel_crtc_state *new_crtc_state =
1099 intel_atomic_get_new_crtc_state(state, crtc);
1100
1101 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */
1102 hsw_ips_post_update(state, crtc);
1103
1104 /*
1105 * Activate DRRS after state readout to avoid
1106 * dp_m_n vs. dp_m2_n2 confusion on BDW+.
1107 */
1108 intel_drrs_activate(crtc_state: new_crtc_state);
1109}
1110
1111static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
1112 struct intel_crtc *crtc)
1113{
1114 const struct intel_crtc_state *crtc_state =
1115 intel_atomic_get_new_crtc_state(state, crtc);
1116 u8 update_planes = crtc_state->update_planes;
1117 const struct intel_plane_state __maybe_unused *plane_state;
1118 struct intel_plane *plane;
1119 int i;
1120
1121 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1122 if (plane->pipe == crtc->pipe &&
1123 update_planes & BIT(plane->id))
1124 plane->enable_flip_done(plane);
1125 }
1126}
1127
1128static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
1129 struct intel_crtc *crtc)
1130{
1131 const struct intel_crtc_state *crtc_state =
1132 intel_atomic_get_new_crtc_state(state, crtc);
1133 u8 update_planes = crtc_state->update_planes;
1134 const struct intel_plane_state __maybe_unused *plane_state;
1135 struct intel_plane *plane;
1136 int i;
1137
1138 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1139 if (plane->pipe == crtc->pipe &&
1140 update_planes & BIT(plane->id))
1141 plane->disable_flip_done(plane);
1142 }
1143}
1144
1145static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
1146 struct intel_crtc *crtc)
1147{
1148 const struct intel_crtc_state *old_crtc_state =
1149 intel_atomic_get_old_crtc_state(state, crtc);
1150 const struct intel_crtc_state *new_crtc_state =
1151 intel_atomic_get_new_crtc_state(state, crtc);
1152 u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &
1153 ~new_crtc_state->async_flip_planes;
1154 const struct intel_plane_state *old_plane_state;
1155 struct intel_plane *plane;
1156 bool need_vbl_wait = false;
1157 int i;
1158
1159 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1160 if (plane->need_async_flip_toggle_wa &&
1161 plane->pipe == crtc->pipe &&
1162 disable_async_flip_planes & BIT(plane->id)) {
1163 /*
1164 * Apart from the async flip bit we want to
1165 * preserve the old state for the plane.
1166 */
1167 intel_plane_async_flip(NULL, plane,
1168 crtc_state: old_crtc_state, plane_state: old_plane_state, async_flip: false);
1169 need_vbl_wait = true;
1170 }
1171 }
1172
1173 if (need_vbl_wait)
1174 intel_crtc_wait_for_next_vblank(crtc);
1175}
1176
1177static void intel_pre_plane_update(struct intel_atomic_state *state,
1178 struct intel_crtc *crtc)
1179{
1180 struct intel_display *display = to_intel_display(state);
1181 const struct intel_crtc_state *old_crtc_state =
1182 intel_atomic_get_old_crtc_state(state, crtc);
1183 const struct intel_crtc_state *new_crtc_state =
1184 intel_atomic_get_new_crtc_state(state, crtc);
1185 enum pipe pipe = crtc->pipe;
1186
1187 intel_alpm_pre_plane_update(state, crtc);
1188 intel_psr_pre_plane_update(state, crtc);
1189
1190 if (intel_crtc_vrr_disabling(state, crtc)) {
1191 intel_vrr_disable(old_crtc_state);
1192 intel_crtc_update_active_timings(crtc_state: old_crtc_state, vrr_enable: false);
1193 }
1194
1195 if (audio_disabling(old_crtc_state, new_crtc_state))
1196 intel_encoders_audio_disable(state, crtc);
1197
1198 intel_drrs_deactivate(crtc_state: old_crtc_state);
1199
1200 if (hsw_ips_pre_update(state, crtc))
1201 intel_crtc_wait_for_next_vblank(crtc);
1202
1203 if (intel_fbc_pre_update(state, crtc))
1204 intel_crtc_wait_for_next_vblank(crtc);
1205
1206 if (!needs_async_flip_vtd_wa(crtc_state: old_crtc_state) &&
1207 needs_async_flip_vtd_wa(crtc_state: new_crtc_state))
1208 intel_async_flip_vtd_wa(display, pipe, enable: true);
1209
1210 /* Display WA 827 */
1211 if (!needs_nv12_wa(crtc_state: old_crtc_state) &&
1212 needs_nv12_wa(crtc_state: new_crtc_state))
1213 skl_wa_827(display, pipe, enable: true);
1214
1215 /* Wa_2006604312:icl,ehl */
1216 if (!needs_scalerclk_wa(crtc_state: old_crtc_state) &&
1217 needs_scalerclk_wa(crtc_state: new_crtc_state))
1218 icl_wa_scalerclkgating(display, pipe, enable: true);
1219
1220 /* Wa_1604331009:icl,jsl,ehl */
1221 if (!needs_cursorclk_wa(crtc_state: old_crtc_state) &&
1222 needs_cursorclk_wa(crtc_state: new_crtc_state))
1223 icl_wa_cursorclkgating(display, pipe, enable: true);
1224
1225 /*
1226 * Vblank time updates from the shadow to live plane control register
1227 * are blocked if the memory self-refresh mode is active at that
1228 * moment. So to make sure the plane gets truly disabled, disable
1229 * first the self-refresh mode. The self-refresh enable bit in turn
1230 * will be checked/applied by the HW only at the next frame start
1231 * event which is after the vblank start event, so we need to have a
1232 * wait-for-vblank between disabling the plane and the pipe.
1233 */
1234 if (HAS_GMCH(display) && old_crtc_state->hw.active &&
1235 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(display, enable: false))
1236 intel_crtc_wait_for_next_vblank(crtc);
1237
1238 /*
1239 * IVB workaround: must disable low power watermarks for at least
1240 * one frame before enabling scaling. LP watermarks can be re-enabled
1241 * when scaling is disabled.
1242 *
1243 * WaCxSRDisabledForSpriteScaling:ivb
1244 */
1245 if (!HAS_GMCH(display) && old_crtc_state->hw.active &&
1246 new_crtc_state->disable_cxsr && ilk_disable_cxsr(display))
1247 intel_crtc_wait_for_next_vblank(crtc);
1248
1249 /*
1250 * If we're doing a modeset we don't need to do any
1251 * pre-vblank watermark programming here.
1252 */
1253 if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state)) {
1254 /*
1255 * For platforms that support atomic watermarks, program the
1256 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
1257 * will be the intermediate values that are safe for both pre- and
1258 * post- vblank; when vblank happens, the 'active' values will be set
1259 * to the final 'target' values and we'll do this again to get the
1260 * optimal watermarks. For gen9+ platforms, the values we program here
1261 * will be the final target values which will get automatically latched
1262 * at vblank time; no further programming will be necessary.
1263 *
1264 * If a platform hasn't been transitioned to atomic watermarks yet,
1265 * we'll continue to update watermarks the old way, if flags tell
1266 * us to.
1267 */
1268 if (!intel_initial_watermarks(state, crtc))
1269 if (new_crtc_state->update_wm_pre)
1270 intel_update_watermarks(display);
1271 }
1272
1273 /*
1274 * Gen2 reports pipe underruns whenever all planes are disabled.
1275 * So disable underrun reporting before all the planes get disabled.
1276 *
1277 * We do this after .initial_watermarks() so that we have a
1278 * chance of catching underruns with the intermediate watermarks
1279 * vs. the old plane configuration.
1280 */
1281 if (DISPLAY_VER(display) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1282 intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: false);
1283
1284 /*
1285 * WA for platforms where async address update enable bit
1286 * is double buffered and only latched at start of vblank.
1287 */
1288 if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)
1289 intel_crtc_async_flip_disable_wa(state, crtc);
1290}
1291
1292static void intel_crtc_disable_planes(struct intel_atomic_state *state,
1293 struct intel_crtc *crtc)
1294{
1295 struct intel_display *display = to_intel_display(state);
1296 const struct intel_crtc_state *new_crtc_state =
1297 intel_atomic_get_new_crtc_state(state, crtc);
1298 unsigned int update_mask = new_crtc_state->update_planes;
1299 const struct intel_plane_state *old_plane_state;
1300 struct intel_plane *plane;
1301 unsigned fb_bits = 0;
1302 int i;
1303
1304 intel_crtc_dpms_overlay_disable(crtc);
1305
1306 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1307 if (crtc->pipe != plane->pipe ||
1308 !(update_mask & BIT(plane->id)))
1309 continue;
1310
1311 intel_plane_disable_arm(NULL, plane, crtc_state: new_crtc_state);
1312
1313 if (old_plane_state->uapi.visible)
1314 fb_bits |= plane->frontbuffer_bit;
1315 }
1316
1317 intel_frontbuffer_flip(display, frontbuffer_bits: fb_bits);
1318}
1319
1320static void intel_encoders_update_prepare(struct intel_atomic_state *state)
1321{
1322 struct intel_display *display = to_intel_display(state);
1323 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1324 struct intel_crtc *crtc;
1325 int i;
1326
1327 /*
1328 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1329 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1330 */
1331 if (display->dpll.mgr) {
1332 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1333 if (intel_crtc_needs_modeset(crtc_state: new_crtc_state))
1334 continue;
1335
1336 new_crtc_state->intel_dpll = old_crtc_state->intel_dpll;
1337 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
1338 }
1339 }
1340}
1341
1342static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
1343 struct intel_crtc *crtc)
1344{
1345 const struct intel_crtc_state *crtc_state =
1346 intel_atomic_get_new_crtc_state(state, crtc);
1347 const struct drm_connector_state *conn_state;
1348 struct drm_connector *conn;
1349 int i;
1350
1351 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1352 struct intel_encoder *encoder =
1353 to_intel_encoder(conn_state->best_encoder);
1354
1355 if (conn_state->crtc != &crtc->base)
1356 continue;
1357
1358 if (encoder->pre_pll_enable)
1359 encoder->pre_pll_enable(state, encoder,
1360 crtc_state, conn_state);
1361 }
1362}
1363
1364static void intel_encoders_pre_enable(struct intel_atomic_state *state,
1365 struct intel_crtc *crtc)
1366{
1367 const struct intel_crtc_state *crtc_state =
1368 intel_atomic_get_new_crtc_state(state, crtc);
1369 const struct drm_connector_state *conn_state;
1370 struct drm_connector *conn;
1371 int i;
1372
1373 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1374 struct intel_encoder *encoder =
1375 to_intel_encoder(conn_state->best_encoder);
1376
1377 if (conn_state->crtc != &crtc->base)
1378 continue;
1379
1380 if (encoder->pre_enable)
1381 encoder->pre_enable(state, encoder,
1382 crtc_state, conn_state);
1383 }
1384}
1385
1386static void intel_encoders_enable(struct intel_atomic_state *state,
1387 struct intel_crtc *crtc)
1388{
1389 const struct intel_crtc_state *crtc_state =
1390 intel_atomic_get_new_crtc_state(state, crtc);
1391 const struct drm_connector_state *conn_state;
1392 struct drm_connector *conn;
1393 int i;
1394
1395 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1396 struct intel_encoder *encoder =
1397 to_intel_encoder(conn_state->best_encoder);
1398
1399 if (conn_state->crtc != &crtc->base)
1400 continue;
1401
1402 if (encoder->enable)
1403 encoder->enable(state, encoder,
1404 crtc_state, conn_state);
1405 intel_opregion_notify_encoder(encoder, enable: true);
1406 }
1407}
1408
1409static void intel_encoders_disable(struct intel_atomic_state *state,
1410 struct intel_crtc *crtc)
1411{
1412 const struct intel_crtc_state *old_crtc_state =
1413 intel_atomic_get_old_crtc_state(state, crtc);
1414 const struct drm_connector_state *old_conn_state;
1415 struct drm_connector *conn;
1416 int i;
1417
1418 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1419 struct intel_encoder *encoder =
1420 to_intel_encoder(old_conn_state->best_encoder);
1421
1422 if (old_conn_state->crtc != &crtc->base)
1423 continue;
1424
1425 intel_opregion_notify_encoder(encoder, enable: false);
1426 if (encoder->disable)
1427 encoder->disable(state, encoder,
1428 old_crtc_state, old_conn_state);
1429 }
1430}
1431
1432static void intel_encoders_post_disable(struct intel_atomic_state *state,
1433 struct intel_crtc *crtc)
1434{
1435 const struct intel_crtc_state *old_crtc_state =
1436 intel_atomic_get_old_crtc_state(state, crtc);
1437 const struct drm_connector_state *old_conn_state;
1438 struct drm_connector *conn;
1439 int i;
1440
1441 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1442 struct intel_encoder *encoder =
1443 to_intel_encoder(old_conn_state->best_encoder);
1444
1445 if (old_conn_state->crtc != &crtc->base)
1446 continue;
1447
1448 if (encoder->post_disable)
1449 encoder->post_disable(state, encoder,
1450 old_crtc_state, old_conn_state);
1451 }
1452}
1453
1454static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
1455 struct intel_crtc *crtc)
1456{
1457 const struct intel_crtc_state *old_crtc_state =
1458 intel_atomic_get_old_crtc_state(state, crtc);
1459 const struct drm_connector_state *old_conn_state;
1460 struct drm_connector *conn;
1461 int i;
1462
1463 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1464 struct intel_encoder *encoder =
1465 to_intel_encoder(old_conn_state->best_encoder);
1466
1467 if (old_conn_state->crtc != &crtc->base)
1468 continue;
1469
1470 if (encoder->post_pll_disable)
1471 encoder->post_pll_disable(state, encoder,
1472 old_crtc_state, old_conn_state);
1473 }
1474}
1475
1476static void intel_encoders_update_pipe(struct intel_atomic_state *state,
1477 struct intel_crtc *crtc)
1478{
1479 const struct intel_crtc_state *crtc_state =
1480 intel_atomic_get_new_crtc_state(state, crtc);
1481 const struct drm_connector_state *conn_state;
1482 struct drm_connector *conn;
1483 int i;
1484
1485 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1486 struct intel_encoder *encoder =
1487 to_intel_encoder(conn_state->best_encoder);
1488
1489 if (conn_state->crtc != &crtc->base)
1490 continue;
1491
1492 if (encoder->update_pipe)
1493 encoder->update_pipe(state, encoder,
1494 crtc_state, conn_state);
1495 }
1496}
1497
1498static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1499{
1500 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1501 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1502
1503 if (crtc_state->has_pch_encoder) {
1504 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1505 m_n: &crtc_state->fdi_m_n);
1506 } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1507 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1508 m_n: &crtc_state->dp_m_n);
1509 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1510 m_n: &crtc_state->dp_m2_n2);
1511 }
1512
1513 intel_set_transcoder_timings(crtc_state);
1514
1515 ilk_set_pipeconf(crtc_state);
1516}
1517
1518static void ilk_crtc_enable(struct intel_atomic_state *state,
1519 struct intel_crtc *crtc)
1520{
1521 struct intel_display *display = to_intel_display(crtc);
1522 const struct intel_crtc_state *new_crtc_state =
1523 intel_atomic_get_new_crtc_state(state, crtc);
1524 enum pipe pipe = crtc->pipe;
1525
1526 if (drm_WARN_ON(display->drm, crtc->active))
1527 return;
1528
1529 /*
1530 * Sometimes spurious CPU pipe underruns happen during FDI
1531 * training, at least with VGA+HDMI cloning. Suppress them.
1532 *
1533 * On ILK we get an occasional spurious CPU pipe underruns
1534 * between eDP port A enable and vdd enable. Also PCH port
1535 * enable seems to result in the occasional CPU pipe underrun.
1536 *
1537 * Spurious PCH underruns also occur during PCH enabling.
1538 */
1539 intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: false);
1540 intel_set_pch_fifo_underrun_reporting(display, pch_transcoder: pipe, enable: false);
1541
1542 ilk_configure_cpu_transcoder(crtc_state: new_crtc_state);
1543
1544 intel_set_pipe_src_size(crtc_state: new_crtc_state);
1545
1546 crtc->active = true;
1547
1548 intel_encoders_pre_enable(state, crtc);
1549
1550 if (new_crtc_state->has_pch_encoder) {
1551 ilk_pch_pre_enable(state, crtc);
1552 } else {
1553 assert_fdi_tx_disabled(display, pipe);
1554 assert_fdi_rx_disabled(display, pipe);
1555 }
1556
1557 ilk_pfit_enable(crtc_state: new_crtc_state);
1558
1559 /*
1560 * On ILK+ LUT must be loaded before the pipe is running but with
1561 * clocks enabled
1562 */
1563 intel_color_modeset(crtc_state: new_crtc_state);
1564
1565 intel_initial_watermarks(state, crtc);
1566 intel_enable_transcoder(new_crtc_state);
1567
1568 if (new_crtc_state->has_pch_encoder)
1569 ilk_pch_enable(state, crtc);
1570
1571 intel_crtc_vblank_on(crtc_state: new_crtc_state);
1572
1573 intel_encoders_enable(state, crtc);
1574
1575 if (HAS_PCH_CPT(display))
1576 intel_wait_for_pipe_scanline_moving(crtc);
1577
1578 /*
1579 * Must wait for vblank to avoid spurious PCH FIFO underruns.
1580 * And a second vblank wait is needed at least on ILK with
1581 * some interlaced HDMI modes. Let's do the double wait always
1582 * in case there are more corner cases we don't know about.
1583 */
1584 if (new_crtc_state->has_pch_encoder) {
1585 intel_crtc_wait_for_next_vblank(crtc);
1586 intel_crtc_wait_for_next_vblank(crtc);
1587 }
1588 intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: true);
1589 intel_set_pch_fifo_underrun_reporting(display, pch_transcoder: pipe, enable: true);
1590}
1591
1592/* Display WA #1180: WaDisableScalarClockGating: glk */
1593static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_state)
1594{
1595 struct intel_display *display = to_intel_display(crtc_state);
1596
1597 return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled;
1598}
1599
1600static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable)
1601{
1602 struct intel_display *display = to_intel_display(crtc);
1603 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
1604
1605 intel_de_rmw(display, CLKGATE_DIS_PSL(crtc->pipe),
1606 clear: mask, set: enable ? mask : 0);
1607}
1608
1609static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
1610{
1611 struct intel_display *display = to_intel_display(crtc_state);
1612 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1613
1614 intel_de_write(display, WM_LINETIME(crtc->pipe),
1615 HSW_LINETIME(crtc_state->linetime) |
1616 HSW_IPS_LINETIME(crtc_state->ips_linetime));
1617}
1618
1619static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
1620{
1621 struct intel_display *display = to_intel_display(crtc_state);
1622
1623 intel_de_rmw(display, CHICKEN_TRANS(display, crtc_state->cpu_transcoder),
1624 HSW_FRAME_START_DELAY_MASK,
1625 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));
1626}
1627
1628static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1629{
1630 struct intel_display *display = to_intel_display(crtc_state);
1631 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1632 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1633
1634 if (crtc_state->has_pch_encoder) {
1635 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1636 m_n: &crtc_state->fdi_m_n);
1637 } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1638 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1639 m_n: &crtc_state->dp_m_n);
1640 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1641 m_n: &crtc_state->dp_m2_n2);
1642 }
1643
1644 intel_set_transcoder_timings(crtc_state);
1645 if (HAS_VRR(display))
1646 intel_vrr_set_transcoder_timings(crtc_state);
1647
1648 if (cpu_transcoder != TRANSCODER_EDP)
1649 intel_de_write(display, TRANS_MULT(display, cpu_transcoder),
1650 val: crtc_state->pixel_multiplier - 1);
1651
1652 hsw_set_frame_start_delay(crtc_state);
1653
1654 hsw_set_transconf(crtc_state);
1655}
1656
1657static void hsw_crtc_enable(struct intel_atomic_state *state,
1658 struct intel_crtc *crtc)
1659{
1660 struct intel_display *display = to_intel_display(state);
1661 const struct intel_crtc_state *new_crtc_state =
1662 intel_atomic_get_new_crtc_state(state, crtc);
1663 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1664 struct intel_crtc *pipe_crtc;
1665 int i;
1666
1667 if (drm_WARN_ON(display->drm, crtc->active))
1668 return;
1669 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1670 const struct intel_crtc_state *new_pipe_crtc_state =
1671 intel_atomic_get_new_crtc_state(state, crtc: pipe_crtc);
1672
1673 intel_dmc_enable_pipe(crtc_state: new_pipe_crtc_state);
1674 }
1675
1676 intel_encoders_pre_pll_enable(state, crtc);
1677
1678 if (new_crtc_state->intel_dpll)
1679 intel_dpll_enable(crtc_state: new_crtc_state);
1680
1681 intel_encoders_pre_enable(state, crtc);
1682
1683 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1684 const struct intel_crtc_state *pipe_crtc_state =
1685 intel_atomic_get_new_crtc_state(state, crtc: pipe_crtc);
1686
1687 intel_dsc_enable(crtc_state: pipe_crtc_state);
1688
1689 if (HAS_UNCOMPRESSED_JOINER(display))
1690 intel_uncompressed_joiner_enable(crtc_state: pipe_crtc_state);
1691
1692 intel_set_pipe_src_size(crtc_state: pipe_crtc_state);
1693
1694 if (DISPLAY_VER(display) >= 9 || display->platform.broadwell)
1695 bdw_set_pipe_misc(NULL, crtc_state: pipe_crtc_state);
1696 }
1697
1698 if (!transcoder_is_dsi(transcoder: cpu_transcoder))
1699 hsw_configure_cpu_transcoder(crtc_state: new_crtc_state);
1700
1701 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1702 const struct intel_crtc_state *pipe_crtc_state =
1703 intel_atomic_get_new_crtc_state(state, crtc: pipe_crtc);
1704
1705 pipe_crtc->active = true;
1706
1707 if (glk_need_scaler_clock_gating_wa(crtc_state: pipe_crtc_state))
1708 glk_pipe_scaler_clock_gating_wa(crtc: pipe_crtc, enable: true);
1709
1710 if (DISPLAY_VER(display) >= 9)
1711 skl_pfit_enable(crtc_state: pipe_crtc_state);
1712 else
1713 ilk_pfit_enable(crtc_state: pipe_crtc_state);
1714
1715 /*
1716 * On ILK+ LUT must be loaded before the pipe is running but with
1717 * clocks enabled
1718 */
1719 intel_color_modeset(crtc_state: pipe_crtc_state);
1720
1721 hsw_set_linetime_wm(crtc_state: pipe_crtc_state);
1722
1723 if (DISPLAY_VER(display) >= 11)
1724 icl_set_pipe_chicken(crtc_state: pipe_crtc_state);
1725
1726 intel_initial_watermarks(state, crtc: pipe_crtc);
1727 }
1728
1729 intel_encoders_enable(state, crtc);
1730
1731 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1732 const struct intel_crtc_state *pipe_crtc_state =
1733 intel_atomic_get_new_crtc_state(state, crtc: pipe_crtc);
1734 enum pipe hsw_workaround_pipe;
1735
1736 if (glk_need_scaler_clock_gating_wa(crtc_state: pipe_crtc_state)) {
1737 intel_crtc_wait_for_next_vblank(crtc: pipe_crtc);
1738 glk_pipe_scaler_clock_gating_wa(crtc: pipe_crtc, enable: false);
1739 }
1740
1741 /*
1742 * If we change the relative order between pipe/planes
1743 * enabling, we need to change the workaround.
1744 */
1745 hsw_workaround_pipe = pipe_crtc_state->hsw_workaround_pipe;
1746 if (display->platform.haswell && hsw_workaround_pipe != INVALID_PIPE) {
1747 struct intel_crtc *wa_crtc =
1748 intel_crtc_for_pipe(display, pipe: hsw_workaround_pipe);
1749
1750 intel_crtc_wait_for_next_vblank(crtc: wa_crtc);
1751 intel_crtc_wait_for_next_vblank(crtc: wa_crtc);
1752 }
1753 }
1754}
1755
1756static void ilk_crtc_disable(struct intel_atomic_state *state,
1757 struct intel_crtc *crtc)
1758{
1759 struct intel_display *display = to_intel_display(crtc);
1760 const struct intel_crtc_state *old_crtc_state =
1761 intel_atomic_get_old_crtc_state(state, crtc);
1762 enum pipe pipe = crtc->pipe;
1763
1764 /*
1765 * Sometimes spurious CPU pipe underruns happen when the
1766 * pipe is already disabled, but FDI RX/TX is still enabled.
1767 * Happens at least with VGA+HDMI cloning. Suppress them.
1768 */
1769 intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: false);
1770 intel_set_pch_fifo_underrun_reporting(display, pch_transcoder: pipe, enable: false);
1771
1772 intel_encoders_disable(state, crtc);
1773
1774 intel_crtc_vblank_off(crtc_state: old_crtc_state);
1775
1776 intel_disable_transcoder(old_crtc_state);
1777
1778 ilk_pfit_disable(old_crtc_state);
1779
1780 if (old_crtc_state->has_pch_encoder)
1781 ilk_pch_disable(state, crtc);
1782
1783 intel_encoders_post_disable(state, crtc);
1784
1785 if (old_crtc_state->has_pch_encoder)
1786 ilk_pch_post_disable(state, crtc);
1787
1788 intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: true);
1789 intel_set_pch_fifo_underrun_reporting(display, pch_transcoder: pipe, enable: true);
1790}
1791
1792static void hsw_crtc_disable(struct intel_atomic_state *state,
1793 struct intel_crtc *crtc)
1794{
1795 struct intel_display *display = to_intel_display(state);
1796 const struct intel_crtc_state *old_crtc_state =
1797 intel_atomic_get_old_crtc_state(state, crtc);
1798 struct intel_crtc *pipe_crtc;
1799 int i;
1800
1801 /*
1802 * FIXME collapse everything to one hook.
1803 * Need care with mst->ddi interactions.
1804 */
1805 intel_encoders_disable(state, crtc);
1806 intel_encoders_post_disable(state, crtc);
1807
1808 intel_dpll_disable(crtc_state: old_crtc_state);
1809
1810 intel_encoders_post_pll_disable(state, crtc);
1811
1812 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
1813 const struct intel_crtc_state *old_pipe_crtc_state =
1814 intel_atomic_get_old_crtc_state(state, crtc: pipe_crtc);
1815
1816 intel_dmc_disable_pipe(crtc_state: old_pipe_crtc_state);
1817 }
1818}
1819
1820/* Prefer intel_encoder_is_combo() */
1821bool intel_phy_is_combo(struct intel_display *display, enum phy phy)
1822{
1823 if (phy == PHY_NONE)
1824 return false;
1825 else if (display->platform.alderlake_s)
1826 return phy <= PHY_E;
1827 else if (display->platform.dg1 || display->platform.rocketlake)
1828 return phy <= PHY_D;
1829 else if (display->platform.jasperlake || display->platform.elkhartlake)
1830 return phy <= PHY_C;
1831 else if (display->platform.alderlake_p || IS_DISPLAY_VER(display, 11, 12))
1832 return phy <= PHY_B;
1833 else
1834 /*
1835 * DG2 outputs labelled as "combo PHY" in the bspec use
1836 * SNPS PHYs with completely different programming,
1837 * hence we always return false here.
1838 */
1839 return false;
1840}
1841
1842/* Prefer intel_encoder_is_tc() */
1843bool intel_phy_is_tc(struct intel_display *display, enum phy phy)
1844{
1845 /*
1846 * Discrete GPU phy's are not attached to FIA's to support TC
1847 * subsystem Legacy or non-legacy, and only support native DP/HDMI
1848 */
1849 if (display->platform.dgfx)
1850 return false;
1851
1852 if (DISPLAY_VER(display) >= 13)
1853 return phy >= PHY_F && phy <= PHY_I;
1854 else if (display->platform.tigerlake)
1855 return phy >= PHY_D && phy <= PHY_I;
1856 else if (display->platform.icelake)
1857 return phy >= PHY_C && phy <= PHY_F;
1858
1859 return false;
1860}
1861
1862/* Prefer intel_encoder_is_snps() */
1863bool intel_phy_is_snps(struct intel_display *display, enum phy phy)
1864{
1865 /*
1866 * For DG2, and for DG2 only, all four "combo" ports and the TC1 port
1867 * (PHY E) use Synopsis PHYs. See intel_phy_is_tc().
1868 */
1869 return display->platform.dg2 && phy > PHY_NONE && phy <= PHY_E;
1870}
1871
1872/* Prefer intel_encoder_to_phy() */
1873enum phy intel_port_to_phy(struct intel_display *display, enum port port)
1874{
1875 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD)
1876 return PHY_D + port - PORT_D_XELPD;
1877 else if (DISPLAY_VER(display) >= 13 && port >= PORT_TC1)
1878 return PHY_F + port - PORT_TC1;
1879 else if (display->platform.alderlake_s && port >= PORT_TC1)
1880 return PHY_B + port - PORT_TC1;
1881 else if ((display->platform.dg1 || display->platform.rocketlake) && port >= PORT_TC1)
1882 return PHY_C + port - PORT_TC1;
1883 else if ((display->platform.jasperlake || display->platform.elkhartlake) &&
1884 port == PORT_D)
1885 return PHY_A;
1886
1887 return PHY_A + port - PORT_A;
1888}
1889
1890/* Prefer intel_encoder_to_tc() */
1891enum tc_port intel_port_to_tc(struct intel_display *display, enum port port)
1892{
1893 if (!intel_phy_is_tc(display, phy: intel_port_to_phy(display, port)))
1894 return TC_PORT_NONE;
1895
1896 if (DISPLAY_VER(display) >= 12)
1897 return TC_PORT_1 + port - PORT_TC1;
1898 else
1899 return TC_PORT_1 + port - PORT_C;
1900}
1901
1902enum phy intel_encoder_to_phy(struct intel_encoder *encoder)
1903{
1904 struct intel_display *display = to_intel_display(encoder);
1905
1906 return intel_port_to_phy(display, port: encoder->port);
1907}
1908
1909bool intel_encoder_is_combo(struct intel_encoder *encoder)
1910{
1911 struct intel_display *display = to_intel_display(encoder);
1912
1913 return intel_phy_is_combo(display, phy: intel_encoder_to_phy(encoder));
1914}
1915
1916bool intel_encoder_is_snps(struct intel_encoder *encoder)
1917{
1918 struct intel_display *display = to_intel_display(encoder);
1919
1920 return intel_phy_is_snps(display, phy: intel_encoder_to_phy(encoder));
1921}
1922
1923bool intel_encoder_is_tc(struct intel_encoder *encoder)
1924{
1925 struct intel_display *display = to_intel_display(encoder);
1926
1927 return intel_phy_is_tc(display, phy: intel_encoder_to_phy(encoder));
1928}
1929
1930enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder)
1931{
1932 struct intel_display *display = to_intel_display(encoder);
1933
1934 return intel_port_to_tc(display, port: encoder->port);
1935}
1936
1937enum intel_display_power_domain
1938intel_aux_power_domain(struct intel_digital_port *dig_port)
1939{
1940 struct intel_display *display = to_intel_display(dig_port);
1941
1942 if (intel_tc_port_in_tbt_alt_mode(dig_port))
1943 return intel_display_power_tbt_aux_domain(display, aux_ch: dig_port->aux_ch);
1944
1945 return intel_display_power_legacy_aux_domain(display, aux_ch: dig_port->aux_ch);
1946}
1947
1948static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1949 struct intel_power_domain_mask *mask)
1950{
1951 struct intel_display *display = to_intel_display(crtc_state);
1952 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1953 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1954 struct drm_encoder *encoder;
1955 enum pipe pipe = crtc->pipe;
1956
1957 bitmap_zero(dst: mask->bits, nbits: POWER_DOMAIN_NUM);
1958
1959 if (!crtc_state->hw.active)
1960 return;
1961
1962 set_bit(POWER_DOMAIN_PIPE(pipe), addr: mask->bits);
1963 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), addr: mask->bits);
1964 if (crtc_state->pch_pfit.enabled ||
1965 crtc_state->pch_pfit.force_thru)
1966 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), addr: mask->bits);
1967
1968 drm_for_each_encoder_mask(encoder, display->drm,
1969 crtc_state->uapi.encoder_mask) {
1970 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1971
1972 set_bit(nr: intel_encoder->power_domain, addr: mask->bits);
1973 }
1974
1975 if (HAS_DDI(display) && crtc_state->has_audio)
1976 set_bit(nr: POWER_DOMAIN_AUDIO_MMIO, addr: mask->bits);
1977
1978 if (crtc_state->intel_dpll)
1979 set_bit(nr: POWER_DOMAIN_DISPLAY_CORE, addr: mask->bits);
1980
1981 if (crtc_state->dsc.compression_enable)
1982 set_bit(nr: intel_dsc_power_domain(crtc, cpu_transcoder), addr: mask->bits);
1983}
1984
1985void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1986 struct intel_power_domain_mask *old_domains)
1987{
1988 struct intel_display *display = to_intel_display(crtc_state);
1989 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1990 enum intel_display_power_domain domain;
1991 struct intel_power_domain_mask domains, new_domains;
1992
1993 get_crtc_power_domains(crtc_state, mask: &domains);
1994
1995 bitmap_andnot(dst: new_domains.bits,
1996 src1: domains.bits,
1997 src2: crtc->enabled_power_domains.mask.bits,
1998 nbits: POWER_DOMAIN_NUM);
1999 bitmap_andnot(dst: old_domains->bits,
2000 src1: crtc->enabled_power_domains.mask.bits,
2001 src2: domains.bits,
2002 nbits: POWER_DOMAIN_NUM);
2003
2004 for_each_power_domain(domain, &new_domains)
2005 intel_display_power_get_in_set(display,
2006 power_domain_set: &crtc->enabled_power_domains,
2007 domain);
2008}
2009
2010void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
2011 struct intel_power_domain_mask *domains)
2012{
2013 struct intel_display *display = to_intel_display(crtc);
2014
2015 intel_display_power_put_mask_in_set(display,
2016 power_domain_set: &crtc->enabled_power_domains,
2017 mask: domains);
2018}
2019
2020static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
2021{
2022 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2023 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2024
2025 if (intel_crtc_has_dp_encoder(crtc_state)) {
2026 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
2027 m_n: &crtc_state->dp_m_n);
2028 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
2029 m_n: &crtc_state->dp_m2_n2);
2030 }
2031
2032 intel_set_transcoder_timings(crtc_state);
2033
2034 i9xx_set_pipeconf(crtc_state);
2035}
2036
2037static void valleyview_crtc_enable(struct intel_atomic_state *state,
2038 struct intel_crtc *crtc)
2039{
2040 struct intel_display *display = to_intel_display(crtc);
2041 const struct intel_crtc_state *new_crtc_state =
2042 intel_atomic_get_new_crtc_state(state, crtc);
2043 enum pipe pipe = crtc->pipe;
2044
2045 if (drm_WARN_ON(display->drm, crtc->active))
2046 return;
2047
2048 i9xx_configure_cpu_transcoder(crtc_state: new_crtc_state);
2049
2050 intel_set_pipe_src_size(crtc_state: new_crtc_state);
2051
2052 intel_de_write(display, VLV_PIPE_MSA_MISC(display, pipe), val: 0);
2053
2054 if (display->platform.cherryview && pipe == PIPE_B) {
2055 intel_de_write(display, CHV_BLEND(display, pipe),
2056 CHV_BLEND_LEGACY);
2057 intel_de_write(display, CHV_CANVAS(display, pipe), val: 0);
2058 }
2059
2060 crtc->active = true;
2061
2062 intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: true);
2063
2064 intel_encoders_pre_pll_enable(state, crtc);
2065
2066 if (display->platform.cherryview)
2067 chv_enable_pll(crtc_state: new_crtc_state);
2068 else
2069 vlv_enable_pll(crtc_state: new_crtc_state);
2070
2071 intel_encoders_pre_enable(state, crtc);
2072
2073 i9xx_pfit_enable(crtc_state: new_crtc_state);
2074
2075 intel_color_modeset(crtc_state: new_crtc_state);
2076
2077 intel_initial_watermarks(state, crtc);
2078 intel_enable_transcoder(new_crtc_state);
2079
2080 intel_crtc_vblank_on(crtc_state: new_crtc_state);
2081
2082 intel_encoders_enable(state, crtc);
2083}
2084
2085static void i9xx_crtc_enable(struct intel_atomic_state *state,
2086 struct intel_crtc *crtc)
2087{
2088 struct intel_display *display = to_intel_display(crtc);
2089 const struct intel_crtc_state *new_crtc_state =
2090 intel_atomic_get_new_crtc_state(state, crtc);
2091 enum pipe pipe = crtc->pipe;
2092
2093 if (drm_WARN_ON(display->drm, crtc->active))
2094 return;
2095
2096 i9xx_configure_cpu_transcoder(crtc_state: new_crtc_state);
2097
2098 intel_set_pipe_src_size(crtc_state: new_crtc_state);
2099
2100 crtc->active = true;
2101
2102 if (DISPLAY_VER(display) != 2)
2103 intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: true);
2104
2105 intel_encoders_pre_enable(state, crtc);
2106
2107 i9xx_enable_pll(crtc_state: new_crtc_state);
2108
2109 i9xx_pfit_enable(crtc_state: new_crtc_state);
2110
2111 intel_color_modeset(crtc_state: new_crtc_state);
2112
2113 if (!intel_initial_watermarks(state, crtc))
2114 intel_update_watermarks(display);
2115 intel_enable_transcoder(new_crtc_state);
2116
2117 intel_crtc_vblank_on(crtc_state: new_crtc_state);
2118
2119 intel_encoders_enable(state, crtc);
2120
2121 /* prevents spurious underruns */
2122 if (DISPLAY_VER(display) == 2)
2123 intel_crtc_wait_for_next_vblank(crtc);
2124}
2125
2126static void i9xx_crtc_disable(struct intel_atomic_state *state,
2127 struct intel_crtc *crtc)
2128{
2129 struct intel_display *display = to_intel_display(state);
2130 struct intel_crtc_state *old_crtc_state =
2131 intel_atomic_get_old_crtc_state(state, crtc);
2132 enum pipe pipe = crtc->pipe;
2133
2134 /*
2135 * On gen2 planes are double buffered but the pipe isn't, so we must
2136 * wait for planes to fully turn off before disabling the pipe.
2137 */
2138 if (DISPLAY_VER(display) == 2)
2139 intel_crtc_wait_for_next_vblank(crtc);
2140
2141 intel_encoders_disable(state, crtc);
2142
2143 intel_crtc_vblank_off(crtc_state: old_crtc_state);
2144
2145 intel_disable_transcoder(old_crtc_state);
2146
2147 i9xx_pfit_disable(old_crtc_state);
2148
2149 intel_encoders_post_disable(state, crtc);
2150
2151 if (!intel_crtc_has_type(crtc_state: old_crtc_state, type: INTEL_OUTPUT_DSI)) {
2152 if (display->platform.cherryview)
2153 chv_disable_pll(display, pipe);
2154 else if (display->platform.valleyview)
2155 vlv_disable_pll(display, pipe);
2156 else
2157 i9xx_disable_pll(crtc_state: old_crtc_state);
2158 }
2159
2160 intel_encoders_post_pll_disable(state, crtc);
2161
2162 if (DISPLAY_VER(display) != 2)
2163 intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: false);
2164
2165 if (!display->funcs.wm->initial_watermarks)
2166 intel_update_watermarks(display);
2167
2168 /* clock the pipe down to 640x480@60 to potentially save power */
2169 if (display->platform.i830)
2170 i830_enable_pipe(display, pipe);
2171}
2172
2173void intel_encoder_destroy(struct drm_encoder *encoder)
2174{
2175 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2176
2177 drm_encoder_cleanup(encoder);
2178 kfree(objp: intel_encoder);
2179}
2180
2181static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
2182{
2183 struct intel_display *display = to_intel_display(crtc);
2184
2185 /* GDG double wide on either pipe, otherwise pipe A only */
2186 return HAS_DOUBLE_WIDE(display) &&
2187 (crtc->pipe == PIPE_A || display->platform.i915g);
2188}
2189
2190static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
2191{
2192 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
2193 struct drm_rect src;
2194
2195 /*
2196 * We only use IF-ID interlacing. If we ever use
2197 * PF-ID we'll need to adjust the pixel_rate here.
2198 */
2199
2200 if (!crtc_state->pch_pfit.enabled)
2201 return pixel_rate;
2202
2203 drm_rect_init(r: &src, x: 0, y: 0,
2204 width: drm_rect_width(r: &crtc_state->pipe_src) << 16,
2205 height: drm_rect_height(r: &crtc_state->pipe_src) << 16);
2206
2207 return intel_adjusted_rate(src: &src, dst: &crtc_state->pch_pfit.dst,
2208 rate: pixel_rate);
2209}
2210
2211static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
2212 const struct drm_display_mode *timings)
2213{
2214 mode->hdisplay = timings->crtc_hdisplay;
2215 mode->htotal = timings->crtc_htotal;
2216 mode->hsync_start = timings->crtc_hsync_start;
2217 mode->hsync_end = timings->crtc_hsync_end;
2218
2219 mode->vdisplay = timings->crtc_vdisplay;
2220 mode->vtotal = timings->crtc_vtotal;
2221 mode->vsync_start = timings->crtc_vsync_start;
2222 mode->vsync_end = timings->crtc_vsync_end;
2223
2224 mode->flags = timings->flags;
2225 mode->type = DRM_MODE_TYPE_DRIVER;
2226
2227 mode->clock = timings->crtc_clock;
2228
2229 drm_mode_set_name(mode);
2230}
2231
2232static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
2233{
2234 struct intel_display *display = to_intel_display(crtc_state);
2235
2236 if (HAS_GMCH(display))
2237 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
2238 crtc_state->pixel_rate =
2239 crtc_state->hw.pipe_mode.crtc_clock;
2240 else
2241 crtc_state->pixel_rate =
2242 ilk_pipe_pixel_rate(crtc_state);
2243}
2244
2245static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state,
2246 struct drm_display_mode *mode)
2247{
2248 int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
2249
2250 if (num_pipes == 1)
2251 return;
2252
2253 mode->crtc_clock /= num_pipes;
2254 mode->crtc_hdisplay /= num_pipes;
2255 mode->crtc_hblank_start /= num_pipes;
2256 mode->crtc_hblank_end /= num_pipes;
2257 mode->crtc_hsync_start /= num_pipes;
2258 mode->crtc_hsync_end /= num_pipes;
2259 mode->crtc_htotal /= num_pipes;
2260}
2261
2262static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
2263 struct drm_display_mode *mode)
2264{
2265 int overlap = crtc_state->splitter.pixel_overlap;
2266 int n = crtc_state->splitter.link_count;
2267
2268 if (!crtc_state->splitter.enable)
2269 return;
2270
2271 /*
2272 * eDP MSO uses segment timings from EDID for transcoder
2273 * timings, but full mode for everything else.
2274 *
2275 * h_full = (h_segment - pixel_overlap) * link_count
2276 */
2277 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
2278 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
2279 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
2280 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
2281 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
2282 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
2283 mode->crtc_clock *= n;
2284}
2285
2286static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
2287{
2288 struct drm_display_mode *mode = &crtc_state->hw.mode;
2289 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2290 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2291
2292 /*
2293 * Start with the adjusted_mode crtc timings, which
2294 * have been filled with the transcoder timings.
2295 */
2296 drm_mode_copy(dst: pipe_mode, src: adjusted_mode);
2297
2298 /* Expand MSO per-segment transcoder timings to full */
2299 intel_splitter_adjust_timings(crtc_state, mode: pipe_mode);
2300
2301 /*
2302 * We want the full numbers in adjusted_mode normal timings,
2303 * adjusted_mode crtc timings are left with the raw transcoder
2304 * timings.
2305 */
2306 intel_mode_from_crtc_timings(mode: adjusted_mode, timings: pipe_mode);
2307
2308 /* Populate the "user" mode with full numbers */
2309 drm_mode_copy(dst: mode, src: pipe_mode);
2310 intel_mode_from_crtc_timings(mode, timings: mode);
2311 mode->hdisplay = drm_rect_width(r: &crtc_state->pipe_src) *
2312 intel_crtc_num_joined_pipes(crtc_state);
2313 mode->vdisplay = drm_rect_height(r: &crtc_state->pipe_src);
2314
2315 /* Derive per-pipe timings in case joiner is used */
2316 intel_joiner_adjust_timings(crtc_state, mode: pipe_mode);
2317 intel_mode_from_crtc_timings(mode: pipe_mode, timings: pipe_mode);
2318
2319 intel_crtc_compute_pixel_rate(crtc_state);
2320}
2321
2322void intel_encoder_get_config(struct intel_encoder *encoder,
2323 struct intel_crtc_state *crtc_state)
2324{
2325 encoder->get_config(encoder, crtc_state);
2326
2327 intel_crtc_readout_derived_state(crtc_state);
2328}
2329
2330static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
2331{
2332 int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
2333 int width, height;
2334
2335 if (num_pipes == 1)
2336 return;
2337
2338 width = drm_rect_width(r: &crtc_state->pipe_src);
2339 height = drm_rect_height(r: &crtc_state->pipe_src);
2340
2341 drm_rect_init(r: &crtc_state->pipe_src, x: 0, y: 0,
2342 width: width / num_pipes, height);
2343}
2344
2345static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
2346{
2347 struct intel_display *display = to_intel_display(crtc_state);
2348 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2349
2350 intel_joiner_compute_pipe_src(crtc_state);
2351
2352 /*
2353 * Pipe horizontal size must be even in:
2354 * - DVO ganged mode
2355 * - LVDS dual channel mode
2356 * - Double wide pipe
2357 */
2358 if (drm_rect_width(r: &crtc_state->pipe_src) & 1) {
2359 if (crtc_state->double_wide) {
2360 drm_dbg_kms(display->drm,
2361 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2362 crtc->base.base.id, crtc->base.name);
2363 return -EINVAL;
2364 }
2365
2366 if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_LVDS) &&
2367 intel_is_dual_link_lvds(display)) {
2368 drm_dbg_kms(display->drm,
2369 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2370 crtc->base.base.id, crtc->base.name);
2371 return -EINVAL;
2372 }
2373 }
2374
2375 return 0;
2376}
2377
2378static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
2379{
2380 struct intel_display *display = to_intel_display(crtc_state);
2381 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2382 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2383 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2384 int clock_limit = display->cdclk.max_dotclk_freq;
2385
2386 /*
2387 * Start with the adjusted_mode crtc timings, which
2388 * have been filled with the transcoder timings.
2389 */
2390 drm_mode_copy(dst: pipe_mode, src: adjusted_mode);
2391
2392 /* Expand MSO per-segment transcoder timings to full */
2393 intel_splitter_adjust_timings(crtc_state, mode: pipe_mode);
2394
2395 /* Derive per-pipe timings in case joiner is used */
2396 intel_joiner_adjust_timings(crtc_state, mode: pipe_mode);
2397 intel_mode_from_crtc_timings(mode: pipe_mode, timings: pipe_mode);
2398
2399 if (DISPLAY_VER(display) < 4) {
2400 clock_limit = display->cdclk.max_cdclk_freq * 9 / 10;
2401
2402 /*
2403 * Enable double wide mode when the dot clock
2404 * is > 90% of the (display) core speed.
2405 */
2406 if (intel_crtc_supports_double_wide(crtc) &&
2407 pipe_mode->crtc_clock > clock_limit) {
2408 clock_limit = display->cdclk.max_dotclk_freq;
2409 crtc_state->double_wide = true;
2410 }
2411 }
2412
2413 if (pipe_mode->crtc_clock > clock_limit) {
2414 drm_dbg_kms(display->drm,
2415 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2416 crtc->base.base.id, crtc->base.name,
2417 pipe_mode->crtc_clock, clock_limit,
2418 str_yes_no(crtc_state->double_wide));
2419 return -EINVAL;
2420 }
2421
2422 return 0;
2423}
2424
2425static int intel_crtc_vblank_delay(const struct intel_crtc_state *crtc_state)
2426{
2427 struct intel_display *display = to_intel_display(crtc_state);
2428 int vblank_delay = 0;
2429
2430 if (!HAS_DSB(display))
2431 return 0;
2432
2433 vblank_delay = max(vblank_delay, intel_psr_min_vblank_delay(crtc_state));
2434
2435 return vblank_delay;
2436}
2437
2438static int intel_crtc_compute_vblank_delay(struct intel_atomic_state *state,
2439 struct intel_crtc *crtc)
2440{
2441 struct intel_display *display = to_intel_display(state);
2442 struct intel_crtc_state *crtc_state =
2443 intel_atomic_get_new_crtc_state(state, crtc);
2444 struct drm_display_mode *adjusted_mode =
2445 &crtc_state->hw.adjusted_mode;
2446 int vblank_delay, max_vblank_delay;
2447
2448 vblank_delay = intel_crtc_vblank_delay(crtc_state);
2449 max_vblank_delay = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start - 1;
2450
2451 if (vblank_delay > max_vblank_delay) {
2452 drm_dbg_kms(display->drm, "[CRTC:%d:%s] vblank delay (%d) exceeds max (%d)\n",
2453 crtc->base.base.id, crtc->base.name, vblank_delay, max_vblank_delay);
2454 return -EINVAL;
2455 }
2456
2457 adjusted_mode->crtc_vblank_start += vblank_delay;
2458
2459 return 0;
2460}
2461
2462static int intel_crtc_compute_config(struct intel_atomic_state *state,
2463 struct intel_crtc *crtc)
2464{
2465 struct intel_crtc_state *crtc_state =
2466 intel_atomic_get_new_crtc_state(state, crtc);
2467 int ret;
2468
2469 ret = intel_crtc_compute_vblank_delay(state, crtc);
2470 if (ret)
2471 return ret;
2472
2473 ret = intel_dpll_crtc_compute_clock(state, crtc);
2474 if (ret)
2475 return ret;
2476
2477 ret = intel_crtc_compute_pipe_src(crtc_state);
2478 if (ret)
2479 return ret;
2480
2481 ret = intel_crtc_compute_pipe_mode(crtc_state);
2482 if (ret)
2483 return ret;
2484
2485 intel_crtc_compute_pixel_rate(crtc_state);
2486
2487 if (crtc_state->has_pch_encoder)
2488 return ilk_fdi_compute_config(intel_crtc: crtc, pipe_config: crtc_state);
2489
2490 return 0;
2491}
2492
2493static void
2494intel_reduce_m_n_ratio(u32 *num, u32 *den)
2495{
2496 while (*num > DATA_LINK_M_N_MASK ||
2497 *den > DATA_LINK_M_N_MASK) {
2498 *num >>= 1;
2499 *den >>= 1;
2500 }
2501}
2502
2503static void compute_m_n(u32 *ret_m, u32 *ret_n,
2504 u32 m, u32 n, u32 constant_n)
2505{
2506 if (constant_n)
2507 *ret_n = constant_n;
2508 else
2509 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
2510
2511 *ret_m = div_u64(dividend: mul_u32_u32(a: m, b: *ret_n), divisor: n);
2512 intel_reduce_m_n_ratio(num: ret_m, den: ret_n);
2513}
2514
2515void
2516intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
2517 int pixel_clock, int link_clock,
2518 int bw_overhead,
2519 struct intel_link_m_n *m_n)
2520{
2521 u32 link_symbol_clock = intel_dp_link_symbol_clock(rate: link_clock);
2522 u32 data_m = intel_dp_effective_data_rate(pixel_clock, bpp_x16: bits_per_pixel_x16,
2523 bw_overhead);
2524 u32 data_n = drm_dp_max_dprx_data_rate(max_link_rate: link_clock, max_lanes: nlanes);
2525
2526 /*
2527 * Windows/BIOS uses fixed M/N values always. Follow suit.
2528 *
2529 * Also several DP dongles in particular seem to be fussy
2530 * about too large link M/N values. Presumably the 20bit
2531 * value used by Windows/BIOS is acceptable to everyone.
2532 */
2533 m_n->tu = 64;
2534 compute_m_n(ret_m: &m_n->data_m, ret_n: &m_n->data_n,
2535 m: data_m, n: data_n,
2536 constant_n: 0x8000000);
2537
2538 compute_m_n(ret_m: &m_n->link_m, ret_n: &m_n->link_n,
2539 m: pixel_clock, n: link_symbol_clock,
2540 constant_n: 0x80000);
2541}
2542
2543void intel_panel_sanitize_ssc(struct intel_display *display)
2544{
2545 /*
2546 * There may be no VBT; and if the BIOS enabled SSC we can
2547 * just keep using it to avoid unnecessary flicker. Whereas if the
2548 * BIOS isn't using it, don't assume it will work even if the VBT
2549 * indicates as much.
2550 */
2551 if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) {
2552 bool bios_lvds_use_ssc = intel_de_read(display,
2553 PCH_DREF_CONTROL) &
2554 DREF_SSC1_ENABLE;
2555
2556 if (display->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2557 drm_dbg_kms(display->drm,
2558 "SSC %s by BIOS, overriding VBT which says %s\n",
2559 str_enabled_disabled(bios_lvds_use_ssc),
2560 str_enabled_disabled(display->vbt.lvds_use_ssc));
2561 display->vbt.lvds_use_ssc = bios_lvds_use_ssc;
2562 }
2563 }
2564}
2565
2566void intel_zero_m_n(struct intel_link_m_n *m_n)
2567{
2568 /* corresponds to 0 register value */
2569 memset(s: m_n, c: 0, n: sizeof(*m_n));
2570 m_n->tu = 1;
2571}
2572
2573void intel_set_m_n(struct intel_display *display,
2574 const struct intel_link_m_n *m_n,
2575 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
2576 i915_reg_t link_m_reg, i915_reg_t link_n_reg)
2577{
2578 intel_de_write(display, reg: data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
2579 intel_de_write(display, reg: data_n_reg, val: m_n->data_n);
2580 intel_de_write(display, reg: link_m_reg, val: m_n->link_m);
2581 /*
2582 * On BDW+ writing LINK_N arms the double buffered update
2583 * of all the M/N registers, so it must be written last.
2584 */
2585 intel_de_write(display, reg: link_n_reg, val: m_n->link_n);
2586}
2587
2588bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
2589 enum transcoder transcoder)
2590{
2591 if (display->platform.haswell)
2592 return transcoder == TRANSCODER_EDP;
2593
2594 return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;
2595}
2596
2597void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
2598 enum transcoder transcoder,
2599 const struct intel_link_m_n *m_n)
2600{
2601 struct intel_display *display = to_intel_display(crtc);
2602 enum pipe pipe = crtc->pipe;
2603
2604 if (DISPLAY_VER(display) >= 5)
2605 intel_set_m_n(display, m_n,
2606 PIPE_DATA_M1(display, transcoder),
2607 PIPE_DATA_N1(display, transcoder),
2608 PIPE_LINK_M1(display, transcoder),
2609 PIPE_LINK_N1(display, transcoder));
2610 else
2611 intel_set_m_n(display, m_n,
2612 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
2613 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
2614}
2615
2616void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
2617 enum transcoder transcoder,
2618 const struct intel_link_m_n *m_n)
2619{
2620 struct intel_display *display = to_intel_display(crtc);
2621
2622 if (!intel_cpu_transcoder_has_m2_n2(display, transcoder))
2623 return;
2624
2625 intel_set_m_n(display, m_n,
2626 PIPE_DATA_M2(display, transcoder),
2627 PIPE_DATA_N2(display, transcoder),
2628 PIPE_LINK_M2(display, transcoder),
2629 PIPE_LINK_N2(display, transcoder));
2630}
2631
2632static bool
2633transcoder_has_vrr(const struct intel_crtc_state *crtc_state)
2634{
2635 struct intel_display *display = to_intel_display(crtc_state);
2636 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2637
2638 return HAS_VRR(display) && !transcoder_is_dsi(transcoder: cpu_transcoder);
2639}
2640
2641static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
2642{
2643 struct intel_display *display = to_intel_display(crtc_state);
2644 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2645 enum pipe pipe = crtc->pipe;
2646 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2647 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2648 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2649 int vsyncshift = 0;
2650
2651 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
2652
2653 /* We need to be careful not to changed the adjusted mode, for otherwise
2654 * the hw state checker will get angry at the mismatch. */
2655 crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2656 crtc_vtotal = adjusted_mode->crtc_vtotal;
2657 crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2658 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2659
2660 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2661 /* the chip adds 2 halflines automatically */
2662 crtc_vtotal -= 1;
2663 crtc_vblank_end -= 1;
2664
2665 if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_SDVO))
2666 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
2667 else
2668 vsyncshift = adjusted_mode->crtc_hsync_start -
2669 adjusted_mode->crtc_htotal / 2;
2670 if (vsyncshift < 0)
2671 vsyncshift += adjusted_mode->crtc_htotal;
2672 }
2673
2674 /*
2675 * VBLANK_START no longer works on ADL+, instead we must use
2676 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
2677 */
2678 if (DISPLAY_VER(display) >= 13) {
2679 intel_de_write(display,
2680 TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
2681 val: crtc_vblank_start - crtc_vdisplay);
2682
2683 /*
2684 * VBLANK_START not used by hw, just clear it
2685 * to make it stand out in register dumps.
2686 */
2687 crtc_vblank_start = 1;
2688 }
2689
2690 if (DISPLAY_VER(display) >= 4)
2691 intel_de_write(display,
2692 TRANS_VSYNCSHIFT(display, cpu_transcoder),
2693 val: vsyncshift);
2694
2695 intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
2696 HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
2697 HTOTAL(adjusted_mode->crtc_htotal - 1));
2698 intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
2699 HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
2700 HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
2701 intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
2702 HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
2703 HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
2704
2705 /*
2706 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
2707 * bits are not required. Since the support for these bits is going to
2708 * be deprecated in upcoming platforms, avoid writing these bits for the
2709 * platforms that do not use legacy Timing Generator.
2710 */
2711 if (intel_vrr_always_use_vrr_tg(display))
2712 crtc_vtotal = 1;
2713
2714 intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
2715 VACTIVE(crtc_vdisplay - 1) |
2716 VTOTAL(crtc_vtotal - 1));
2717 intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
2718 VBLANK_START(crtc_vblank_start - 1) |
2719 VBLANK_END(crtc_vblank_end - 1));
2720 intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
2721 VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
2722 VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
2723
2724 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2725 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2726 * documented on the DDI_FUNC_CTL register description, EDP Input Select
2727 * bits. */
2728 if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP &&
2729 (pipe == PIPE_B || pipe == PIPE_C))
2730 intel_de_write(display, TRANS_VTOTAL(display, pipe),
2731 VACTIVE(crtc_vdisplay - 1) |
2732 VTOTAL(crtc_vtotal - 1));
2733
2734 if (DISPLAY_VER(display) >= 30) {
2735 /*
2736 * Address issues for resolutions with high refresh rate that
2737 * have small Hblank, specifically where Hblank is smaller than
2738 * one MTP. Simulations indicate this will address the
2739 * jitter issues that currently causes BS to be immediately
2740 * followed by BE which DPRX devices are unable to handle.
2741 * https://groups.vesa.org/wg/DP/document/20494
2742 */
2743 intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
2744 val: crtc_state->min_hblank);
2745 }
2746}
2747
2748static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
2749{
2750 struct intel_display *display = to_intel_display(crtc_state);
2751 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2752 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2753 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2754
2755 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
2756
2757 crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2758 crtc_vtotal = adjusted_mode->crtc_vtotal;
2759 crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2760 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2761
2762 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2763 /* the chip adds 2 halflines automatically */
2764 crtc_vtotal -= 1;
2765 crtc_vblank_end -= 1;
2766 }
2767
2768 if (DISPLAY_VER(display) >= 13) {
2769 intel_de_write(display,
2770 TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
2771 val: crtc_vblank_start - crtc_vdisplay);
2772
2773 /*
2774 * VBLANK_START not used by hw, just clear it
2775 * to make it stand out in register dumps.
2776 */
2777 crtc_vblank_start = 1;
2778 }
2779
2780 /*
2781 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
2782 * But let's write it anyway to keep the state checker happy.
2783 */
2784 intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
2785 VBLANK_START(crtc_vblank_start - 1) |
2786 VBLANK_END(crtc_vblank_end - 1));
2787 /*
2788 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
2789 * bits are not required. Since the support for these bits is going to
2790 * be deprecated in upcoming platforms, avoid writing these bits for the
2791 * platforms that do not use legacy Timing Generator.
2792 */
2793 if (intel_vrr_always_use_vrr_tg(display))
2794 crtc_vtotal = 1;
2795
2796 /*
2797 * The double buffer latch point for TRANS_VTOTAL
2798 * is the transcoder's undelayed vblank.
2799 */
2800 intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
2801 VACTIVE(crtc_vdisplay - 1) |
2802 VTOTAL(crtc_vtotal - 1));
2803
2804 intel_vrr_set_fixed_rr_timings(crtc_state);
2805 intel_vrr_transcoder_enable(crtc_state);
2806}
2807
2808static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
2809{
2810 struct intel_display *display = to_intel_display(crtc_state);
2811 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2812 int width = drm_rect_width(r: &crtc_state->pipe_src);
2813 int height = drm_rect_height(r: &crtc_state->pipe_src);
2814 enum pipe pipe = crtc->pipe;
2815
2816 /* pipesrc controls the size that is scaled from, which should
2817 * always be the user's requested size.
2818 */
2819 intel_de_write(display, PIPESRC(display, pipe),
2820 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2821}
2822
2823static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
2824{
2825 struct intel_display *display = to_intel_display(crtc_state);
2826 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2827
2828 if (DISPLAY_VER(display) == 2)
2829 return false;
2830
2831 if (DISPLAY_VER(display) >= 9 ||
2832 display->platform.broadwell || display->platform.haswell)
2833 return intel_de_read(display,
2834 TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
2835 else
2836 return intel_de_read(display,
2837 TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
2838}
2839
2840static void intel_get_transcoder_timings(struct intel_crtc *crtc,
2841 struct intel_crtc_state *pipe_config)
2842{
2843 struct intel_display *display = to_intel_display(crtc);
2844 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2845 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2846 u32 tmp;
2847
2848 tmp = intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder));
2849 adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
2850 adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
2851
2852 if (!transcoder_is_dsi(transcoder: cpu_transcoder)) {
2853 tmp = intel_de_read(display,
2854 TRANS_HBLANK(display, cpu_transcoder));
2855 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
2856 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
2857 }
2858
2859 tmp = intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder));
2860 adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
2861 adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
2862
2863 tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder));
2864 adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
2865 adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
2866
2867 /* FIXME TGL+ DSI transcoders have this! */
2868 if (!transcoder_is_dsi(transcoder: cpu_transcoder)) {
2869 tmp = intel_de_read(display,
2870 TRANS_VBLANK(display, cpu_transcoder));
2871 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
2872 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
2873 }
2874 tmp = intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder));
2875 adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
2876 adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
2877
2878 if (intel_pipe_is_interlaced(crtc_state: pipe_config)) {
2879 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
2880 adjusted_mode->crtc_vtotal += 1;
2881 adjusted_mode->crtc_vblank_end += 1;
2882 }
2883
2884 if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(transcoder: cpu_transcoder))
2885 adjusted_mode->crtc_vblank_start =
2886 adjusted_mode->crtc_vdisplay +
2887 intel_de_read(display,
2888 TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder));
2889
2890 if (DISPLAY_VER(display) >= 30)
2891 pipe_config->min_hblank = intel_de_read(display,
2892 DP_MIN_HBLANK_CTL(cpu_transcoder));
2893}
2894
2895static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
2896{
2897 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2898 int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
2899 enum pipe primary_pipe, pipe = crtc->pipe;
2900 int width;
2901
2902 if (num_pipes == 1)
2903 return;
2904
2905 primary_pipe = joiner_primary_pipe(crtc_state);
2906 width = drm_rect_width(r: &crtc_state->pipe_src);
2907
2908 drm_rect_translate_to(r: &crtc_state->pipe_src,
2909 x: (pipe - primary_pipe) * width, y: 0);
2910}
2911
2912static void intel_get_pipe_src_size(struct intel_crtc *crtc,
2913 struct intel_crtc_state *pipe_config)
2914{
2915 struct intel_display *display = to_intel_display(crtc);
2916 u32 tmp;
2917
2918 tmp = intel_de_read(display, PIPESRC(display, crtc->pipe));
2919
2920 drm_rect_init(r: &pipe_config->pipe_src, x: 0, y: 0,
2921 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
2922 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
2923
2924 intel_joiner_adjust_pipe_src(crtc_state: pipe_config);
2925}
2926
2927void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
2928{
2929 struct intel_display *display = to_intel_display(crtc_state);
2930 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2931 u32 val = 0;
2932
2933 /*
2934 * - We keep both pipes enabled on 830
2935 * - During modeset the pipe is still disabled and must remain so
2936 * - During fastset the pipe is already enabled and must remain so
2937 */
2938 if (display->platform.i830 || !intel_crtc_needs_modeset(crtc_state))
2939 val |= TRANSCONF_ENABLE;
2940
2941 if (crtc_state->double_wide)
2942 val |= TRANSCONF_DOUBLE_WIDE;
2943
2944 /* only g4x and later have fancy bpc/dither controls */
2945 if (display->platform.g4x || display->platform.valleyview ||
2946 display->platform.cherryview) {
2947 /* Bspec claims that we can't use dithering for 30bpp pipes. */
2948 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
2949 val |= TRANSCONF_DITHER_EN |
2950 TRANSCONF_DITHER_TYPE_SP;
2951
2952 switch (crtc_state->pipe_bpp) {
2953 default:
2954 /* Case prevented by intel_choose_pipe_bpp_dither. */
2955 MISSING_CASE(crtc_state->pipe_bpp);
2956 fallthrough;
2957 case 18:
2958 val |= TRANSCONF_BPC_6;
2959 break;
2960 case 24:
2961 val |= TRANSCONF_BPC_8;
2962 break;
2963 case 30:
2964 val |= TRANSCONF_BPC_10;
2965 break;
2966 }
2967 }
2968
2969 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2970 if (DISPLAY_VER(display) < 4 ||
2971 intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_SDVO))
2972 val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION;
2973 else
2974 val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT;
2975 } else {
2976 val |= TRANSCONF_INTERLACE_PROGRESSIVE;
2977 }
2978
2979 if ((display->platform.valleyview || display->platform.cherryview) &&
2980 crtc_state->limited_color_range)
2981 val |= TRANSCONF_COLOR_RANGE_SELECT;
2982
2983 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
2984
2985 if (crtc_state->wgc_enable)
2986 val |= TRANSCONF_WGC_ENABLE;
2987
2988 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
2989
2990 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
2991 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
2992}
2993
2994static enum intel_output_format
2995bdw_get_pipe_misc_output_format(struct intel_crtc *crtc)
2996{
2997 struct intel_display *display = to_intel_display(crtc);
2998 u32 tmp;
2999
3000 tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));
3001
3002 if (tmp & PIPE_MISC_YUV420_ENABLE) {
3003 /*
3004 * We support 4:2:0 in full blend mode only.
3005 * For xe3_lpd+ this is implied in YUV420 Enable bit.
3006 * Ensure the same for prior platforms in YUV420 Mode bit.
3007 */
3008 if (DISPLAY_VER(display) < 30)
3009 drm_WARN_ON(display->drm,
3010 (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0);
3011
3012 return INTEL_OUTPUT_FORMAT_YCBCR420;
3013 } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) {
3014 return INTEL_OUTPUT_FORMAT_YCBCR444;
3015 } else {
3016 return INTEL_OUTPUT_FORMAT_RGB;
3017 }
3018}
3019
3020static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
3021 struct intel_crtc_state *pipe_config)
3022{
3023 struct intel_display *display = to_intel_display(crtc);
3024 enum intel_display_power_domain power_domain;
3025 enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe;
3026 intel_wakeref_t wakeref;
3027 bool ret = false;
3028 u32 tmp;
3029
3030 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3031 wakeref = intel_display_power_get_if_enabled(display, domain: power_domain);
3032 if (!wakeref)
3033 return false;
3034
3035 tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
3036 if (!(tmp & TRANSCONF_ENABLE))
3037 goto out;
3038
3039 pipe_config->cpu_transcoder = cpu_transcoder;
3040
3041 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3042 pipe_config->sink_format = pipe_config->output_format;
3043
3044 if (display->platform.g4x || display->platform.valleyview ||
3045 display->platform.cherryview) {
3046 switch (tmp & TRANSCONF_BPC_MASK) {
3047 case TRANSCONF_BPC_6:
3048 pipe_config->pipe_bpp = 18;
3049 break;
3050 case TRANSCONF_BPC_8:
3051 pipe_config->pipe_bpp = 24;
3052 break;
3053 case TRANSCONF_BPC_10:
3054 pipe_config->pipe_bpp = 30;
3055 break;
3056 default:
3057 MISSING_CASE(tmp);
3058 break;
3059 }
3060 }
3061
3062 if ((display->platform.valleyview || display->platform.cherryview) &&
3063 (tmp & TRANSCONF_COLOR_RANGE_SELECT))
3064 pipe_config->limited_color_range = true;
3065
3066 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);
3067
3068 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3069
3070 if ((display->platform.valleyview || display->platform.cherryview) &&
3071 (tmp & TRANSCONF_WGC_ENABLE))
3072 pipe_config->wgc_enable = true;
3073
3074 intel_color_get_config(crtc_state: pipe_config);
3075
3076 if (HAS_DOUBLE_WIDE(display))
3077 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
3078
3079 intel_get_transcoder_timings(crtc, pipe_config);
3080 intel_get_pipe_src_size(crtc, pipe_config);
3081
3082 i9xx_pfit_get_config(crtc_state: pipe_config);
3083
3084 i9xx_dpll_get_hw_state(crtc, dpll_hw_state: &pipe_config->dpll_hw_state);
3085
3086 if (DISPLAY_VER(display) >= 4) {
3087 tmp = pipe_config->dpll_hw_state.i9xx.dpll_md;
3088 pipe_config->pixel_multiplier =
3089 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
3090 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
3091 } else if (display->platform.i945g || display->platform.i945gm ||
3092 display->platform.g33 || display->platform.pineview) {
3093 tmp = pipe_config->dpll_hw_state.i9xx.dpll;
3094 pipe_config->pixel_multiplier =
3095 ((tmp & SDVO_MULTIPLIER_MASK)
3096 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
3097 } else {
3098 /* Note that on i915G/GM the pixel multiplier is in the sdvo
3099 * port and will be fixed up in the encoder->get_config
3100 * function. */
3101 pipe_config->pixel_multiplier = 1;
3102 }
3103
3104 if (display->platform.cherryview)
3105 chv_crtc_clock_get(crtc_state: pipe_config);
3106 else if (display->platform.valleyview)
3107 vlv_crtc_clock_get(crtc_state: pipe_config);
3108 else
3109 i9xx_crtc_clock_get(crtc_state: pipe_config);
3110
3111 /*
3112 * Normally the dotclock is filled in by the encoder .get_config()
3113 * but in case the pipe is enabled w/o any ports we need a sane
3114 * default.
3115 */
3116 pipe_config->hw.adjusted_mode.crtc_clock =
3117 pipe_config->port_clock / pipe_config->pixel_multiplier;
3118
3119 ret = true;
3120
3121out:
3122 intel_display_power_put(display, domain: power_domain, wakeref);
3123
3124 return ret;
3125}
3126
3127void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3128{
3129 struct intel_display *display = to_intel_display(crtc_state);
3130 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3131 u32 val = 0;
3132
3133 /*
3134 * - During modeset the pipe is still disabled and must remain so
3135 * - During fastset the pipe is already enabled and must remain so
3136 */
3137 if (!intel_crtc_needs_modeset(crtc_state))
3138 val |= TRANSCONF_ENABLE;
3139
3140 switch (crtc_state->pipe_bpp) {
3141 default:
3142 /* Case prevented by intel_choose_pipe_bpp_dither. */
3143 MISSING_CASE(crtc_state->pipe_bpp);
3144 fallthrough;
3145 case 18:
3146 val |= TRANSCONF_BPC_6;
3147 break;
3148 case 24:
3149 val |= TRANSCONF_BPC_8;
3150 break;
3151 case 30:
3152 val |= TRANSCONF_BPC_10;
3153 break;
3154 case 36:
3155 val |= TRANSCONF_BPC_12;
3156 break;
3157 }
3158
3159 if (crtc_state->dither)
3160 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3161
3162 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3163 val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3164 else
3165 val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3166
3167 /*
3168 * This would end up with an odd purple hue over
3169 * the entire display. Make sure we don't do it.
3170 */
3171 drm_WARN_ON(display->drm, crtc_state->limited_color_range &&
3172 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
3173
3174 if (crtc_state->limited_color_range &&
3175 !intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_SDVO))
3176 val |= TRANSCONF_COLOR_RANGE_SELECT;
3177
3178 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3179 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709;
3180
3181 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
3182
3183 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3184 val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
3185
3186 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
3187 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
3188}
3189
3190static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
3191{
3192 struct intel_display *display = to_intel_display(crtc_state);
3193 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3194 u32 val = 0;
3195
3196 /*
3197 * - During modeset the pipe is still disabled and must remain so
3198 * - During fastset the pipe is already enabled and must remain so
3199 */
3200 if (!intel_crtc_needs_modeset(crtc_state))
3201 val |= TRANSCONF_ENABLE;
3202
3203 if (display->platform.haswell && crtc_state->dither)
3204 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3205
3206 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3207 val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3208 else
3209 val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3210
3211 if (display->platform.haswell &&
3212 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3213 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
3214
3215 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
3216 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
3217}
3218
3219static void bdw_set_pipe_misc(struct intel_dsb *dsb,
3220 const struct intel_crtc_state *crtc_state)
3221{
3222 struct intel_display *display = to_intel_display(crtc_state);
3223 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3224 u32 val = 0;
3225
3226 switch (crtc_state->pipe_bpp) {
3227 case 18:
3228 val |= PIPE_MISC_BPC_6;
3229 break;
3230 case 24:
3231 val |= PIPE_MISC_BPC_8;
3232 break;
3233 case 30:
3234 val |= PIPE_MISC_BPC_10;
3235 break;
3236 case 36:
3237 /* Port output 12BPC defined for ADLP+ */
3238 if (DISPLAY_VER(display) >= 13)
3239 val |= PIPE_MISC_BPC_12_ADLP;
3240 break;
3241 default:
3242 MISSING_CASE(crtc_state->pipe_bpp);
3243 break;
3244 }
3245
3246 if (crtc_state->dither)
3247 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP;
3248
3249 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3250 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3251 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV;
3252
3253 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3254 val |= DISPLAY_VER(display) >= 30 ? PIPE_MISC_YUV420_ENABLE :
3255 PIPE_MISC_YUV420_ENABLE | PIPE_MISC_YUV420_MODE_FULL_BLEND;
3256
3257 if (DISPLAY_VER(display) >= 11 && is_hdr_mode(crtc_state))
3258 val |= PIPE_MISC_HDR_MODE_PRECISION;
3259
3260 if (DISPLAY_VER(display) >= 12)
3261 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC;
3262
3263 /* allow PSR with sprite enabled */
3264 if (display->platform.broadwell)
3265 val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE;
3266
3267 intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val);
3268}
3269
3270int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc)
3271{
3272 struct intel_display *display = to_intel_display(crtc);
3273 u32 tmp;
3274
3275 tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));
3276
3277 switch (tmp & PIPE_MISC_BPC_MASK) {
3278 case PIPE_MISC_BPC_6:
3279 return 18;
3280 case PIPE_MISC_BPC_8:
3281 return 24;
3282 case PIPE_MISC_BPC_10:
3283 return 30;
3284 /*
3285 * PORT OUTPUT 12 BPC defined for ADLP+.
3286 *
3287 * TODO:
3288 * For previous platforms with DSI interface, bits 5:7
3289 * are used for storing pipe_bpp irrespective of dithering.
3290 * Since the value of 12 BPC is not defined for these bits
3291 * on older platforms, need to find a workaround for 12 BPC
3292 * MIPI DSI HW readout.
3293 */
3294 case PIPE_MISC_BPC_12_ADLP:
3295 if (DISPLAY_VER(display) >= 13)
3296 return 36;
3297 fallthrough;
3298 default:
3299 MISSING_CASE(tmp);
3300 return 0;
3301 }
3302}
3303
3304int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
3305{
3306 /*
3307 * Account for spread spectrum to avoid
3308 * oversubscribing the link. Max center spread
3309 * is 2.5%; use 5% for safety's sake.
3310 */
3311 u32 bps = target_clock * bpp * 21 / 20;
3312 return DIV_ROUND_UP(bps, link_bw * 8);
3313}
3314
3315void intel_get_m_n(struct intel_display *display,
3316 struct intel_link_m_n *m_n,
3317 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3318 i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3319{
3320 m_n->link_m = intel_de_read(display, reg: link_m_reg) & DATA_LINK_M_N_MASK;
3321 m_n->link_n = intel_de_read(display, reg: link_n_reg) & DATA_LINK_M_N_MASK;
3322 m_n->data_m = intel_de_read(display, reg: data_m_reg) & DATA_LINK_M_N_MASK;
3323 m_n->data_n = intel_de_read(display, reg: data_n_reg) & DATA_LINK_M_N_MASK;
3324 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
3325}
3326
3327void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
3328 enum transcoder transcoder,
3329 struct intel_link_m_n *m_n)
3330{
3331 struct intel_display *display = to_intel_display(crtc);
3332 enum pipe pipe = crtc->pipe;
3333
3334 if (DISPLAY_VER(display) >= 5)
3335 intel_get_m_n(display, m_n,
3336 PIPE_DATA_M1(display, transcoder),
3337 PIPE_DATA_N1(display, transcoder),
3338 PIPE_LINK_M1(display, transcoder),
3339 PIPE_LINK_N1(display, transcoder));
3340 else
3341 intel_get_m_n(display, m_n,
3342 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3343 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
3344}
3345
3346void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
3347 enum transcoder transcoder,
3348 struct intel_link_m_n *m_n)
3349{
3350 struct intel_display *display = to_intel_display(crtc);
3351
3352 if (!intel_cpu_transcoder_has_m2_n2(display, transcoder))
3353 return;
3354
3355 intel_get_m_n(display, m_n,
3356 PIPE_DATA_M2(display, transcoder),
3357 PIPE_DATA_N2(display, transcoder),
3358 PIPE_LINK_M2(display, transcoder),
3359 PIPE_LINK_N2(display, transcoder));
3360}
3361
3362static bool ilk_get_pipe_config(struct intel_crtc *crtc,
3363 struct intel_crtc_state *pipe_config)
3364{
3365 struct intel_display *display = to_intel_display(crtc);
3366 enum intel_display_power_domain power_domain;
3367 enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe;
3368 intel_wakeref_t wakeref;
3369 bool ret = false;
3370 u32 tmp;
3371
3372 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3373 wakeref = intel_display_power_get_if_enabled(display, domain: power_domain);
3374 if (!wakeref)
3375 return false;
3376
3377 tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
3378 if (!(tmp & TRANSCONF_ENABLE))
3379 goto out;
3380
3381 pipe_config->cpu_transcoder = cpu_transcoder;
3382
3383 switch (tmp & TRANSCONF_BPC_MASK) {
3384 case TRANSCONF_BPC_6:
3385 pipe_config->pipe_bpp = 18;
3386 break;
3387 case TRANSCONF_BPC_8:
3388 pipe_config->pipe_bpp = 24;
3389 break;
3390 case TRANSCONF_BPC_10:
3391 pipe_config->pipe_bpp = 30;
3392 break;
3393 case TRANSCONF_BPC_12:
3394 pipe_config->pipe_bpp = 36;
3395 break;
3396 default:
3397 break;
3398 }
3399
3400 if (tmp & TRANSCONF_COLOR_RANGE_SELECT)
3401 pipe_config->limited_color_range = true;
3402
3403 switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) {
3404 case TRANSCONF_OUTPUT_COLORSPACE_YUV601:
3405 case TRANSCONF_OUTPUT_COLORSPACE_YUV709:
3406 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3407 break;
3408 default:
3409 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3410 break;
3411 }
3412
3413 pipe_config->sink_format = pipe_config->output_format;
3414
3415 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);
3416
3417 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3418
3419 pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
3420
3421 intel_color_get_config(crtc_state: pipe_config);
3422
3423 pipe_config->pixel_multiplier = 1;
3424
3425 ilk_pch_get_config(crtc_state: pipe_config);
3426
3427 intel_get_transcoder_timings(crtc, pipe_config);
3428 intel_get_pipe_src_size(crtc, pipe_config);
3429
3430 ilk_pfit_get_config(crtc_state: pipe_config);
3431
3432 ret = true;
3433
3434out:
3435 intel_display_power_put(display, domain: power_domain, wakeref);
3436
3437 return ret;
3438}
3439
3440static u8 joiner_pipes(struct intel_display *display)
3441{
3442 u8 pipes;
3443
3444 if (DISPLAY_VER(display) >= 12)
3445 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3446 else if (DISPLAY_VER(display) >= 11)
3447 pipes = BIT(PIPE_B) | BIT(PIPE_C);
3448 else
3449 pipes = 0;
3450
3451 return pipes & DISPLAY_RUNTIME_INFO(display)->pipe_mask;
3452}
3453
3454static bool transcoder_ddi_func_is_enabled(struct intel_display *display,
3455 enum transcoder cpu_transcoder)
3456{
3457 enum intel_display_power_domain power_domain;
3458 intel_wakeref_t wakeref;
3459 u32 tmp = 0;
3460
3461 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3462
3463 with_intel_display_power_if_enabled(display, power_domain, wakeref)
3464 tmp = intel_de_read(display,
3465 TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
3466
3467 return tmp & TRANS_DDI_FUNC_ENABLE;
3468}
3469
3470static void enabled_uncompressed_joiner_pipes(struct intel_display *display,
3471 u8 *primary_pipes, u8 *secondary_pipes)
3472{
3473 struct intel_crtc *crtc;
3474
3475 *primary_pipes = 0;
3476 *secondary_pipes = 0;
3477
3478 if (!HAS_UNCOMPRESSED_JOINER(display))
3479 return;
3480
3481 for_each_intel_crtc_in_pipe_mask(display->drm, crtc,
3482 joiner_pipes(display)) {
3483 enum intel_display_power_domain power_domain;
3484 enum pipe pipe = crtc->pipe;
3485 intel_wakeref_t wakeref;
3486
3487 power_domain = POWER_DOMAIN_PIPE(pipe);
3488 with_intel_display_power_if_enabled(display, power_domain, wakeref) {
3489 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
3490
3491 if (tmp & UNCOMPRESSED_JOINER_PRIMARY)
3492 *primary_pipes |= BIT(pipe);
3493 if (tmp & UNCOMPRESSED_JOINER_SECONDARY)
3494 *secondary_pipes |= BIT(pipe);
3495 }
3496 }
3497}
3498
3499static void enabled_bigjoiner_pipes(struct intel_display *display,
3500 u8 *primary_pipes, u8 *secondary_pipes)
3501{
3502 struct intel_crtc *crtc;
3503
3504 *primary_pipes = 0;
3505 *secondary_pipes = 0;
3506
3507 if (!HAS_BIGJOINER(display))
3508 return;
3509
3510 for_each_intel_crtc_in_pipe_mask(display->drm, crtc,
3511 joiner_pipes(display)) {
3512 enum intel_display_power_domain power_domain;
3513 enum pipe pipe = crtc->pipe;
3514 intel_wakeref_t wakeref;
3515
3516 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder: (enum transcoder)pipe);
3517 with_intel_display_power_if_enabled(display, power_domain, wakeref) {
3518 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
3519
3520 if (!(tmp & BIG_JOINER_ENABLE))
3521 continue;
3522
3523 if (tmp & PRIMARY_BIG_JOINER_ENABLE)
3524 *primary_pipes |= BIT(pipe);
3525 else
3526 *secondary_pipes |= BIT(pipe);
3527 }
3528 }
3529}
3530
3531static u8 expected_secondary_pipes(u8 primary_pipes, int num_pipes)
3532{
3533 u8 secondary_pipes = 0;
3534
3535 for (int i = 1; i < num_pipes; i++)
3536 secondary_pipes |= primary_pipes << i;
3537
3538 return secondary_pipes;
3539}
3540
3541static u8 expected_uncompressed_joiner_secondary_pipes(u8 uncompjoiner_primary_pipes)
3542{
3543 return expected_secondary_pipes(primary_pipes: uncompjoiner_primary_pipes, num_pipes: 2);
3544}
3545
3546static u8 expected_bigjoiner_secondary_pipes(u8 bigjoiner_primary_pipes)
3547{
3548 return expected_secondary_pipes(primary_pipes: bigjoiner_primary_pipes, num_pipes: 2);
3549}
3550
3551static u8 get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes)
3552{
3553 primary_pipes &= GENMASK(pipe, 0);
3554
3555 return primary_pipes ? BIT(fls(primary_pipes) - 1) : 0;
3556}
3557
3558static u8 expected_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes)
3559{
3560 return expected_secondary_pipes(primary_pipes: ultrajoiner_primary_pipes, num_pipes: 4);
3561}
3562
3563static u8 fixup_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes,
3564 u8 ultrajoiner_secondary_pipes)
3565{
3566 return ultrajoiner_secondary_pipes | ultrajoiner_primary_pipes << 3;
3567}
3568
3569static void enabled_ultrajoiner_pipes(struct intel_display *display,
3570 u8 *primary_pipes, u8 *secondary_pipes)
3571{
3572 struct intel_crtc *crtc;
3573
3574 *primary_pipes = 0;
3575 *secondary_pipes = 0;
3576
3577 if (!HAS_ULTRAJOINER(display))
3578 return;
3579
3580 for_each_intel_crtc_in_pipe_mask(display->drm, crtc,
3581 joiner_pipes(display)) {
3582 enum intel_display_power_domain power_domain;
3583 enum pipe pipe = crtc->pipe;
3584 intel_wakeref_t wakeref;
3585
3586 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder: (enum transcoder)pipe);
3587 with_intel_display_power_if_enabled(display, power_domain, wakeref) {
3588 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
3589
3590 if (!(tmp & ULTRA_JOINER_ENABLE))
3591 continue;
3592
3593 if (tmp & PRIMARY_ULTRA_JOINER_ENABLE)
3594 *primary_pipes |= BIT(pipe);
3595 else
3596 *secondary_pipes |= BIT(pipe);
3597 }
3598 }
3599}
3600
3601static void enabled_joiner_pipes(struct intel_display *display,
3602 enum pipe pipe,
3603 u8 *primary_pipe, u8 *secondary_pipes)
3604{
3605 u8 primary_ultrajoiner_pipes;
3606 u8 primary_uncompressed_joiner_pipes, primary_bigjoiner_pipes;
3607 u8 secondary_ultrajoiner_pipes;
3608 u8 secondary_uncompressed_joiner_pipes, secondary_bigjoiner_pipes;
3609 u8 ultrajoiner_pipes;
3610 u8 uncompressed_joiner_pipes, bigjoiner_pipes;
3611
3612 enabled_ultrajoiner_pipes(display, primary_pipes: &primary_ultrajoiner_pipes,
3613 secondary_pipes: &secondary_ultrajoiner_pipes);
3614 /*
3615 * For some strange reason the last pipe in the set of four
3616 * shouldn't have ultrajoiner enable bit set in hardware.
3617 * Set the bit anyway to make life easier.
3618 */
3619 drm_WARN_ON(display->drm,
3620 expected_secondary_pipes(primary_ultrajoiner_pipes, 3) !=
3621 secondary_ultrajoiner_pipes);
3622 secondary_ultrajoiner_pipes =
3623 fixup_ultrajoiner_secondary_pipes(ultrajoiner_primary_pipes: primary_ultrajoiner_pipes,
3624 ultrajoiner_secondary_pipes: secondary_ultrajoiner_pipes);
3625
3626 drm_WARN_ON(display->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0);
3627
3628 enabled_uncompressed_joiner_pipes(display, primary_pipes: &primary_uncompressed_joiner_pipes,
3629 secondary_pipes: &secondary_uncompressed_joiner_pipes);
3630
3631 drm_WARN_ON(display->drm,
3632 (primary_uncompressed_joiner_pipes & secondary_uncompressed_joiner_pipes) != 0);
3633
3634 enabled_bigjoiner_pipes(display, primary_pipes: &primary_bigjoiner_pipes,
3635 secondary_pipes: &secondary_bigjoiner_pipes);
3636
3637 drm_WARN_ON(display->drm,
3638 (primary_bigjoiner_pipes & secondary_bigjoiner_pipes) != 0);
3639
3640 ultrajoiner_pipes = primary_ultrajoiner_pipes | secondary_ultrajoiner_pipes;
3641 uncompressed_joiner_pipes = primary_uncompressed_joiner_pipes |
3642 secondary_uncompressed_joiner_pipes;
3643 bigjoiner_pipes = primary_bigjoiner_pipes | secondary_bigjoiner_pipes;
3644
3645 drm_WARN(display->drm, (ultrajoiner_pipes & bigjoiner_pipes) != ultrajoiner_pipes,
3646 "Ultrajoiner pipes(%#x) should be bigjoiner pipes(%#x)\n",
3647 ultrajoiner_pipes, bigjoiner_pipes);
3648
3649 drm_WARN(display->drm, secondary_ultrajoiner_pipes !=
3650 expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes),
3651 "Wrong secondary ultrajoiner pipes(expected %#x, current %#x)\n",
3652 expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes),
3653 secondary_ultrajoiner_pipes);
3654
3655 drm_WARN(display->drm, (uncompressed_joiner_pipes & bigjoiner_pipes) != 0,
3656 "Uncompressed joiner pipes(%#x) and bigjoiner pipes(%#x) can't intersect\n",
3657 uncompressed_joiner_pipes, bigjoiner_pipes);
3658
3659 drm_WARN(display->drm, secondary_bigjoiner_pipes !=
3660 expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes),
3661 "Wrong secondary bigjoiner pipes(expected %#x, current %#x)\n",
3662 expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes),
3663 secondary_bigjoiner_pipes);
3664
3665 drm_WARN(display->drm, secondary_uncompressed_joiner_pipes !=
3666 expected_uncompressed_joiner_secondary_pipes(primary_uncompressed_joiner_pipes),
3667 "Wrong secondary uncompressed joiner pipes(expected %#x, current %#x)\n",
3668 expected_uncompressed_joiner_secondary_pipes(primary_uncompressed_joiner_pipes),
3669 secondary_uncompressed_joiner_pipes);
3670
3671 *primary_pipe = 0;
3672 *secondary_pipes = 0;
3673
3674 if (ultrajoiner_pipes & BIT(pipe)) {
3675 *primary_pipe = get_joiner_primary_pipe(pipe, primary_pipes: primary_ultrajoiner_pipes);
3676 *secondary_pipes = secondary_ultrajoiner_pipes &
3677 expected_ultrajoiner_secondary_pipes(ultrajoiner_primary_pipes: *primary_pipe);
3678
3679 drm_WARN(display->drm,
3680 expected_ultrajoiner_secondary_pipes(*primary_pipe) !=
3681 *secondary_pipes,
3682 "Wrong ultrajoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n",
3683 *primary_pipe,
3684 expected_ultrajoiner_secondary_pipes(*primary_pipe),
3685 *secondary_pipes);
3686 return;
3687 }
3688
3689 if (uncompressed_joiner_pipes & BIT(pipe)) {
3690 *primary_pipe = get_joiner_primary_pipe(pipe, primary_pipes: primary_uncompressed_joiner_pipes);
3691 *secondary_pipes = secondary_uncompressed_joiner_pipes &
3692 expected_uncompressed_joiner_secondary_pipes(uncompjoiner_primary_pipes: *primary_pipe);
3693
3694 drm_WARN(display->drm,
3695 expected_uncompressed_joiner_secondary_pipes(*primary_pipe) !=
3696 *secondary_pipes,
3697 "Wrong uncompressed joiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n",
3698 *primary_pipe,
3699 expected_uncompressed_joiner_secondary_pipes(*primary_pipe),
3700 *secondary_pipes);
3701 return;
3702 }
3703
3704 if (bigjoiner_pipes & BIT(pipe)) {
3705 *primary_pipe = get_joiner_primary_pipe(pipe, primary_pipes: primary_bigjoiner_pipes);
3706 *secondary_pipes = secondary_bigjoiner_pipes &
3707 expected_bigjoiner_secondary_pipes(bigjoiner_primary_pipes: *primary_pipe);
3708
3709 drm_WARN(display->drm,
3710 expected_bigjoiner_secondary_pipes(*primary_pipe) !=
3711 *secondary_pipes,
3712 "Wrong bigjoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n",
3713 *primary_pipe,
3714 expected_bigjoiner_secondary_pipes(*primary_pipe),
3715 *secondary_pipes);
3716 return;
3717 }
3718}
3719
3720static u8 hsw_panel_transcoders(struct intel_display *display)
3721{
3722 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
3723
3724 if (DISPLAY_VER(display) >= 11)
3725 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
3726
3727 return panel_transcoder_mask;
3728}
3729
3730static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
3731{
3732 struct intel_display *display = to_intel_display(crtc);
3733 u8 panel_transcoder_mask = hsw_panel_transcoders(display);
3734 enum transcoder cpu_transcoder;
3735 u8 primary_pipe, secondary_pipes;
3736 u8 enabled_transcoders = 0;
3737
3738 /*
3739 * XXX: Do intel_display_power_get_if_enabled before reading this (for
3740 * consistency and less surprising code; it's in always on power).
3741 */
3742 for_each_cpu_transcoder_masked(display, cpu_transcoder,
3743 panel_transcoder_mask) {
3744 enum intel_display_power_domain power_domain;
3745 intel_wakeref_t wakeref;
3746 enum pipe trans_pipe;
3747 u32 tmp = 0;
3748
3749 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3750 with_intel_display_power_if_enabled(display, power_domain, wakeref)
3751 tmp = intel_de_read(display,
3752 TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
3753
3754 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
3755 continue;
3756
3757 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
3758 default:
3759 drm_WARN(display->drm, 1,
3760 "unknown pipe linked to transcoder %s\n",
3761 transcoder_name(cpu_transcoder));
3762 fallthrough;
3763 case TRANS_DDI_EDP_INPUT_A_ONOFF:
3764 case TRANS_DDI_EDP_INPUT_A_ON:
3765 trans_pipe = PIPE_A;
3766 break;
3767 case TRANS_DDI_EDP_INPUT_B_ONOFF:
3768 trans_pipe = PIPE_B;
3769 break;
3770 case TRANS_DDI_EDP_INPUT_C_ONOFF:
3771 trans_pipe = PIPE_C;
3772 break;
3773 case TRANS_DDI_EDP_INPUT_D_ONOFF:
3774 trans_pipe = PIPE_D;
3775 break;
3776 }
3777
3778 if (trans_pipe == crtc->pipe)
3779 enabled_transcoders |= BIT(cpu_transcoder);
3780 }
3781
3782 /* single pipe or joiner primary */
3783 cpu_transcoder = (enum transcoder) crtc->pipe;
3784 if (transcoder_ddi_func_is_enabled(display, cpu_transcoder))
3785 enabled_transcoders |= BIT(cpu_transcoder);
3786
3787 /* joiner secondary -> consider the primary pipe's transcoder as well */
3788 enabled_joiner_pipes(display, pipe: crtc->pipe, primary_pipe: &primary_pipe, secondary_pipes: &secondary_pipes);
3789 if (secondary_pipes & BIT(crtc->pipe)) {
3790 cpu_transcoder = (enum transcoder)ffs(primary_pipe) - 1;
3791 if (transcoder_ddi_func_is_enabled(display, cpu_transcoder))
3792 enabled_transcoders |= BIT(cpu_transcoder);
3793 }
3794
3795 return enabled_transcoders;
3796}
3797
3798static bool has_edp_transcoders(u8 enabled_transcoders)
3799{
3800 return enabled_transcoders & BIT(TRANSCODER_EDP);
3801}
3802
3803static bool has_dsi_transcoders(u8 enabled_transcoders)
3804{
3805 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
3806 BIT(TRANSCODER_DSI_1));
3807}
3808
3809static bool has_pipe_transcoders(u8 enabled_transcoders)
3810{
3811 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
3812 BIT(TRANSCODER_DSI_0) |
3813 BIT(TRANSCODER_DSI_1));
3814}
3815
3816static void assert_enabled_transcoders(struct intel_display *display,
3817 u8 enabled_transcoders)
3818{
3819 /* Only one type of transcoder please */
3820 drm_WARN_ON(display->drm,
3821 has_edp_transcoders(enabled_transcoders) +
3822 has_dsi_transcoders(enabled_transcoders) +
3823 has_pipe_transcoders(enabled_transcoders) > 1);
3824
3825 /* Only DSI transcoders can be ganged */
3826 drm_WARN_ON(display->drm,
3827 !has_dsi_transcoders(enabled_transcoders) &&
3828 !is_power_of_2(enabled_transcoders));
3829}
3830
3831static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
3832 struct intel_crtc_state *pipe_config,
3833 struct intel_display_power_domain_set *power_domain_set)
3834{
3835 struct intel_display *display = to_intel_display(crtc);
3836 unsigned long enabled_transcoders;
3837 u32 tmp;
3838
3839 enabled_transcoders = hsw_enabled_transcoders(crtc);
3840 if (!enabled_transcoders)
3841 return false;
3842
3843 assert_enabled_transcoders(display, enabled_transcoders);
3844
3845 /*
3846 * With the exception of DSI we should only ever have
3847 * a single enabled transcoder. With DSI let's just
3848 * pick the first one.
3849 */
3850 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;
3851
3852 if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set,
3853 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
3854 return false;
3855
3856 if (hsw_panel_transcoders(display) & BIT(pipe_config->cpu_transcoder)) {
3857 tmp = intel_de_read(display,
3858 TRANS_DDI_FUNC_CTL(display, pipe_config->cpu_transcoder));
3859
3860 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
3861 pipe_config->pch_pfit.force_thru = true;
3862 }
3863
3864 tmp = intel_de_read(display,
3865 TRANSCONF(display, pipe_config->cpu_transcoder));
3866
3867 return tmp & TRANSCONF_ENABLE;
3868}
3869
3870static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
3871 struct intel_crtc_state *pipe_config,
3872 struct intel_display_power_domain_set *power_domain_set)
3873{
3874 struct intel_display *display = to_intel_display(crtc);
3875 enum transcoder cpu_transcoder;
3876 enum port port;
3877 u32 tmp;
3878
3879 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
3880 if (port == PORT_A)
3881 cpu_transcoder = TRANSCODER_DSI_A;
3882 else
3883 cpu_transcoder = TRANSCODER_DSI_C;
3884
3885 if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set,
3886 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
3887 continue;
3888
3889 /*
3890 * The PLL needs to be enabled with a valid divider
3891 * configuration, otherwise accessing DSI registers will hang
3892 * the machine. See BSpec North Display Engine
3893 * registers/MIPI[BXT]. We can break out here early, since we
3894 * need the same DSI PLL to be enabled for both DSI ports.
3895 */
3896 if (!bxt_dsi_pll_is_enabled(display))
3897 break;
3898
3899 /* XXX: this works for video mode only */
3900 tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));
3901 if (!(tmp & DPI_ENABLE))
3902 continue;
3903
3904 tmp = intel_de_read(display, MIPI_CTRL(display, port));
3905 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
3906 continue;
3907
3908 pipe_config->cpu_transcoder = cpu_transcoder;
3909 break;
3910 }
3911
3912 return transcoder_is_dsi(transcoder: pipe_config->cpu_transcoder);
3913}
3914
3915static void intel_joiner_get_config(struct intel_crtc_state *crtc_state)
3916{
3917 struct intel_display *display = to_intel_display(crtc_state);
3918 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3919 u8 primary_pipe, secondary_pipes;
3920 enum pipe pipe = crtc->pipe;
3921
3922 enabled_joiner_pipes(display, pipe, primary_pipe: &primary_pipe, secondary_pipes: &secondary_pipes);
3923
3924 if (((primary_pipe | secondary_pipes) & BIT(pipe)) == 0)
3925 return;
3926
3927 crtc_state->joiner_pipes = primary_pipe | secondary_pipes;
3928}
3929
3930static bool hsw_get_pipe_config(struct intel_crtc *crtc,
3931 struct intel_crtc_state *pipe_config)
3932{
3933 struct intel_display *display = to_intel_display(crtc);
3934 bool active;
3935 u32 tmp;
3936
3937 if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set: &crtc->hw_readout_power_domains,
3938 POWER_DOMAIN_PIPE(crtc->pipe)))
3939 return false;
3940
3941 active = hsw_get_transcoder_state(crtc, pipe_config, power_domain_set: &crtc->hw_readout_power_domains);
3942
3943 if ((display->platform.geminilake || display->platform.broxton) &&
3944 bxt_get_dsi_transcoder_state(crtc, pipe_config, power_domain_set: &crtc->hw_readout_power_domains)) {
3945 drm_WARN_ON(display->drm, active);
3946 active = true;
3947 }
3948
3949 if (!active)
3950 goto out;
3951
3952 intel_joiner_get_config(crtc_state: pipe_config);
3953 intel_dsc_get_config(crtc_state: pipe_config);
3954
3955 if (!transcoder_is_dsi(transcoder: pipe_config->cpu_transcoder) ||
3956 DISPLAY_VER(display) >= 11)
3957 intel_get_transcoder_timings(crtc, pipe_config);
3958
3959 if (transcoder_has_vrr(crtc_state: pipe_config))
3960 intel_vrr_get_config(crtc_state: pipe_config);
3961
3962 intel_get_pipe_src_size(crtc, pipe_config);
3963
3964 if (display->platform.haswell) {
3965 u32 tmp = intel_de_read(display,
3966 TRANSCONF(display, pipe_config->cpu_transcoder));
3967
3968 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
3969 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3970 else
3971 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3972 } else {
3973 pipe_config->output_format =
3974 bdw_get_pipe_misc_output_format(crtc);
3975 }
3976
3977 pipe_config->sink_format = pipe_config->output_format;
3978
3979 intel_color_get_config(crtc_state: pipe_config);
3980
3981 tmp = intel_de_read(display, WM_LINETIME(crtc->pipe));
3982 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
3983 if (display->platform.broadwell || display->platform.haswell)
3984 pipe_config->ips_linetime =
3985 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
3986
3987 if (intel_display_power_get_in_set_if_enabled(display, power_domain_set: &crtc->hw_readout_power_domains,
3988 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
3989 if (DISPLAY_VER(display) >= 9)
3990 skl_scaler_get_config(crtc_state: pipe_config);
3991 else
3992 ilk_pfit_get_config(crtc_state: pipe_config);
3993 }
3994
3995 hsw_ips_get_config(crtc_state: pipe_config);
3996
3997 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
3998 !transcoder_is_dsi(transcoder: pipe_config->cpu_transcoder)) {
3999 pipe_config->pixel_multiplier =
4000 intel_de_read(display,
4001 TRANS_MULT(display, pipe_config->cpu_transcoder)) + 1;
4002 } else {
4003 pipe_config->pixel_multiplier = 1;
4004 }
4005
4006 if (!transcoder_is_dsi(transcoder: pipe_config->cpu_transcoder)) {
4007 tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
4008
4009 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
4010 } else {
4011 /* no idea if this is correct */
4012 pipe_config->framestart_delay = 1;
4013 }
4014
4015out:
4016 intel_display_power_put_all_in_set(display, power_domain_set: &crtc->hw_readout_power_domains);
4017
4018 return active;
4019}
4020
4021bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
4022{
4023 struct intel_display *display = to_intel_display(crtc_state);
4024 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4025
4026 if (!display->funcs.display->get_pipe_config(crtc, crtc_state))
4027 return false;
4028
4029 crtc_state->hw.active = true;
4030
4031 intel_crtc_readout_derived_state(crtc_state);
4032
4033 return true;
4034}
4035
4036int intel_dotclock_calculate(int link_freq,
4037 const struct intel_link_m_n *m_n)
4038{
4039 /*
4040 * The calculation for the data clock -> pixel clock is:
4041 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
4042 * But we want to avoid losing precision if possible, so:
4043 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
4044 *
4045 * and for link freq (10kbs units) -> pixel clock it is:
4046 * link_symbol_clock = link_freq * 10 / link_symbol_size
4047 * pixel_clock = (m * link_symbol_clock) / n
4048 * or for more precision:
4049 * pixel_clock = (m * link_freq * 10) / (n * link_symbol_size)
4050 */
4051
4052 if (!m_n->link_n)
4053 return 0;
4054
4055 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10),
4056 m_n->link_n * intel_dp_link_symbol_size(link_freq));
4057}
4058
4059int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
4060{
4061 int dotclock;
4062
4063 if (intel_crtc_has_dp_encoder(crtc_state: pipe_config))
4064 dotclock = intel_dotclock_calculate(link_freq: pipe_config->port_clock,
4065 m_n: &pipe_config->dp_m_n);
4066 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
4067 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,
4068 pipe_config->pipe_bpp);
4069 else
4070 dotclock = pipe_config->port_clock;
4071
4072 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
4073 !intel_crtc_has_dp_encoder(crtc_state: pipe_config))
4074 dotclock *= 2;
4075
4076 if (pipe_config->pixel_multiplier)
4077 dotclock /= pipe_config->pixel_multiplier;
4078
4079 return dotclock;
4080}
4081
4082/* Returns the currently programmed mode of the given encoder. */
4083struct drm_display_mode *
4084intel_encoder_current_mode(struct intel_encoder *encoder)
4085{
4086 struct intel_display *display = to_intel_display(encoder);
4087 struct intel_crtc_state *crtc_state;
4088 struct drm_display_mode *mode;
4089 struct intel_crtc *crtc;
4090 enum pipe pipe;
4091
4092 if (!encoder->get_hw_state(encoder, &pipe))
4093 return NULL;
4094
4095 crtc = intel_crtc_for_pipe(display, pipe);
4096
4097 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4098 if (!mode)
4099 return NULL;
4100
4101 crtc_state = intel_crtc_state_alloc(crtc);
4102 if (!crtc_state) {
4103 kfree(objp: mode);
4104 return NULL;
4105 }
4106
4107 if (!intel_crtc_get_pipe_config(crtc_state)) {
4108 intel_crtc_destroy_state(crtc: &crtc->base, state: &crtc_state->uapi);
4109 kfree(objp: mode);
4110 return NULL;
4111 }
4112
4113 intel_encoder_get_config(encoder, crtc_state);
4114
4115 intel_mode_from_crtc_timings(mode, timings: &crtc_state->hw.adjusted_mode);
4116
4117 intel_crtc_destroy_state(crtc: &crtc->base, state: &crtc_state->uapi);
4118
4119 return mode;
4120}
4121
4122static bool encoders_cloneable(const struct intel_encoder *a,
4123 const struct intel_encoder *b)
4124{
4125 /* masks could be asymmetric, so check both ways */
4126 return a == b || (a->cloneable & BIT(b->type) &&
4127 b->cloneable & BIT(a->type));
4128}
4129
4130static bool check_single_encoder_cloning(struct intel_atomic_state *state,
4131 struct intel_crtc *crtc,
4132 struct intel_encoder *encoder)
4133{
4134 struct intel_encoder *source_encoder;
4135 struct drm_connector *connector;
4136 struct drm_connector_state *connector_state;
4137 int i;
4138
4139 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4140 if (connector_state->crtc != &crtc->base)
4141 continue;
4142
4143 source_encoder =
4144 to_intel_encoder(connector_state->best_encoder);
4145 if (!encoders_cloneable(a: encoder, b: source_encoder))
4146 return false;
4147 }
4148
4149 return true;
4150}
4151
4152static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
4153{
4154 const struct drm_display_mode *pipe_mode =
4155 &crtc_state->hw.pipe_mode;
4156 int linetime_wm;
4157
4158 if (!crtc_state->hw.enable)
4159 return 0;
4160
4161 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4162 pipe_mode->crtc_clock);
4163
4164 return min(linetime_wm, 0x1ff);
4165}
4166
4167static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
4168 const struct intel_cdclk_state *cdclk_state)
4169{
4170 const struct drm_display_mode *pipe_mode =
4171 &crtc_state->hw.pipe_mode;
4172 int linetime_wm;
4173
4174 if (!crtc_state->hw.enable)
4175 return 0;
4176
4177 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4178 intel_cdclk_logical(cdclk_state));
4179
4180 return min(linetime_wm, 0x1ff);
4181}
4182
4183static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
4184{
4185 struct intel_display *display = to_intel_display(crtc_state);
4186 const struct drm_display_mode *pipe_mode =
4187 &crtc_state->hw.pipe_mode;
4188 int linetime_wm;
4189
4190 if (!crtc_state->hw.enable)
4191 return 0;
4192
4193 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
4194 crtc_state->pixel_rate);
4195
4196 /* Display WA #1135: BXT:ALL GLK:ALL */
4197 if ((display->platform.geminilake || display->platform.broxton) &&
4198 skl_watermark_ipc_enabled(display))
4199 linetime_wm /= 2;
4200
4201 return min(linetime_wm, 0x1ff);
4202}
4203
4204static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
4205 struct intel_crtc *crtc)
4206{
4207 struct intel_display *display = to_intel_display(state);
4208 struct intel_crtc_state *crtc_state =
4209 intel_atomic_get_new_crtc_state(state, crtc);
4210 const struct intel_cdclk_state *cdclk_state;
4211
4212 if (DISPLAY_VER(display) >= 9)
4213 crtc_state->linetime = skl_linetime_wm(crtc_state);
4214 else
4215 crtc_state->linetime = hsw_linetime_wm(crtc_state);
4216
4217 if (!hsw_crtc_supports_ips(crtc))
4218 return 0;
4219
4220 cdclk_state = intel_atomic_get_cdclk_state(state);
4221 if (IS_ERR(ptr: cdclk_state))
4222 return PTR_ERR(ptr: cdclk_state);
4223
4224 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
4225 cdclk_state);
4226
4227 return 0;
4228}
4229
4230static int intel_crtc_atomic_check(struct intel_atomic_state *state,
4231 struct intel_crtc *crtc)
4232{
4233 struct intel_display *display = to_intel_display(crtc);
4234 struct intel_crtc_state *crtc_state =
4235 intel_atomic_get_new_crtc_state(state, crtc);
4236 int ret;
4237
4238 if (DISPLAY_VER(display) < 5 && !display->platform.g4x &&
4239 intel_crtc_needs_modeset(crtc_state) &&
4240 !crtc_state->hw.active)
4241 crtc_state->update_wm_post = true;
4242
4243 if (intel_crtc_needs_modeset(crtc_state)) {
4244 ret = intel_dpll_crtc_get_dpll(state, crtc);
4245 if (ret)
4246 return ret;
4247 }
4248
4249 ret = intel_color_check(state, crtc);
4250 if (ret)
4251 return ret;
4252
4253 ret = intel_wm_compute(state, crtc);
4254 if (ret) {
4255 drm_dbg_kms(display->drm,
4256 "[CRTC:%d:%s] watermarks are invalid\n",
4257 crtc->base.base.id, crtc->base.name);
4258 return ret;
4259 }
4260
4261 if (DISPLAY_VER(display) >= 9) {
4262 if (intel_crtc_needs_modeset(crtc_state) ||
4263 intel_crtc_needs_fastset(crtc_state)) {
4264 ret = skl_update_scaler_crtc(crtc_state);
4265 if (ret)
4266 return ret;
4267 }
4268
4269 ret = intel_atomic_setup_scalers(state, crtc);
4270 if (ret)
4271 return ret;
4272 }
4273
4274 if (HAS_IPS(display)) {
4275 ret = hsw_ips_compute_config(state, crtc);
4276 if (ret)
4277 return ret;
4278 }
4279
4280 if (DISPLAY_VER(display) >= 9 ||
4281 display->platform.broadwell || display->platform.haswell) {
4282 ret = hsw_compute_linetime_wm(state, crtc);
4283 if (ret)
4284 return ret;
4285
4286 }
4287
4288 ret = intel_psr2_sel_fetch_update(state, crtc);
4289 if (ret)
4290 return ret;
4291
4292 return 0;
4293}
4294
4295static int
4296compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
4297 struct intel_crtc_state *crtc_state)
4298{
4299 struct intel_display *display = to_intel_display(crtc_state);
4300 struct drm_connector *connector = conn_state->connector;
4301 const struct drm_display_info *info = &connector->display_info;
4302 int bpp;
4303
4304 switch (conn_state->max_bpc) {
4305 case 6 ... 7:
4306 bpp = 6 * 3;
4307 break;
4308 case 8 ... 9:
4309 bpp = 8 * 3;
4310 break;
4311 case 10 ... 11:
4312 bpp = 10 * 3;
4313 break;
4314 case 12 ... 16:
4315 bpp = 12 * 3;
4316 break;
4317 default:
4318 MISSING_CASE(conn_state->max_bpc);
4319 return -EINVAL;
4320 }
4321
4322 if (bpp < crtc_state->pipe_bpp) {
4323 drm_dbg_kms(display->drm,
4324 "[CONNECTOR:%d:%s] Limiting display bpp to %d "
4325 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4326 connector->base.id, connector->name,
4327 bpp, 3 * info->bpc,
4328 3 * conn_state->max_requested_bpc,
4329 crtc_state->pipe_bpp);
4330
4331 crtc_state->pipe_bpp = bpp;
4332 }
4333
4334 return 0;
4335}
4336
4337int intel_display_min_pipe_bpp(void)
4338{
4339 return 6 * 3;
4340}
4341
4342int intel_display_max_pipe_bpp(struct intel_display *display)
4343{
4344 if (display->platform.g4x || display->platform.valleyview ||
4345 display->platform.cherryview)
4346 return 10*3;
4347 else if (DISPLAY_VER(display) >= 5)
4348 return 12*3;
4349 else
4350 return 8*3;
4351}
4352
4353static int
4354compute_baseline_pipe_bpp(struct intel_atomic_state *state,
4355 struct intel_crtc *crtc)
4356{
4357 struct intel_display *display = to_intel_display(crtc);
4358 struct intel_crtc_state *crtc_state =
4359 intel_atomic_get_new_crtc_state(state, crtc);
4360 struct drm_connector *connector;
4361 struct drm_connector_state *connector_state;
4362 int i;
4363
4364 crtc_state->pipe_bpp = intel_display_max_pipe_bpp(display);
4365
4366 /* Clamp display bpp to connector max bpp */
4367 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4368 int ret;
4369
4370 if (connector_state->crtc != &crtc->base)
4371 continue;
4372
4373 ret = compute_sink_pipe_bpp(conn_state: connector_state, crtc_state);
4374 if (ret)
4375 return ret;
4376 }
4377
4378 return 0;
4379}
4380
4381static bool check_digital_port_conflicts(struct intel_atomic_state *state)
4382{
4383 struct intel_display *display = to_intel_display(state);
4384 struct drm_connector *connector;
4385 struct drm_connector_list_iter conn_iter;
4386 unsigned int used_ports = 0;
4387 unsigned int used_mst_ports = 0;
4388 bool ret = true;
4389
4390 /*
4391 * We're going to peek into connector->state,
4392 * hence connection_mutex must be held.
4393 */
4394 drm_modeset_lock_assert_held(lock: &display->drm->mode_config.connection_mutex);
4395
4396 /*
4397 * Walk the connector list instead of the encoder
4398 * list to detect the problem on ddi platforms
4399 * where there's just one encoder per digital port.
4400 */
4401 drm_connector_list_iter_begin(dev: display->drm, iter: &conn_iter);
4402 drm_for_each_connector_iter(connector, &conn_iter) {
4403 struct drm_connector_state *connector_state;
4404 struct intel_encoder *encoder;
4405
4406 connector_state =
4407 drm_atomic_get_new_connector_state(state: &state->base,
4408 connector);
4409 if (!connector_state)
4410 connector_state = connector->state;
4411
4412 if (!connector_state->best_encoder)
4413 continue;
4414
4415 encoder = to_intel_encoder(connector_state->best_encoder);
4416
4417 drm_WARN_ON(display->drm, !connector_state->crtc);
4418
4419 switch (encoder->type) {
4420 case INTEL_OUTPUT_DDI:
4421 if (drm_WARN_ON(display->drm, !HAS_DDI(display)))
4422 break;
4423 fallthrough;
4424 case INTEL_OUTPUT_DP:
4425 case INTEL_OUTPUT_HDMI:
4426 case INTEL_OUTPUT_EDP:
4427 /* the same port mustn't appear more than once */
4428 if (used_ports & BIT(encoder->port))
4429 ret = false;
4430
4431 used_ports |= BIT(encoder->port);
4432 break;
4433 case INTEL_OUTPUT_DP_MST:
4434 used_mst_ports |=
4435 1 << encoder->port;
4436 break;
4437 default:
4438 break;
4439 }
4440 }
4441 drm_connector_list_iter_end(iter: &conn_iter);
4442
4443 /* can't mix MST and SST/HDMI on the same port */
4444 if (used_ports & used_mst_ports)
4445 return false;
4446
4447 return ret;
4448}
4449
4450static void
4451intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
4452 struct intel_crtc *crtc)
4453{
4454 struct intel_crtc_state *crtc_state =
4455 intel_atomic_get_new_crtc_state(state, crtc);
4456
4457 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
4458
4459 drm_property_replace_blob(blob: &crtc_state->hw.degamma_lut,
4460 new_blob: crtc_state->uapi.degamma_lut);
4461 drm_property_replace_blob(blob: &crtc_state->hw.gamma_lut,
4462 new_blob: crtc_state->uapi.gamma_lut);
4463 drm_property_replace_blob(blob: &crtc_state->hw.ctm,
4464 new_blob: crtc_state->uapi.ctm);
4465}
4466
4467static void
4468intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
4469 struct intel_crtc *crtc)
4470{
4471 struct intel_crtc_state *crtc_state =
4472 intel_atomic_get_new_crtc_state(state, crtc);
4473
4474 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
4475
4476 crtc_state->hw.enable = crtc_state->uapi.enable;
4477 crtc_state->hw.active = crtc_state->uapi.active;
4478 drm_mode_copy(dst: &crtc_state->hw.mode,
4479 src: &crtc_state->uapi.mode);
4480 drm_mode_copy(dst: &crtc_state->hw.adjusted_mode,
4481 src: &crtc_state->uapi.adjusted_mode);
4482 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
4483
4484 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
4485}
4486
4487static void
4488copy_joiner_crtc_state_nomodeset(struct intel_atomic_state *state,
4489 struct intel_crtc *secondary_crtc)
4490{
4491 struct intel_crtc_state *secondary_crtc_state =
4492 intel_atomic_get_new_crtc_state(state, crtc: secondary_crtc);
4493 struct intel_crtc *primary_crtc = intel_primary_crtc(crtc_state: secondary_crtc_state);
4494 const struct intel_crtc_state *primary_crtc_state =
4495 intel_atomic_get_new_crtc_state(state, crtc: primary_crtc);
4496
4497 drm_property_replace_blob(blob: &secondary_crtc_state->hw.degamma_lut,
4498 new_blob: primary_crtc_state->hw.degamma_lut);
4499 drm_property_replace_blob(blob: &secondary_crtc_state->hw.gamma_lut,
4500 new_blob: primary_crtc_state->hw.gamma_lut);
4501 drm_property_replace_blob(blob: &secondary_crtc_state->hw.ctm,
4502 new_blob: primary_crtc_state->hw.ctm);
4503
4504 secondary_crtc_state->uapi.color_mgmt_changed = primary_crtc_state->uapi.color_mgmt_changed;
4505}
4506
4507static int
4508copy_joiner_crtc_state_modeset(struct intel_atomic_state *state,
4509 struct intel_crtc *secondary_crtc)
4510{
4511 struct intel_crtc_state *secondary_crtc_state =
4512 intel_atomic_get_new_crtc_state(state, crtc: secondary_crtc);
4513 struct intel_crtc *primary_crtc = intel_primary_crtc(crtc_state: secondary_crtc_state);
4514 const struct intel_crtc_state *primary_crtc_state =
4515 intel_atomic_get_new_crtc_state(state, crtc: primary_crtc);
4516 struct intel_crtc_state *saved_state;
4517
4518 WARN_ON(primary_crtc_state->joiner_pipes !=
4519 secondary_crtc_state->joiner_pipes);
4520
4521 saved_state = kmemdup(primary_crtc_state, sizeof(*saved_state), GFP_KERNEL);
4522 if (!saved_state)
4523 return -ENOMEM;
4524
4525 /* preserve some things from the slave's original crtc state */
4526 saved_state->uapi = secondary_crtc_state->uapi;
4527 saved_state->scaler_state = secondary_crtc_state->scaler_state;
4528 saved_state->intel_dpll = secondary_crtc_state->intel_dpll;
4529 saved_state->crc_enabled = secondary_crtc_state->crc_enabled;
4530
4531 intel_crtc_free_hw_state(crtc_state: secondary_crtc_state);
4532 if (secondary_crtc_state->dp_tunnel_ref.tunnel)
4533 drm_dp_tunnel_ref_put(tunnel_ref: &secondary_crtc_state->dp_tunnel_ref);
4534 memcpy(to: secondary_crtc_state, from: saved_state, len: sizeof(*secondary_crtc_state));
4535 kfree(objp: saved_state);
4536
4537 /* Re-init hw state */
4538 memset(s: &secondary_crtc_state->hw, c: 0, n: sizeof(secondary_crtc_state->hw));
4539 secondary_crtc_state->hw.enable = primary_crtc_state->hw.enable;
4540 secondary_crtc_state->hw.active = primary_crtc_state->hw.active;
4541 drm_mode_copy(dst: &secondary_crtc_state->hw.mode,
4542 src: &primary_crtc_state->hw.mode);
4543 drm_mode_copy(dst: &secondary_crtc_state->hw.pipe_mode,
4544 src: &primary_crtc_state->hw.pipe_mode);
4545 drm_mode_copy(dst: &secondary_crtc_state->hw.adjusted_mode,
4546 src: &primary_crtc_state->hw.adjusted_mode);
4547 secondary_crtc_state->hw.scaling_filter = primary_crtc_state->hw.scaling_filter;
4548
4549 if (primary_crtc_state->dp_tunnel_ref.tunnel)
4550 drm_dp_tunnel_ref_get(tunnel: primary_crtc_state->dp_tunnel_ref.tunnel,
4551 tunnel_ref: &secondary_crtc_state->dp_tunnel_ref);
4552
4553 copy_joiner_crtc_state_nomodeset(state, secondary_crtc);
4554
4555 secondary_crtc_state->uapi.mode_changed = primary_crtc_state->uapi.mode_changed;
4556 secondary_crtc_state->uapi.connectors_changed = primary_crtc_state->uapi.connectors_changed;
4557 secondary_crtc_state->uapi.active_changed = primary_crtc_state->uapi.active_changed;
4558
4559 WARN_ON(primary_crtc_state->joiner_pipes !=
4560 secondary_crtc_state->joiner_pipes);
4561
4562 return 0;
4563}
4564
4565static int
4566intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
4567 struct intel_crtc *crtc)
4568{
4569 struct intel_display *display = to_intel_display(state);
4570 struct intel_crtc_state *crtc_state =
4571 intel_atomic_get_new_crtc_state(state, crtc);
4572 struct intel_crtc_state *saved_state;
4573
4574 saved_state = intel_crtc_state_alloc(crtc);
4575 if (!saved_state)
4576 return -ENOMEM;
4577
4578 /* free the old crtc_state->hw members */
4579 intel_crtc_free_hw_state(crtc_state);
4580
4581 intel_dp_tunnel_atomic_clear_stream_bw(state, crtc_state);
4582
4583 /* FIXME: before the switch to atomic started, a new pipe_config was
4584 * kzalloc'd. Code that depends on any field being zero should be
4585 * fixed, so that the crtc_state can be safely duplicated. For now,
4586 * only fields that are know to not cause problems are preserved. */
4587
4588 saved_state->uapi = crtc_state->uapi;
4589 saved_state->inherited = crtc_state->inherited;
4590 saved_state->scaler_state = crtc_state->scaler_state;
4591 saved_state->intel_dpll = crtc_state->intel_dpll;
4592 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
4593 memcpy(to: saved_state->icl_port_dplls, from: crtc_state->icl_port_dplls,
4594 len: sizeof(saved_state->icl_port_dplls));
4595 saved_state->crc_enabled = crtc_state->crc_enabled;
4596 if (display->platform.g4x ||
4597 display->platform.valleyview || display->platform.cherryview)
4598 saved_state->wm = crtc_state->wm;
4599
4600 memcpy(to: crtc_state, from: saved_state, len: sizeof(*crtc_state));
4601 kfree(objp: saved_state);
4602
4603 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc);
4604
4605 return 0;
4606}
4607
4608static int
4609intel_modeset_pipe_config(struct intel_atomic_state *state,
4610 struct intel_crtc *crtc,
4611 const struct intel_link_bw_limits *limits)
4612{
4613 struct intel_display *display = to_intel_display(crtc);
4614 struct intel_crtc_state *crtc_state =
4615 intel_atomic_get_new_crtc_state(state, crtc);
4616 struct drm_connector *connector;
4617 struct drm_connector_state *connector_state;
4618 int pipe_src_w, pipe_src_h;
4619 int base_bpp, ret, i;
4620
4621 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
4622
4623 crtc_state->framestart_delay = 1;
4624
4625 /*
4626 * Sanitize sync polarity flags based on requested ones. If neither
4627 * positive or negative polarity is requested, treat this as meaning
4628 * negative polarity.
4629 */
4630 if (!(crtc_state->hw.adjusted_mode.flags &
4631 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
4632 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
4633
4634 if (!(crtc_state->hw.adjusted_mode.flags &
4635 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
4636 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
4637
4638 ret = compute_baseline_pipe_bpp(state, crtc);
4639 if (ret)
4640 return ret;
4641
4642 crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);
4643 crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
4644
4645 if (crtc_state->pipe_bpp > fxp_q4_to_int(val_q4: crtc_state->max_link_bpp_x16)) {
4646 drm_dbg_kms(display->drm,
4647 "[CRTC:%d:%s] Link bpp limited to " FXP_Q4_FMT "\n",
4648 crtc->base.base.id, crtc->base.name,
4649 FXP_Q4_ARGS(crtc_state->max_link_bpp_x16));
4650 crtc_state->bw_constrained = true;
4651 }
4652
4653 base_bpp = crtc_state->pipe_bpp;
4654
4655 /*
4656 * Determine the real pipe dimensions. Note that stereo modes can
4657 * increase the actual pipe size due to the frame doubling and
4658 * insertion of additional space for blanks between the frame. This
4659 * is stored in the crtc timings. We use the requested mode to do this
4660 * computation to clearly distinguish it from the adjusted mode, which
4661 * can be changed by the connectors in the below retry loop.
4662 */
4663 drm_mode_get_hv_timing(mode: &crtc_state->hw.mode,
4664 hdisplay: &pipe_src_w, vdisplay: &pipe_src_h);
4665 drm_rect_init(r: &crtc_state->pipe_src, x: 0, y: 0,
4666 width: pipe_src_w, height: pipe_src_h);
4667
4668 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4669 struct intel_encoder *encoder =
4670 to_intel_encoder(connector_state->best_encoder);
4671
4672 if (connector_state->crtc != &crtc->base)
4673 continue;
4674
4675 if (!check_single_encoder_cloning(state, crtc, encoder)) {
4676 drm_dbg_kms(display->drm,
4677 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
4678 encoder->base.base.id, encoder->base.name);
4679 return -EINVAL;
4680 }
4681
4682 /*
4683 * Determine output_types before calling the .compute_config()
4684 * hooks so that the hooks can use this information safely.
4685 */
4686 if (encoder->compute_output_type)
4687 crtc_state->output_types |=
4688 BIT(encoder->compute_output_type(encoder, crtc_state,
4689 connector_state));
4690 else
4691 crtc_state->output_types |= BIT(encoder->type);
4692 }
4693
4694 /* Ensure the port clock defaults are reset when retrying. */
4695 crtc_state->port_clock = 0;
4696 crtc_state->pixel_multiplier = 1;
4697
4698 /* Fill in default crtc timings, allow encoders to overwrite them. */
4699 drm_mode_set_crtcinfo(p: &crtc_state->hw.adjusted_mode,
4700 CRTC_STEREO_DOUBLE);
4701
4702 /* Pass our mode to the connectors and the CRTC to give them a chance to
4703 * adjust it according to limitations or connector properties, and also
4704 * a chance to reject the mode entirely.
4705 */
4706 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4707 struct intel_encoder *encoder =
4708 to_intel_encoder(connector_state->best_encoder);
4709
4710 if (connector_state->crtc != &crtc->base)
4711 continue;
4712
4713 ret = encoder->compute_config(encoder, crtc_state,
4714 connector_state);
4715 if (ret == -EDEADLK)
4716 return ret;
4717 if (ret < 0) {
4718 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] config failure: %d\n",
4719 encoder->base.base.id, encoder->base.name, ret);
4720 return ret;
4721 }
4722 }
4723
4724 /* Set default port clock if not overwritten by the encoder. Needs to be
4725 * done afterwards in case the encoder adjusts the mode. */
4726 if (!crtc_state->port_clock)
4727 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
4728 * crtc_state->pixel_multiplier;
4729
4730 ret = intel_crtc_compute_config(state, crtc);
4731 if (ret == -EDEADLK)
4732 return ret;
4733 if (ret < 0) {
4734 drm_dbg_kms(display->drm, "[CRTC:%d:%s] config failure: %d\n",
4735 crtc->base.base.id, crtc->base.name, ret);
4736 return ret;
4737 }
4738
4739 /* Dithering seems to not pass-through bits correctly when it should, so
4740 * only enable it on 6bpc panels and when its not a compliance
4741 * test requesting 6bpc video pattern.
4742 */
4743 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
4744 !crtc_state->dither_force_disable;
4745 drm_dbg_kms(display->drm,
4746 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
4747 crtc->base.base.id, crtc->base.name,
4748 base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
4749
4750 return 0;
4751}
4752
4753static int
4754intel_modeset_pipe_config_late(struct intel_atomic_state *state,
4755 struct intel_crtc *crtc)
4756{
4757 struct intel_crtc_state *crtc_state =
4758 intel_atomic_get_new_crtc_state(state, crtc);
4759 struct drm_connector_state *conn_state;
4760 struct drm_connector *connector;
4761 int i;
4762
4763 intel_vrr_compute_config_late(crtc_state);
4764
4765 for_each_new_connector_in_state(&state->base, connector,
4766 conn_state, i) {
4767 struct intel_encoder *encoder =
4768 to_intel_encoder(conn_state->best_encoder);
4769 int ret;
4770
4771 if (conn_state->crtc != &crtc->base ||
4772 !encoder->compute_config_late)
4773 continue;
4774
4775 ret = encoder->compute_config_late(encoder, crtc_state,
4776 conn_state);
4777 if (ret)
4778 return ret;
4779 }
4780
4781 return 0;
4782}
4783
4784bool intel_fuzzy_clock_check(int clock1, int clock2)
4785{
4786 int diff;
4787
4788 if (clock1 == clock2)
4789 return true;
4790
4791 if (!clock1 || !clock2)
4792 return false;
4793
4794 diff = abs(clock1 - clock2);
4795
4796 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
4797 return true;
4798
4799 return false;
4800}
4801
4802static bool
4803intel_compare_link_m_n(const struct intel_link_m_n *m_n,
4804 const struct intel_link_m_n *m2_n2)
4805{
4806 return m_n->tu == m2_n2->tu &&
4807 m_n->data_m == m2_n2->data_m &&
4808 m_n->data_n == m2_n2->data_n &&
4809 m_n->link_m == m2_n2->link_m &&
4810 m_n->link_n == m2_n2->link_n;
4811}
4812
4813static bool
4814intel_compare_infoframe(const union hdmi_infoframe *a,
4815 const union hdmi_infoframe *b)
4816{
4817 return memcmp(a, b, sizeof(*a)) == 0;
4818}
4819
4820static bool
4821intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
4822 const struct drm_dp_vsc_sdp *b)
4823{
4824 return a->pixelformat == b->pixelformat &&
4825 a->colorimetry == b->colorimetry &&
4826 a->bpc == b->bpc &&
4827 a->dynamic_range == b->dynamic_range &&
4828 a->content_type == b->content_type;
4829}
4830
4831static bool
4832intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
4833 const struct drm_dp_as_sdp *b)
4834{
4835 return a->vtotal == b->vtotal &&
4836 a->target_rr == b->target_rr &&
4837 a->duration_incr_ms == b->duration_incr_ms &&
4838 a->duration_decr_ms == b->duration_decr_ms &&
4839 a->mode == b->mode;
4840}
4841
4842static bool
4843intel_compare_buffer(const u8 *a, const u8 *b, size_t len)
4844{
4845 return memcmp(a, b, len) == 0;
4846}
4847
4848static void __printf(5, 6)
4849pipe_config_mismatch(struct drm_printer *p, bool fastset,
4850 const struct intel_crtc *crtc,
4851 const char *name, const char *format, ...)
4852{
4853 struct va_format vaf;
4854 va_list args;
4855
4856 va_start(args, format);
4857 vaf.fmt = format;
4858 vaf.va = &args;
4859
4860 if (fastset)
4861 drm_printf(p, f: "[CRTC:%d:%s] fastset requirement not met in %s %pV\n",
4862 crtc->base.base.id, crtc->base.name, name, &vaf);
4863 else
4864 drm_printf(p, f: "[CRTC:%d:%s] mismatch in %s %pV\n",
4865 crtc->base.base.id, crtc->base.name, name, &vaf);
4866
4867 va_end(args);
4868}
4869
4870static void
4871pipe_config_infoframe_mismatch(struct drm_printer *p, bool fastset,
4872 const struct intel_crtc *crtc,
4873 const char *name,
4874 const union hdmi_infoframe *a,
4875 const union hdmi_infoframe *b)
4876{
4877 struct intel_display *display = to_intel_display(crtc);
4878 const char *loglevel;
4879
4880 if (fastset) {
4881 if (!drm_debug_enabled(DRM_UT_KMS))
4882 return;
4883
4884 loglevel = KERN_DEBUG;
4885 } else {
4886 loglevel = KERN_ERR;
4887 }
4888
4889 pipe_config_mismatch(p, fastset, crtc, name, format: "infoframe");
4890
4891 drm_printf(p, f: "expected:\n");
4892 hdmi_infoframe_log(level: loglevel, dev: display->drm->dev, frame: a);
4893 drm_printf(p, f: "found:\n");
4894 hdmi_infoframe_log(level: loglevel, dev: display->drm->dev, frame: b);
4895}
4896
4897static void
4898pipe_config_dp_vsc_sdp_mismatch(struct drm_printer *p, bool fastset,
4899 const struct intel_crtc *crtc,
4900 const char *name,
4901 const struct drm_dp_vsc_sdp *a,
4902 const struct drm_dp_vsc_sdp *b)
4903{
4904 pipe_config_mismatch(p, fastset, crtc, name, format: "dp vsc sdp");
4905
4906 drm_printf(p, f: "expected:\n");
4907 drm_dp_vsc_sdp_log(p, vsc: a);
4908 drm_printf(p, f: "found:\n");
4909 drm_dp_vsc_sdp_log(p, vsc: b);
4910}
4911
4912static void
4913pipe_config_dp_as_sdp_mismatch(struct drm_printer *p, bool fastset,
4914 const struct intel_crtc *crtc,
4915 const char *name,
4916 const struct drm_dp_as_sdp *a,
4917 const struct drm_dp_as_sdp *b)
4918{
4919 pipe_config_mismatch(p, fastset, crtc, name, format: "dp as sdp");
4920
4921 drm_printf(p, f: "expected:\n");
4922 drm_dp_as_sdp_log(p, as_sdp: a);
4923 drm_printf(p, f: "found:\n");
4924 drm_dp_as_sdp_log(p, as_sdp: b);
4925}
4926
4927/* Returns the length up to and including the last differing byte */
4928static size_t
4929memcmp_diff_len(const u8 *a, const u8 *b, size_t len)
4930{
4931 int i;
4932
4933 for (i = len - 1; i >= 0; i--) {
4934 if (a[i] != b[i])
4935 return i + 1;
4936 }
4937
4938 return 0;
4939}
4940
4941static void
4942pipe_config_buffer_mismatch(struct drm_printer *p, bool fastset,
4943 const struct intel_crtc *crtc,
4944 const char *name,
4945 const u8 *a, const u8 *b, size_t len)
4946{
4947 pipe_config_mismatch(p, fastset, crtc, name, format: "buffer");
4948
4949 /* only dump up to the last difference */
4950 len = memcmp_diff_len(a, b, len);
4951
4952 drm_print_hex_dump(p, prefix: "expected: ", buf: a, len);
4953 drm_print_hex_dump(p, prefix: "found: ", buf: b, len);
4954}
4955
4956static void
4957pipe_config_pll_mismatch(struct drm_printer *p, bool fastset,
4958 const struct intel_crtc *crtc,
4959 const char *name,
4960 const struct intel_dpll_hw_state *a,
4961 const struct intel_dpll_hw_state *b)
4962{
4963 struct intel_display *display = to_intel_display(crtc);
4964
4965 pipe_config_mismatch(p, fastset, crtc, name, format: " "); /* stupid -Werror=format-zero-length */
4966
4967 drm_printf(p, f: "expected:\n");
4968 intel_dpll_dump_hw_state(display, p, dpll_hw_state: a);
4969 drm_printf(p, f: "found:\n");
4970 intel_dpll_dump_hw_state(display, p, dpll_hw_state: b);
4971}
4972
4973static void
4974pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
4975 const struct intel_crtc *crtc,
4976 const char *name,
4977 const struct intel_cx0pll_state *a,
4978 const struct intel_cx0pll_state *b)
4979{
4980 struct intel_display *display = to_intel_display(crtc);
4981 char *chipname = a->use_c10 ? "C10" : "C20";
4982
4983 pipe_config_mismatch(p, fastset, crtc, name, format: chipname);
4984
4985 drm_printf(p, f: "expected:\n");
4986 intel_cx0pll_dump_hw_state(display, hw_state: a);
4987 drm_printf(p, f: "found:\n");
4988 intel_cx0pll_dump_hw_state(display, hw_state: b);
4989}
4990
4991static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state)
4992{
4993 struct intel_display *display = to_intel_display(old_crtc_state);
4994
4995 /*
4996 * Allow fastboot to fix up vblank delay (handled via LRR
4997 * codepaths), a bit dodgy as the registers aren't
4998 * double buffered but seems to be working more or less...
4999 */
5000 return HAS_LRR(display) && old_crtc_state->inherited &&
5001 !intel_crtc_has_type(crtc_state: old_crtc_state, type: INTEL_OUTPUT_DSI);
5002}
5003
5004bool
5005intel_pipe_config_compare(const struct intel_crtc_state *current_config,
5006 const struct intel_crtc_state *pipe_config,
5007 bool fastset)
5008{
5009 struct intel_display *display = to_intel_display(current_config);
5010 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
5011 struct drm_printer p;
5012 u32 exclude_infoframes = 0;
5013 bool ret = true;
5014
5015 if (fastset)
5016 p = drm_dbg_printer(drm: display->drm, category: DRM_UT_KMS, NULL);
5017 else
5018 p = drm_err_printer(drm: display->drm, NULL);
5019
5020#define PIPE_CONF_CHECK_X(name) do { \
5021 if (current_config->name != pipe_config->name) { \
5022 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
5023 __stringify(name) " is bool"); \
5024 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5025 "(expected 0x%08x, found 0x%08x)", \
5026 current_config->name, \
5027 pipe_config->name); \
5028 ret = false; \
5029 } \
5030} while (0)
5031
5032#define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
5033 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
5034 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
5035 __stringify(name) " is bool"); \
5036 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5037 "(expected 0x%08x, found 0x%08x)", \
5038 current_config->name & (mask), \
5039 pipe_config->name & (mask)); \
5040 ret = false; \
5041 } \
5042} while (0)
5043
5044#define PIPE_CONF_CHECK_I(name) do { \
5045 if (current_config->name != pipe_config->name) { \
5046 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
5047 __stringify(name) " is bool"); \
5048 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5049 "(expected %i, found %i)", \
5050 current_config->name, \
5051 pipe_config->name); \
5052 ret = false; \
5053 } \
5054} while (0)
5055
5056#define PIPE_CONF_CHECK_LLI(name) do { \
5057 if (current_config->name != pipe_config->name) { \
5058 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5059 "(expected %lli, found %lli)", \
5060 current_config->name, \
5061 pipe_config->name); \
5062 ret = false; \
5063 } \
5064} while (0)
5065
5066#define PIPE_CONF_CHECK_BOOL(name) do { \
5067 if (current_config->name != pipe_config->name) { \
5068 BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
5069 __stringify(name) " is not bool"); \
5070 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5071 "(expected %s, found %s)", \
5072 str_yes_no(current_config->name), \
5073 str_yes_no(pipe_config->name)); \
5074 ret = false; \
5075 } \
5076} while (0)
5077
5078#define PIPE_CONF_CHECK_P(name) do { \
5079 if (current_config->name != pipe_config->name) { \
5080 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5081 "(expected %p, found %p)", \
5082 current_config->name, \
5083 pipe_config->name); \
5084 ret = false; \
5085 } \
5086} while (0)
5087
5088#define PIPE_CONF_CHECK_M_N(name) do { \
5089 if (!intel_compare_link_m_n(&current_config->name, \
5090 &pipe_config->name)) { \
5091 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5092 "(expected tu %i data %i/%i link %i/%i, " \
5093 "found tu %i, data %i/%i link %i/%i)", \
5094 current_config->name.tu, \
5095 current_config->name.data_m, \
5096 current_config->name.data_n, \
5097 current_config->name.link_m, \
5098 current_config->name.link_n, \
5099 pipe_config->name.tu, \
5100 pipe_config->name.data_m, \
5101 pipe_config->name.data_n, \
5102 pipe_config->name.link_m, \
5103 pipe_config->name.link_n); \
5104 ret = false; \
5105 } \
5106} while (0)
5107
5108#define PIPE_CONF_CHECK_PLL(name) do { \
5109 if (!intel_dpll_compare_hw_state(display, &current_config->name, \
5110 &pipe_config->name)) { \
5111 pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \
5112 &current_config->name, \
5113 &pipe_config->name); \
5114 ret = false; \
5115 } \
5116} while (0)
5117
5118#define PIPE_CONF_CHECK_PLL_CX0(name) do { \
5119 if (!intel_cx0pll_compare_hw_state(&current_config->name, \
5120 &pipe_config->name)) { \
5121 pipe_config_cx0pll_mismatch(&p, fastset, crtc, __stringify(name), \
5122 &current_config->name, \
5123 &pipe_config->name); \
5124 ret = false; \
5125 } \
5126} while (0)
5127
5128#define PIPE_CONF_CHECK_TIMINGS(name) do { \
5129 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
5130 PIPE_CONF_CHECK_I(name.crtc_htotal); \
5131 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
5132 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
5133 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
5134 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
5135 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5136 if (!fastset || !allow_vblank_delay_fastset(current_config)) \
5137 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5138 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
5139 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5140 if (!fastset || !pipe_config->update_lrr) { \
5141 PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5142 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5143 } \
5144} while (0)
5145
5146#define PIPE_CONF_CHECK_RECT(name) do { \
5147 PIPE_CONF_CHECK_I(name.x1); \
5148 PIPE_CONF_CHECK_I(name.x2); \
5149 PIPE_CONF_CHECK_I(name.y1); \
5150 PIPE_CONF_CHECK_I(name.y2); \
5151} while (0)
5152
5153#define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5154 if ((current_config->name ^ pipe_config->name) & (mask)) { \
5155 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5156 "(%x) (expected %i, found %i)", \
5157 (mask), \
5158 current_config->name & (mask), \
5159 pipe_config->name & (mask)); \
5160 ret = false; \
5161 } \
5162} while (0)
5163
5164#define PIPE_CONF_CHECK_INFOFRAME(name) do { \
5165 if (!intel_compare_infoframe(&current_config->infoframes.name, \
5166 &pipe_config->infoframes.name)) { \
5167 pipe_config_infoframe_mismatch(&p, fastset, crtc, __stringify(name), \
5168 &current_config->infoframes.name, \
5169 &pipe_config->infoframes.name); \
5170 ret = false; \
5171 } \
5172} while (0)
5173
5174#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5175 if (!intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
5176 &pipe_config->infoframes.name)) { \
5177 pipe_config_dp_vsc_sdp_mismatch(&p, fastset, crtc, __stringify(name), \
5178 &current_config->infoframes.name, \
5179 &pipe_config->infoframes.name); \
5180 ret = false; \
5181 } \
5182} while (0)
5183
5184#define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \
5185 if (!intel_compare_dp_as_sdp(&current_config->infoframes.name, \
5186 &pipe_config->infoframes.name)) { \
5187 pipe_config_dp_as_sdp_mismatch(&p, fastset, crtc, __stringify(name), \
5188 &current_config->infoframes.name, \
5189 &pipe_config->infoframes.name); \
5190 ret = false; \
5191 } \
5192} while (0)
5193
5194#define PIPE_CONF_CHECK_BUFFER(name, len) do { \
5195 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
5196 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
5197 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
5198 pipe_config_buffer_mismatch(&p, fastset, crtc, __stringify(name), \
5199 current_config->name, \
5200 pipe_config->name, \
5201 (len)); \
5202 ret = false; \
5203 } \
5204} while (0)
5205
5206#define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
5207 if (current_config->gamma_mode == pipe_config->gamma_mode && \
5208 !intel_color_lut_equal(current_config, \
5209 current_config->lut, pipe_config->lut, \
5210 is_pre_csc_lut)) { \
5211 pipe_config_mismatch(&p, fastset, crtc, __stringify(lut), \
5212 "hw_state doesn't match sw_state"); \
5213 ret = false; \
5214 } \
5215} while (0)
5216
5217#define PIPE_CONF_CHECK_CSC(name) do { \
5218 PIPE_CONF_CHECK_X(name.preoff[0]); \
5219 PIPE_CONF_CHECK_X(name.preoff[1]); \
5220 PIPE_CONF_CHECK_X(name.preoff[2]); \
5221 PIPE_CONF_CHECK_X(name.coeff[0]); \
5222 PIPE_CONF_CHECK_X(name.coeff[1]); \
5223 PIPE_CONF_CHECK_X(name.coeff[2]); \
5224 PIPE_CONF_CHECK_X(name.coeff[3]); \
5225 PIPE_CONF_CHECK_X(name.coeff[4]); \
5226 PIPE_CONF_CHECK_X(name.coeff[5]); \
5227 PIPE_CONF_CHECK_X(name.coeff[6]); \
5228 PIPE_CONF_CHECK_X(name.coeff[7]); \
5229 PIPE_CONF_CHECK_X(name.coeff[8]); \
5230 PIPE_CONF_CHECK_X(name.postoff[0]); \
5231 PIPE_CONF_CHECK_X(name.postoff[1]); \
5232 PIPE_CONF_CHECK_X(name.postoff[2]); \
5233} while (0)
5234
5235#define PIPE_CONF_QUIRK(quirk) \
5236 ((current_config->quirks | pipe_config->quirks) & (quirk))
5237
5238 PIPE_CONF_CHECK_BOOL(hw.enable);
5239 PIPE_CONF_CHECK_BOOL(hw.active);
5240
5241 PIPE_CONF_CHECK_I(cpu_transcoder);
5242 PIPE_CONF_CHECK_I(mst_master_transcoder);
5243
5244 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
5245 PIPE_CONF_CHECK_I(fdi_lanes);
5246 PIPE_CONF_CHECK_M_N(fdi_m_n);
5247
5248 PIPE_CONF_CHECK_I(lane_count);
5249 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
5250
5251 PIPE_CONF_CHECK_I(min_hblank);
5252
5253 if (HAS_DOUBLE_BUFFERED_M_N(display)) {
5254 if (!fastset || !pipe_config->update_m_n)
5255 PIPE_CONF_CHECK_M_N(dp_m_n);
5256 } else {
5257 PIPE_CONF_CHECK_M_N(dp_m_n);
5258 PIPE_CONF_CHECK_M_N(dp_m2_n2);
5259 }
5260
5261 PIPE_CONF_CHECK_X(output_types);
5262
5263 PIPE_CONF_CHECK_I(framestart_delay);
5264 PIPE_CONF_CHECK_I(msa_timing_delay);
5265
5266 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
5267 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
5268
5269 PIPE_CONF_CHECK_I(pixel_multiplier);
5270
5271 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5272 DRM_MODE_FLAG_INTERLACE);
5273
5274 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
5275 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5276 DRM_MODE_FLAG_PHSYNC);
5277 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5278 DRM_MODE_FLAG_NHSYNC);
5279 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5280 DRM_MODE_FLAG_PVSYNC);
5281 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5282 DRM_MODE_FLAG_NVSYNC);
5283 }
5284
5285 PIPE_CONF_CHECK_I(output_format);
5286 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
5287 if ((DISPLAY_VER(display) < 8 && !display->platform.haswell) ||
5288 display->platform.valleyview || display->platform.cherryview)
5289 PIPE_CONF_CHECK_BOOL(limited_color_range);
5290
5291 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
5292 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
5293 PIPE_CONF_CHECK_BOOL(has_infoframe);
5294 PIPE_CONF_CHECK_BOOL(enhanced_framing);
5295 PIPE_CONF_CHECK_BOOL(fec_enable);
5296
5297 if (!fastset) {
5298 PIPE_CONF_CHECK_BOOL(has_audio);
5299 PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES);
5300 }
5301
5302 PIPE_CONF_CHECK_X(gmch_pfit.control);
5303 /* pfit ratios are autocomputed by the hw on gen4+ */
5304 if (DISPLAY_VER(display) < 4)
5305 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
5306 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5307
5308 /*
5309 * Changing the EDP transcoder input mux
5310 * (A_ONOFF vs. A_ON) requires a full modeset.
5311 */
5312 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
5313
5314 if (!fastset) {
5315 PIPE_CONF_CHECK_RECT(pipe_src);
5316
5317 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
5318 PIPE_CONF_CHECK_RECT(pch_pfit.dst);
5319
5320 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
5321 PIPE_CONF_CHECK_I(pixel_rate);
5322
5323 PIPE_CONF_CHECK_X(gamma_mode);
5324 if (display->platform.cherryview)
5325 PIPE_CONF_CHECK_X(cgm_mode);
5326 else
5327 PIPE_CONF_CHECK_X(csc_mode);
5328 PIPE_CONF_CHECK_BOOL(gamma_enable);
5329 PIPE_CONF_CHECK_BOOL(csc_enable);
5330 PIPE_CONF_CHECK_BOOL(wgc_enable);
5331
5332 PIPE_CONF_CHECK_I(linetime);
5333 PIPE_CONF_CHECK_I(ips_linetime);
5334
5335 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true);
5336 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false);
5337
5338 PIPE_CONF_CHECK_CSC(csc);
5339 PIPE_CONF_CHECK_CSC(output_csc);
5340 }
5341
5342 PIPE_CONF_CHECK_BOOL(double_wide);
5343
5344 if (display->dpll.mgr)
5345 PIPE_CONF_CHECK_P(intel_dpll);
5346
5347 /* FIXME convert everything over the dpll_mgr */
5348 if (display->dpll.mgr || HAS_GMCH(display))
5349 PIPE_CONF_CHECK_PLL(dpll_hw_state);
5350
5351 /* FIXME convert MTL+ platforms over to dpll_mgr */
5352 if (DISPLAY_VER(display) >= 14)
5353 PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);
5354
5355 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5356 PIPE_CONF_CHECK_X(dsi_pll.div);
5357
5358 if (display->platform.g4x || DISPLAY_VER(display) >= 5)
5359 PIPE_CONF_CHECK_I(pipe_bpp);
5360
5361 if (!fastset || !pipe_config->update_m_n) {
5362 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
5363 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
5364 }
5365 PIPE_CONF_CHECK_I(port_clock);
5366
5367 PIPE_CONF_CHECK_I(min_voltage_level);
5368
5369 if (current_config->has_psr || pipe_config->has_psr)
5370 exclude_infoframes |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
5371
5372 if (current_config->vrr.enable || pipe_config->vrr.enable)
5373 exclude_infoframes |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
5374
5375 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, ~exclude_infoframes);
5376 PIPE_CONF_CHECK_X(infoframes.gcp);
5377 PIPE_CONF_CHECK_INFOFRAME(avi);
5378 PIPE_CONF_CHECK_INFOFRAME(spd);
5379 PIPE_CONF_CHECK_INFOFRAME(hdmi);
5380 if (!fastset) {
5381 PIPE_CONF_CHECK_INFOFRAME(drm);
5382 PIPE_CONF_CHECK_DP_AS_SDP(as_sdp);
5383 }
5384 PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5385
5386 PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
5387 PIPE_CONF_CHECK_I(master_transcoder);
5388 PIPE_CONF_CHECK_X(joiner_pipes);
5389
5390 PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);
5391 PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);
5392 PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);
5393 PIPE_CONF_CHECK_BOOL(dsc.config.native_422);
5394 PIPE_CONF_CHECK_BOOL(dsc.config.native_420);
5395 PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);
5396 PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);
5397 PIPE_CONF_CHECK_I(dsc.config.bits_per_component);
5398 PIPE_CONF_CHECK_I(dsc.config.pic_width);
5399 PIPE_CONF_CHECK_I(dsc.config.pic_height);
5400 PIPE_CONF_CHECK_I(dsc.config.slice_width);
5401 PIPE_CONF_CHECK_I(dsc.config.slice_height);
5402 PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);
5403 PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);
5404 PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);
5405 PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);
5406 PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);
5407 PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);
5408 PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);
5409 PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);
5410 PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);
5411 PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);
5412 PIPE_CONF_CHECK_I(dsc.config.initial_offset);
5413 PIPE_CONF_CHECK_I(dsc.config.final_offset);
5414 PIPE_CONF_CHECK_I(dsc.config.rc_model_size);
5415 PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);
5416 PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);
5417 PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);
5418 PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);
5419 PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
5420
5421 PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
5422 PIPE_CONF_CHECK_I(dsc.num_streams);
5423 PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
5424
5425 PIPE_CONF_CHECK_BOOL(splitter.enable);
5426 PIPE_CONF_CHECK_I(splitter.link_count);
5427 PIPE_CONF_CHECK_I(splitter.pixel_overlap);
5428
5429 if (!fastset) {
5430 PIPE_CONF_CHECK_BOOL(vrr.enable);
5431 PIPE_CONF_CHECK_I(vrr.vmin);
5432 PIPE_CONF_CHECK_I(vrr.vmax);
5433 PIPE_CONF_CHECK_I(vrr.flipline);
5434 PIPE_CONF_CHECK_I(vrr.vsync_start);
5435 PIPE_CONF_CHECK_I(vrr.vsync_end);
5436 PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
5437 PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
5438 PIPE_CONF_CHECK_BOOL(cmrr.enable);
5439 }
5440
5441 if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
5442 PIPE_CONF_CHECK_I(vrr.pipeline_full);
5443 PIPE_CONF_CHECK_I(vrr.guardband);
5444 }
5445
5446#undef PIPE_CONF_CHECK_X
5447#undef PIPE_CONF_CHECK_I
5448#undef PIPE_CONF_CHECK_LLI
5449#undef PIPE_CONF_CHECK_BOOL
5450#undef PIPE_CONF_CHECK_P
5451#undef PIPE_CONF_CHECK_FLAGS
5452#undef PIPE_CONF_CHECK_COLOR_LUT
5453#undef PIPE_CONF_CHECK_TIMINGS
5454#undef PIPE_CONF_CHECK_RECT
5455#undef PIPE_CONF_QUIRK
5456
5457 return ret;
5458}
5459
5460static void
5461intel_verify_planes(struct intel_atomic_state *state)
5462{
5463 struct intel_plane *plane;
5464 const struct intel_plane_state *plane_state;
5465 int i;
5466
5467 for_each_new_intel_plane_in_state(state, plane,
5468 plane_state, i)
5469 assert_plane(plane, state: plane_state->is_y_plane ||
5470 plane_state->uapi.visible);
5471}
5472
5473static int intel_modeset_pipe(struct intel_atomic_state *state,
5474 struct intel_crtc_state *crtc_state,
5475 const char *reason)
5476{
5477 struct intel_display *display = to_intel_display(state);
5478 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5479 int ret;
5480
5481 drm_dbg_kms(display->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
5482 crtc->base.base.id, crtc->base.name, reason);
5483
5484 ret = drm_atomic_add_affected_connectors(state: &state->base,
5485 crtc: &crtc->base);
5486 if (ret)
5487 return ret;
5488
5489 ret = intel_dp_tunnel_atomic_add_state_for_crtc(state, crtc);
5490 if (ret)
5491 return ret;
5492
5493 ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc);
5494 if (ret)
5495 return ret;
5496
5497 ret = intel_plane_add_affected(state, crtc);
5498 if (ret)
5499 return ret;
5500
5501 crtc_state->uapi.mode_changed = true;
5502
5503 return 0;
5504}
5505
5506/**
5507 * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
5508 * @state: intel atomic state
5509 * @reason: the reason for the full modeset
5510 * @mask: mask of pipes to modeset
5511 *
5512 * Add pipes in @mask to @state and force a full modeset on the enabled ones
5513 * due to the description in @reason.
5514 * This function can be called only before new plane states are computed.
5515 *
5516 * Returns 0 in case of success, negative error code otherwise.
5517 */
5518int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
5519 const char *reason, u8 mask)
5520{
5521 struct intel_display *display = to_intel_display(state);
5522 struct intel_crtc *crtc;
5523
5524 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mask) {
5525 struct intel_crtc_state *crtc_state;
5526 int ret;
5527
5528 crtc_state = intel_atomic_get_crtc_state(state: &state->base, crtc);
5529 if (IS_ERR(ptr: crtc_state))
5530 return PTR_ERR(ptr: crtc_state);
5531
5532 if (!crtc_state->hw.enable ||
5533 intel_crtc_needs_modeset(crtc_state))
5534 continue;
5535
5536 ret = intel_modeset_pipe(state, crtc_state, reason);
5537 if (ret)
5538 return ret;
5539 }
5540
5541 return 0;
5542}
5543
5544static void
5545intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state)
5546{
5547 crtc_state->uapi.mode_changed = true;
5548
5549 crtc_state->update_pipe = false;
5550 crtc_state->update_m_n = false;
5551 crtc_state->update_lrr = false;
5552}
5553
5554/**
5555 * intel_modeset_all_pipes_late - force a full modeset on all pipes
5556 * @state: intel atomic state
5557 * @reason: the reason for the full modeset
5558 *
5559 * Add all pipes to @state and force a full modeset on the active ones due to
5560 * the description in @reason.
5561 * This function can be called only after new plane states are computed already.
5562 *
5563 * Returns 0 in case of success, negative error code otherwise.
5564 */
5565int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
5566 const char *reason)
5567{
5568 struct intel_display *display = to_intel_display(state);
5569 struct intel_crtc *crtc;
5570
5571 for_each_intel_crtc(display->drm, crtc) {
5572 struct intel_crtc_state *crtc_state;
5573 int ret;
5574
5575 crtc_state = intel_atomic_get_crtc_state(state: &state->base, crtc);
5576 if (IS_ERR(ptr: crtc_state))
5577 return PTR_ERR(ptr: crtc_state);
5578
5579 if (!crtc_state->hw.active ||
5580 intel_crtc_needs_modeset(crtc_state))
5581 continue;
5582
5583 ret = intel_modeset_pipe(state, crtc_state, reason);
5584 if (ret)
5585 return ret;
5586
5587 intel_crtc_flag_modeset(crtc_state);
5588
5589 crtc_state->update_planes |= crtc_state->active_planes;
5590 crtc_state->async_flip_planes = 0;
5591 crtc_state->do_async_flip = false;
5592 }
5593
5594 return 0;
5595}
5596
5597int intel_modeset_commit_pipes(struct intel_display *display,
5598 u8 pipe_mask,
5599 struct drm_modeset_acquire_ctx *ctx)
5600{
5601 struct drm_atomic_state *state;
5602 struct intel_crtc *crtc;
5603 int ret;
5604
5605 state = drm_atomic_state_alloc(dev: display->drm);
5606 if (!state)
5607 return -ENOMEM;
5608
5609 state->acquire_ctx = ctx;
5610 to_intel_atomic_state(state)->internal = true;
5611
5612 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {
5613 struct intel_crtc_state *crtc_state =
5614 intel_atomic_get_crtc_state(state, crtc);
5615
5616 if (IS_ERR(ptr: crtc_state)) {
5617 ret = PTR_ERR(ptr: crtc_state);
5618 goto out;
5619 }
5620
5621 crtc_state->uapi.connectors_changed = true;
5622 }
5623
5624 ret = drm_atomic_commit(state);
5625out:
5626 drm_atomic_state_put(state);
5627
5628 return ret;
5629}
5630
5631/*
5632 * This implements the workaround described in the "notes" section of the mode
5633 * set sequence documentation. When going from no pipes or single pipe to
5634 * multiple pipes, and planes are enabled after the pipe, we need to wait at
5635 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
5636 */
5637static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
5638{
5639 struct intel_crtc_state *crtc_state;
5640 struct intel_crtc *crtc;
5641 struct intel_crtc_state *first_crtc_state = NULL;
5642 struct intel_crtc_state *other_crtc_state = NULL;
5643 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
5644 int i;
5645
5646 /* look at all crtc's that are going to be enabled in during modeset */
5647 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5648 if (!crtc_state->hw.active ||
5649 !intel_crtc_needs_modeset(crtc_state))
5650 continue;
5651
5652 if (first_crtc_state) {
5653 other_crtc_state = crtc_state;
5654 break;
5655 } else {
5656 first_crtc_state = crtc_state;
5657 first_pipe = crtc->pipe;
5658 }
5659 }
5660
5661 /* No workaround needed? */
5662 if (!first_crtc_state)
5663 return 0;
5664
5665 /* w/a possibly needed, check how many crtc's are already enabled. */
5666 for_each_intel_crtc(state->base.dev, crtc) {
5667 crtc_state = intel_atomic_get_crtc_state(state: &state->base, crtc);
5668 if (IS_ERR(ptr: crtc_state))
5669 return PTR_ERR(ptr: crtc_state);
5670
5671 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
5672
5673 if (!crtc_state->hw.active ||
5674 intel_crtc_needs_modeset(crtc_state))
5675 continue;
5676
5677 /* 2 or more enabled crtcs means no need for w/a */
5678 if (enabled_pipe != INVALID_PIPE)
5679 return 0;
5680
5681 enabled_pipe = crtc->pipe;
5682 }
5683
5684 if (enabled_pipe != INVALID_PIPE)
5685 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
5686 else if (other_crtc_state)
5687 other_crtc_state->hsw_workaround_pipe = first_pipe;
5688
5689 return 0;
5690}
5691
5692u8 intel_calc_active_pipes(struct intel_atomic_state *state,
5693 u8 active_pipes)
5694{
5695 const struct intel_crtc_state *crtc_state;
5696 struct intel_crtc *crtc;
5697 int i;
5698
5699 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5700 if (crtc_state->hw.active)
5701 active_pipes |= BIT(crtc->pipe);
5702 else
5703 active_pipes &= ~BIT(crtc->pipe);
5704 }
5705
5706 return active_pipes;
5707}
5708
5709static int intel_modeset_checks(struct intel_atomic_state *state)
5710{
5711 struct intel_display *display = to_intel_display(state);
5712
5713 state->modeset = true;
5714
5715 if (display->platform.haswell)
5716 return hsw_mode_set_planes_workaround(state);
5717
5718 return 0;
5719}
5720
5721static bool lrr_params_changed(const struct drm_display_mode *old_adjusted_mode,
5722 const struct drm_display_mode *new_adjusted_mode)
5723{
5724 return old_adjusted_mode->crtc_vblank_start != new_adjusted_mode->crtc_vblank_start ||
5725 old_adjusted_mode->crtc_vblank_end != new_adjusted_mode->crtc_vblank_end ||
5726 old_adjusted_mode->crtc_vtotal != new_adjusted_mode->crtc_vtotal;
5727}
5728
5729static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
5730 struct intel_crtc_state *new_crtc_state)
5731{
5732 struct intel_display *display = to_intel_display(new_crtc_state);
5733 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5734
5735 /* only allow LRR when the timings stay within the VRR range */
5736 if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
5737 new_crtc_state->update_lrr = false;
5738
5739 if (!intel_pipe_config_compare(current_config: old_crtc_state, pipe_config: new_crtc_state, fastset: true)) {
5740 drm_dbg_kms(display->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n",
5741 crtc->base.base.id, crtc->base.name);
5742 } else {
5743 if (allow_vblank_delay_fastset(old_crtc_state))
5744 new_crtc_state->update_lrr = true;
5745 new_crtc_state->uapi.mode_changed = false;
5746 }
5747
5748 if (intel_compare_link_m_n(m_n: &old_crtc_state->dp_m_n,
5749 m2_n2: &new_crtc_state->dp_m_n))
5750 new_crtc_state->update_m_n = false;
5751
5752 if (!lrr_params_changed(old_adjusted_mode: &old_crtc_state->hw.adjusted_mode,
5753 new_adjusted_mode: &new_crtc_state->hw.adjusted_mode))
5754 new_crtc_state->update_lrr = false;
5755
5756 if (intel_crtc_needs_modeset(crtc_state: new_crtc_state))
5757 intel_crtc_flag_modeset(crtc_state: new_crtc_state);
5758 else
5759 new_crtc_state->update_pipe = true;
5760}
5761
5762static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
5763{
5764 struct intel_display *display = to_intel_display(state);
5765 struct intel_crtc_state __maybe_unused *crtc_state;
5766 struct intel_crtc *crtc;
5767 int i;
5768
5769 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5770 int ret;
5771
5772 ret = intel_crtc_atomic_check(state, crtc);
5773 if (ret) {
5774 drm_dbg_atomic(display->drm,
5775 "[CRTC:%d:%s] atomic driver check failed\n",
5776 crtc->base.base.id, crtc->base.name);
5777 return ret;
5778 }
5779 }
5780
5781 return 0;
5782}
5783
5784static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
5785 u8 transcoders)
5786{
5787 const struct intel_crtc_state *new_crtc_state;
5788 struct intel_crtc *crtc;
5789 int i;
5790
5791 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5792 if (new_crtc_state->hw.enable &&
5793 transcoders & BIT(new_crtc_state->cpu_transcoder) &&
5794 intel_crtc_needs_modeset(crtc_state: new_crtc_state))
5795 return true;
5796 }
5797
5798 return false;
5799}
5800
5801static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
5802 u8 pipes)
5803{
5804 const struct intel_crtc_state *new_crtc_state;
5805 struct intel_crtc *crtc;
5806 int i;
5807
5808 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5809 if (new_crtc_state->hw.enable &&
5810 pipes & BIT(crtc->pipe) &&
5811 intel_crtc_needs_modeset(crtc_state: new_crtc_state))
5812 return true;
5813 }
5814
5815 return false;
5816}
5817
5818static int intel_atomic_check_joiner(struct intel_atomic_state *state,
5819 struct intel_crtc *primary_crtc)
5820{
5821 struct intel_display *display = to_intel_display(state);
5822 struct intel_crtc_state *primary_crtc_state =
5823 intel_atomic_get_new_crtc_state(state, crtc: primary_crtc);
5824 struct intel_crtc *secondary_crtc;
5825
5826 if (!primary_crtc_state->joiner_pipes)
5827 return 0;
5828
5829 /* sanity check */
5830 if (drm_WARN_ON(display->drm,
5831 primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state)))
5832 return -EINVAL;
5833
5834 if (primary_crtc_state->joiner_pipes & ~joiner_pipes(display)) {
5835 drm_dbg_kms(display->drm,
5836 "[CRTC:%d:%s] Cannot act as joiner primary "
5837 "(need 0x%x as pipes, only 0x%x possible)\n",
5838 primary_crtc->base.base.id, primary_crtc->base.name,
5839 primary_crtc_state->joiner_pipes, joiner_pipes(display));
5840 return -EINVAL;
5841 }
5842
5843 for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,
5844 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) {
5845 struct intel_crtc_state *secondary_crtc_state;
5846 int ret;
5847
5848 secondary_crtc_state = intel_atomic_get_crtc_state(state: &state->base, crtc: secondary_crtc);
5849 if (IS_ERR(ptr: secondary_crtc_state))
5850 return PTR_ERR(ptr: secondary_crtc_state);
5851
5852 /* primary being enabled, secondary was already configured? */
5853 if (secondary_crtc_state->uapi.enable) {
5854 drm_dbg_kms(display->drm,
5855 "[CRTC:%d:%s] secondary is enabled as normal CRTC, but "
5856 "[CRTC:%d:%s] claiming this CRTC for joiner.\n",
5857 secondary_crtc->base.base.id, secondary_crtc->base.name,
5858 primary_crtc->base.base.id, primary_crtc->base.name);
5859 return -EINVAL;
5860 }
5861
5862 /*
5863 * The state copy logic assumes the primary crtc gets processed
5864 * before the secondary crtc during the main compute_config loop.
5865 * This works because the crtcs are created in pipe order,
5866 * and the hardware requires primary pipe < secondary pipe as well.
5867 * Should that change we need to rethink the logic.
5868 */
5869 if (WARN_ON(drm_crtc_index(&primary_crtc->base) >
5870 drm_crtc_index(&secondary_crtc->base)))
5871 return -EINVAL;
5872
5873 drm_dbg_kms(display->drm,
5874 "[CRTC:%d:%s] Used as secondary for joiner primary [CRTC:%d:%s]\n",
5875 secondary_crtc->base.base.id, secondary_crtc->base.name,
5876 primary_crtc->base.base.id, primary_crtc->base.name);
5877
5878 secondary_crtc_state->joiner_pipes =
5879 primary_crtc_state->joiner_pipes;
5880
5881 ret = copy_joiner_crtc_state_modeset(state, secondary_crtc);
5882 if (ret)
5883 return ret;
5884 }
5885
5886 return 0;
5887}
5888
5889static void kill_joiner_secondaries(struct intel_atomic_state *state,
5890 struct intel_crtc *primary_crtc)
5891{
5892 struct intel_display *display = to_intel_display(state);
5893 struct intel_crtc_state *primary_crtc_state =
5894 intel_atomic_get_new_crtc_state(state, crtc: primary_crtc);
5895 struct intel_crtc *secondary_crtc;
5896
5897 for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,
5898 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) {
5899 struct intel_crtc_state *secondary_crtc_state =
5900 intel_atomic_get_new_crtc_state(state, crtc: secondary_crtc);
5901
5902 secondary_crtc_state->joiner_pipes = 0;
5903
5904 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc: secondary_crtc);
5905 }
5906
5907 primary_crtc_state->joiner_pipes = 0;
5908}
5909
5910/**
5911 * DOC: asynchronous flip implementation
5912 *
5913 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
5914 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
5915 * Correspondingly, support is currently added for primary plane only.
5916 *
5917 * Async flip can only change the plane surface address, so anything else
5918 * changing is rejected from the intel_async_flip_check_hw() function.
5919 * Once this check is cleared, flip done interrupt is enabled using
5920 * the intel_crtc_enable_flip_done() function.
5921 *
5922 * As soon as the surface address register is written, flip done interrupt is
5923 * generated and the requested events are sent to the userspace in the interrupt
5924 * handler itself. The timestamp and sequence sent during the flip done event
5925 * correspond to the last vblank and have no relation to the actual time when
5926 * the flip done event was sent.
5927 */
5928static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
5929 struct intel_crtc *crtc)
5930{
5931 struct intel_display *display = to_intel_display(state);
5932 const struct intel_crtc_state *new_crtc_state =
5933 intel_atomic_get_new_crtc_state(state, crtc);
5934 const struct intel_plane_state *old_plane_state;
5935 struct intel_plane_state *new_plane_state;
5936 struct intel_plane *plane;
5937 int i;
5938
5939 if (!new_crtc_state->uapi.async_flip)
5940 return 0;
5941
5942 if (!new_crtc_state->uapi.active) {
5943 drm_dbg_kms(display->drm,
5944 "[CRTC:%d:%s] not active\n",
5945 crtc->base.base.id, crtc->base.name);
5946 return -EINVAL;
5947 }
5948
5949 if (intel_crtc_needs_modeset(crtc_state: new_crtc_state)) {
5950 drm_dbg_kms(display->drm,
5951 "[CRTC:%d:%s] modeset required\n",
5952 crtc->base.base.id, crtc->base.name);
5953 return -EINVAL;
5954 }
5955
5956 /*
5957 * FIXME: joiner+async flip is busted currently.
5958 * Remove this check once the issues are fixed.
5959 */
5960 if (new_crtc_state->joiner_pipes) {
5961 drm_dbg_kms(display->drm,
5962 "[CRTC:%d:%s] async flip disallowed with joiner\n",
5963 crtc->base.base.id, crtc->base.name);
5964 return -EINVAL;
5965 }
5966
5967 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
5968 new_plane_state, i) {
5969 if (plane->pipe != crtc->pipe)
5970 continue;
5971
5972 /*
5973 * TODO: Async flip is only supported through the page flip IOCTL
5974 * as of now. So support currently added for primary plane only.
5975 * Support for other planes on platforms on which supports
5976 * this(vlv/chv and icl+) should be added when async flip is
5977 * enabled in the atomic IOCTL path.
5978 */
5979 if (!plane->async_flip) {
5980 drm_dbg_kms(display->drm,
5981 "[PLANE:%d:%s] async flip not supported\n",
5982 plane->base.base.id, plane->base.name);
5983 return -EINVAL;
5984 }
5985
5986 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {
5987 drm_dbg_kms(display->drm,
5988 "[PLANE:%d:%s] no old or new framebuffer\n",
5989 plane->base.base.id, plane->base.name);
5990 return -EINVAL;
5991 }
5992 }
5993
5994 return 0;
5995}
5996
5997static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc)
5998{
5999 struct intel_display *display = to_intel_display(state);
6000 const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6001 const struct intel_plane_state *new_plane_state, *old_plane_state;
6002 struct intel_plane *plane;
6003 int i;
6004
6005 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6006 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6007
6008 if (!new_crtc_state->uapi.async_flip)
6009 return 0;
6010
6011 if (!new_crtc_state->hw.active) {
6012 drm_dbg_kms(display->drm,
6013 "[CRTC:%d:%s] not active\n",
6014 crtc->base.base.id, crtc->base.name);
6015 return -EINVAL;
6016 }
6017
6018 if (intel_crtc_needs_modeset(crtc_state: new_crtc_state)) {
6019 drm_dbg_kms(display->drm,
6020 "[CRTC:%d:%s] modeset required\n",
6021 crtc->base.base.id, crtc->base.name);
6022 return -EINVAL;
6023 }
6024
6025 if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
6026 drm_dbg_kms(display->drm,
6027 "[CRTC:%d:%s] Active planes cannot be in async flip\n",
6028 crtc->base.base.id, crtc->base.name);
6029 return -EINVAL;
6030 }
6031
6032 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6033 new_plane_state, i) {
6034 if (plane->pipe != crtc->pipe)
6035 continue;
6036
6037 /*
6038 * Only async flip capable planes should be in the state
6039 * if we're really about to ask the hardware to perform
6040 * an async flip. We should never get this far otherwise.
6041 */
6042 if (drm_WARN_ON(display->drm,
6043 new_crtc_state->do_async_flip && !plane->async_flip))
6044 return -EINVAL;
6045
6046 /*
6047 * Only check async flip capable planes other planes
6048 * may be involved in the initial commit due to
6049 * the wm0/ddb optimization.
6050 *
6051 * TODO maybe should track which planes actually
6052 * were requested to do the async flip...
6053 */
6054 if (!plane->async_flip)
6055 continue;
6056
6057 if (!intel_plane_can_async_flip(plane, format: new_plane_state->hw.fb->format->format,
6058 modifier: new_plane_state->hw.fb->modifier)) {
6059 drm_dbg_kms(display->drm,
6060 "[PLANE:%d:%s] pixel format %p4cc / modifier 0x%llx does not support async flip\n",
6061 plane->base.base.id, plane->base.name,
6062 &new_plane_state->hw.fb->format->format,
6063 new_plane_state->hw.fb->modifier);
6064 return -EINVAL;
6065 }
6066
6067 /*
6068 * We turn the first async flip request into a sync flip
6069 * so that we can reconfigure the plane (eg. change modifier).
6070 */
6071 if (!new_crtc_state->do_async_flip)
6072 continue;
6073
6074 if (old_plane_state->view.color_plane[0].mapping_stride !=
6075 new_plane_state->view.color_plane[0].mapping_stride) {
6076 drm_dbg_kms(display->drm,
6077 "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6078 plane->base.base.id, plane->base.name);
6079 return -EINVAL;
6080 }
6081
6082 if (old_plane_state->hw.fb->modifier !=
6083 new_plane_state->hw.fb->modifier) {
6084 drm_dbg_kms(display->drm,
6085 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6086 plane->base.base.id, plane->base.name);
6087 return -EINVAL;
6088 }
6089
6090 if (old_plane_state->hw.fb->format !=
6091 new_plane_state->hw.fb->format) {
6092 drm_dbg_kms(display->drm,
6093 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6094 plane->base.base.id, plane->base.name);
6095 return -EINVAL;
6096 }
6097
6098 if (old_plane_state->hw.rotation !=
6099 new_plane_state->hw.rotation) {
6100 drm_dbg_kms(display->drm,
6101 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6102 plane->base.base.id, plane->base.name);
6103 return -EINVAL;
6104 }
6105
6106 if (skl_plane_aux_dist(plane_state: old_plane_state, color_plane: 0) !=
6107 skl_plane_aux_dist(plane_state: new_plane_state, color_plane: 0)) {
6108 drm_dbg_kms(display->drm,
6109 "[PLANE:%d:%s] AUX_DIST cannot be changed in async flip\n",
6110 plane->base.base.id, plane->base.name);
6111 return -EINVAL;
6112 }
6113
6114 if (!drm_rect_equals(r1: &old_plane_state->uapi.src, r2: &new_plane_state->uapi.src) ||
6115 !drm_rect_equals(r1: &old_plane_state->uapi.dst, r2: &new_plane_state->uapi.dst)) {
6116 drm_dbg_kms(display->drm,
6117 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6118 plane->base.base.id, plane->base.name);
6119 return -EINVAL;
6120 }
6121
6122 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
6123 drm_dbg_kms(display->drm,
6124 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6125 plane->base.base.id, plane->base.name);
6126 return -EINVAL;
6127 }
6128
6129 if (old_plane_state->hw.pixel_blend_mode !=
6130 new_plane_state->hw.pixel_blend_mode) {
6131 drm_dbg_kms(display->drm,
6132 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6133 plane->base.base.id, plane->base.name);
6134 return -EINVAL;
6135 }
6136
6137 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
6138 drm_dbg_kms(display->drm,
6139 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6140 plane->base.base.id, plane->base.name);
6141 return -EINVAL;
6142 }
6143
6144 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
6145 drm_dbg_kms(display->drm,
6146 "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6147 plane->base.base.id, plane->base.name);
6148 return -EINVAL;
6149 }
6150
6151 /* plane decryption is allow to change only in synchronous flips */
6152 if (old_plane_state->decrypt != new_plane_state->decrypt) {
6153 drm_dbg_kms(display->drm,
6154 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6155 plane->base.base.id, plane->base.name);
6156 return -EINVAL;
6157 }
6158 }
6159
6160 return 0;
6161}
6162
6163static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state)
6164{
6165 struct intel_display *display = to_intel_display(state);
6166 const struct intel_plane_state *plane_state;
6167 struct intel_crtc_state *crtc_state;
6168 struct intel_plane *plane;
6169 struct intel_crtc *crtc;
6170 u8 affected_pipes = 0;
6171 u8 modeset_pipes = 0;
6172 int i;
6173
6174 /*
6175 * Any plane which is in use by the joiner needs its crtc.
6176 * Pull those in first as this will not have happened yet
6177 * if the plane remains disabled according to uapi.
6178 */
6179 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6180 crtc = to_intel_crtc(plane_state->hw.crtc);
6181 if (!crtc)
6182 continue;
6183
6184 crtc_state = intel_atomic_get_crtc_state(state: &state->base, crtc);
6185 if (IS_ERR(ptr: crtc_state))
6186 return PTR_ERR(ptr: crtc_state);
6187 }
6188
6189 /* Now pull in all joined crtcs */
6190 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6191 affected_pipes |= crtc_state->joiner_pipes;
6192 if (intel_crtc_needs_modeset(crtc_state))
6193 modeset_pipes |= crtc_state->joiner_pipes;
6194 }
6195
6196 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, affected_pipes) {
6197 crtc_state = intel_atomic_get_crtc_state(state: &state->base, crtc);
6198 if (IS_ERR(ptr: crtc_state))
6199 return PTR_ERR(ptr: crtc_state);
6200 }
6201
6202 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, modeset_pipes) {
6203 int ret;
6204
6205 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6206
6207 crtc_state->uapi.mode_changed = true;
6208
6209 ret = drm_atomic_add_affected_connectors(state: &state->base, crtc: &crtc->base);
6210 if (ret)
6211 return ret;
6212
6213 ret = intel_plane_add_affected(state, crtc);
6214 if (ret)
6215 return ret;
6216 }
6217
6218 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6219 /* Kill old joiner link, we may re-establish afterwards */
6220 if (intel_crtc_needs_modeset(crtc_state) &&
6221 intel_crtc_is_joiner_primary(crtc_state))
6222 kill_joiner_secondaries(state, primary_crtc: crtc);
6223 }
6224
6225 return 0;
6226}
6227
6228static int intel_atomic_check_config(struct intel_atomic_state *state,
6229 struct intel_link_bw_limits *limits,
6230 enum pipe *failed_pipe)
6231{
6232 struct intel_display *display = to_intel_display(state);
6233 struct intel_crtc_state *new_crtc_state;
6234 struct intel_crtc *crtc;
6235 int ret;
6236 int i;
6237
6238 *failed_pipe = INVALID_PIPE;
6239
6240 ret = intel_joiner_add_affected_crtcs(state);
6241 if (ret)
6242 return ret;
6243
6244 ret = intel_fdi_add_affected_crtcs(state);
6245 if (ret)
6246 return ret;
6247
6248 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6249 if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state)) {
6250 if (intel_crtc_is_joiner_secondary(crtc_state: new_crtc_state))
6251 copy_joiner_crtc_state_nomodeset(state, secondary_crtc: crtc);
6252 else
6253 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6254 continue;
6255 }
6256
6257 if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))
6258 continue;
6259
6260 ret = intel_crtc_prepare_cleared_state(state, crtc);
6261 if (ret)
6262 goto fail;
6263
6264 if (!new_crtc_state->hw.enable)
6265 continue;
6266
6267 ret = intel_modeset_pipe_config(state, crtc, limits);
6268 if (ret)
6269 goto fail;
6270 }
6271
6272 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6273 if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state))
6274 continue;
6275
6276 if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))
6277 continue;
6278
6279 if (!new_crtc_state->hw.enable)
6280 continue;
6281
6282 ret = intel_modeset_pipe_config_late(state, crtc);
6283 if (ret)
6284 goto fail;
6285 }
6286
6287fail:
6288 if (ret)
6289 *failed_pipe = crtc->pipe;
6290
6291 return ret;
6292}
6293
6294static int intel_atomic_check_config_and_link(struct intel_atomic_state *state)
6295{
6296 struct intel_link_bw_limits new_limits;
6297 struct intel_link_bw_limits old_limits;
6298 int ret;
6299
6300 intel_link_bw_init_limits(state, limits: &new_limits);
6301 old_limits = new_limits;
6302
6303 while (true) {
6304 enum pipe failed_pipe;
6305
6306 ret = intel_atomic_check_config(state, limits: &new_limits,
6307 failed_pipe: &failed_pipe);
6308 if (ret) {
6309 /*
6310 * The bpp limit for a pipe is below the minimum it supports, set the
6311 * limit to the minimum and recalculate the config.
6312 */
6313 if (ret == -EINVAL &&
6314 intel_link_bw_set_bpp_limit_for_pipe(state,
6315 old_limits: &old_limits,
6316 new_limits: &new_limits,
6317 pipe: failed_pipe))
6318 continue;
6319
6320 break;
6321 }
6322
6323 old_limits = new_limits;
6324
6325 ret = intel_link_bw_atomic_check(state, new_limits: &new_limits);
6326 if (ret != -EAGAIN)
6327 break;
6328 }
6329
6330 return ret;
6331}
6332/**
6333 * intel_atomic_check - validate state object
6334 * @dev: drm device
6335 * @_state: state to validate
6336 */
6337int intel_atomic_check(struct drm_device *dev,
6338 struct drm_atomic_state *_state)
6339{
6340 struct intel_display *display = to_intel_display(dev);
6341 struct intel_atomic_state *state = to_intel_atomic_state(_state);
6342 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6343 struct intel_crtc *crtc;
6344 int ret, i;
6345 bool any_ms = false;
6346
6347 if (!intel_display_driver_check_access(display))
6348 return -ENODEV;
6349
6350 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6351 new_crtc_state, i) {
6352 /*
6353 * crtc's state no longer considered to be inherited
6354 * after the first userspace/client initiated commit.
6355 */
6356 if (!state->internal)
6357 new_crtc_state->inherited = false;
6358
6359 if (new_crtc_state->inherited != old_crtc_state->inherited)
6360 new_crtc_state->uapi.mode_changed = true;
6361
6362 if (new_crtc_state->uapi.scaling_filter !=
6363 old_crtc_state->uapi.scaling_filter)
6364 new_crtc_state->uapi.mode_changed = true;
6365 }
6366
6367 intel_vrr_check_modeset(state);
6368
6369 ret = drm_atomic_helper_check_modeset(dev, state: &state->base);
6370 if (ret)
6371 goto fail;
6372
6373 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6374 ret = intel_async_flip_check_uapi(state, crtc);
6375 if (ret)
6376 return ret;
6377 }
6378
6379 ret = intel_atomic_check_config_and_link(state);
6380 if (ret)
6381 goto fail;
6382
6383 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6384 if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state))
6385 continue;
6386
6387 if (intel_crtc_is_joiner_secondary(crtc_state: new_crtc_state)) {
6388 drm_WARN_ON(display->drm, new_crtc_state->uapi.enable);
6389 continue;
6390 }
6391
6392 ret = intel_atomic_check_joiner(state, primary_crtc: crtc);
6393 if (ret)
6394 goto fail;
6395 }
6396
6397 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6398 new_crtc_state, i) {
6399 if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state))
6400 continue;
6401
6402 intel_joiner_adjust_pipe_src(crtc_state: new_crtc_state);
6403
6404 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
6405 }
6406
6407 /**
6408 * Check if fastset is allowed by external dependencies like other
6409 * pipes and transcoders.
6410 *
6411 * Right now it only forces a fullmodeset when the MST master
6412 * transcoder did not changed but the pipe of the master transcoder
6413 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
6414 * in case of port synced crtcs, if one of the synced crtcs
6415 * needs a full modeset, all other synced crtcs should be
6416 * forced a full modeset.
6417 */
6418 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6419 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(crtc_state: new_crtc_state))
6420 continue;
6421
6422 if (intel_dp_mst_crtc_needs_modeset(state, crtc))
6423 intel_crtc_flag_modeset(crtc_state: new_crtc_state);
6424
6425 if (intel_dp_mst_is_slave_trans(crtc_state: new_crtc_state)) {
6426 enum transcoder master = new_crtc_state->mst_master_transcoder;
6427
6428 if (intel_cpu_transcoders_need_modeset(state, BIT(master)))
6429 intel_crtc_flag_modeset(crtc_state: new_crtc_state);
6430 }
6431
6432 if (is_trans_port_sync_mode(crtc_state: new_crtc_state)) {
6433 u8 trans = new_crtc_state->sync_mode_slaves_mask;
6434
6435 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
6436 trans |= BIT(new_crtc_state->master_transcoder);
6437
6438 if (intel_cpu_transcoders_need_modeset(state, transcoders: trans))
6439 intel_crtc_flag_modeset(crtc_state: new_crtc_state);
6440 }
6441
6442 if (new_crtc_state->joiner_pipes) {
6443 if (intel_pipes_need_modeset(state, pipes: new_crtc_state->joiner_pipes))
6444 intel_crtc_flag_modeset(crtc_state: new_crtc_state);
6445 }
6446 }
6447
6448 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6449 new_crtc_state, i) {
6450 if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state))
6451 continue;
6452
6453 any_ms = true;
6454
6455 intel_dpll_release(state, crtc);
6456 }
6457
6458 if (any_ms && !check_digital_port_conflicts(state)) {
6459 drm_dbg_kms(display->drm,
6460 "rejecting conflicting digital port configuration\n");
6461 ret = -EINVAL;
6462 goto fail;
6463 }
6464
6465 ret = intel_plane_atomic_check(state);
6466 if (ret)
6467 goto fail;
6468
6469 ret = intel_compute_global_watermarks(state);
6470 if (ret)
6471 goto fail;
6472
6473 ret = intel_bw_atomic_check(state, any_ms);
6474 if (ret)
6475 goto fail;
6476
6477 ret = intel_cdclk_atomic_check(state, need_cdclk_calc: &any_ms);
6478 if (ret)
6479 goto fail;
6480
6481 if (intel_any_crtc_needs_modeset(state))
6482 any_ms = true;
6483
6484 if (any_ms) {
6485 ret = intel_modeset_checks(state);
6486 if (ret)
6487 goto fail;
6488
6489 ret = intel_modeset_calc_cdclk(state);
6490 if (ret)
6491 return ret;
6492 }
6493
6494 ret = intel_pmdemand_atomic_check(state);
6495 if (ret)
6496 goto fail;
6497
6498 ret = intel_atomic_check_crtcs(state);
6499 if (ret)
6500 goto fail;
6501
6502 ret = intel_fbc_atomic_check(state);
6503 if (ret)
6504 goto fail;
6505
6506 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6507 new_crtc_state, i) {
6508 intel_color_assert_luts(crtc_state: new_crtc_state);
6509
6510 ret = intel_async_flip_check_hw(state, crtc);
6511 if (ret)
6512 goto fail;
6513
6514 /* Either full modeset or fastset (or neither), never both */
6515 drm_WARN_ON(display->drm,
6516 intel_crtc_needs_modeset(new_crtc_state) &&
6517 intel_crtc_needs_fastset(new_crtc_state));
6518
6519 if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state) &&
6520 !intel_crtc_needs_fastset(crtc_state: new_crtc_state))
6521 continue;
6522
6523 intel_crtc_state_dump(crtc_state: new_crtc_state, state,
6524 context: intel_crtc_needs_modeset(crtc_state: new_crtc_state) ?
6525 "modeset" : "fastset");
6526 }
6527
6528 return 0;
6529
6530 fail:
6531 if (ret == -EDEADLK)
6532 return ret;
6533
6534 /*
6535 * FIXME would probably be nice to know which crtc specifically
6536 * caused the failure, in cases where we can pinpoint it.
6537 */
6538 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6539 new_crtc_state, i)
6540 intel_crtc_state_dump(crtc_state: new_crtc_state, state, context: "failed");
6541
6542 return ret;
6543}
6544
6545static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
6546{
6547 int ret;
6548
6549 ret = drm_atomic_helper_prepare_planes(dev: state->base.dev, state: &state->base);
6550 if (ret < 0)
6551 return ret;
6552
6553 return 0;
6554}
6555
6556void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
6557 struct intel_crtc_state *crtc_state)
6558{
6559 struct intel_display *display = to_intel_display(crtc);
6560
6561 if (DISPLAY_VER(display) != 2 || crtc_state->active_planes)
6562 intel_set_cpu_fifo_underrun_reporting(display, pipe: crtc->pipe, enable: true);
6563
6564 if (crtc_state->has_pch_encoder) {
6565 enum pipe pch_transcoder =
6566 intel_crtc_pch_transcoder(crtc);
6567
6568 intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, enable: true);
6569 }
6570}
6571
6572static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
6573 const struct intel_crtc_state *new_crtc_state)
6574{
6575 struct intel_display *display = to_intel_display(new_crtc_state);
6576 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6577
6578 /*
6579 * Update pipe size and adjust fitter if needed: the reason for this is
6580 * that in compute_mode_changes we check the native mode (not the pfit
6581 * mode) to see if we can flip rather than do a full mode set. In the
6582 * fastboot case, we'll flip, but if we don't update the pipesrc and
6583 * pfit state, we'll end up with a big fb scanned out into the wrong
6584 * sized surface.
6585 */
6586 intel_set_pipe_src_size(crtc_state: new_crtc_state);
6587
6588 /* on skylake this is done by detaching scalers */
6589 if (DISPLAY_VER(display) >= 9) {
6590 if (new_crtc_state->pch_pfit.enabled)
6591 skl_pfit_enable(crtc_state: new_crtc_state);
6592 } else if (HAS_PCH_SPLIT(display)) {
6593 if (new_crtc_state->pch_pfit.enabled)
6594 ilk_pfit_enable(crtc_state: new_crtc_state);
6595 else if (old_crtc_state->pch_pfit.enabled)
6596 ilk_pfit_disable(old_crtc_state);
6597 }
6598
6599 /*
6600 * The register is supposedly single buffered so perhaps
6601 * not 100% correct to do this here. But SKL+ calculate
6602 * this based on the adjust pixel rate so pfit changes do
6603 * affect it and so it must be updated for fastsets.
6604 * HSW/BDW only really need this here for fastboot, after
6605 * that the value should not change without a full modeset.
6606 */
6607 if (DISPLAY_VER(display) >= 9 ||
6608 display->platform.broadwell || display->platform.haswell)
6609 hsw_set_linetime_wm(crtc_state: new_crtc_state);
6610
6611 if (new_crtc_state->update_m_n)
6612 intel_cpu_transcoder_set_m1_n1(crtc, transcoder: new_crtc_state->cpu_transcoder,
6613 m_n: &new_crtc_state->dp_m_n);
6614
6615 if (new_crtc_state->update_lrr)
6616 intel_set_transcoder_timings_lrr(crtc_state: new_crtc_state);
6617}
6618
6619static void commit_pipe_pre_planes(struct intel_atomic_state *state,
6620 struct intel_crtc *crtc)
6621{
6622 struct intel_display *display = to_intel_display(state);
6623 const struct intel_crtc_state *old_crtc_state =
6624 intel_atomic_get_old_crtc_state(state, crtc);
6625 const struct intel_crtc_state *new_crtc_state =
6626 intel_atomic_get_new_crtc_state(state, crtc);
6627 bool modeset = intel_crtc_needs_modeset(crtc_state: new_crtc_state);
6628
6629 drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq);
6630
6631 /*
6632 * During modesets pipe configuration was programmed as the
6633 * CRTC was enabled.
6634 */
6635 if (!modeset) {
6636 if (intel_crtc_needs_color_update(crtc_state: new_crtc_state))
6637 intel_color_commit_arm(NULL, crtc_state: new_crtc_state);
6638
6639 if (DISPLAY_VER(display) >= 9 || display->platform.broadwell)
6640 bdw_set_pipe_misc(NULL, crtc_state: new_crtc_state);
6641
6642 if (intel_crtc_needs_fastset(crtc_state: new_crtc_state))
6643 intel_pipe_fastset(old_crtc_state, new_crtc_state);
6644 }
6645
6646 intel_psr2_program_trans_man_trk_ctl(NULL, crtc_state: new_crtc_state);
6647
6648 intel_atomic_update_watermarks(state, crtc);
6649}
6650
6651static void commit_pipe_post_planes(struct intel_atomic_state *state,
6652 struct intel_crtc *crtc)
6653{
6654 struct intel_display *display = to_intel_display(state);
6655 const struct intel_crtc_state *new_crtc_state =
6656 intel_atomic_get_new_crtc_state(state, crtc);
6657 bool modeset = intel_crtc_needs_modeset(crtc_state: new_crtc_state);
6658
6659 drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq);
6660
6661 /*
6662 * Disable the scaler(s) after the plane(s) so that we don't
6663 * get a catastrophic underrun even if the two operations
6664 * end up happening in two different frames.
6665 */
6666 if (DISPLAY_VER(display) >= 9 && !modeset)
6667 skl_detach_scalers(NULL, crtc_state: new_crtc_state);
6668
6669 if (!modeset &&
6670 intel_crtc_needs_color_update(crtc_state: new_crtc_state) &&
6671 !intel_color_uses_dsb(crtc_state: new_crtc_state) &&
6672 HAS_DOUBLE_BUFFERED_LUT(display))
6673 intel_color_load_luts(crtc_state: new_crtc_state);
6674
6675 if (intel_crtc_vrr_enabling(state, crtc))
6676 intel_vrr_enable(crtc_state: new_crtc_state);
6677}
6678
6679static void intel_enable_crtc(struct intel_atomic_state *state,
6680 struct intel_crtc *crtc)
6681{
6682 struct intel_display *display = to_intel_display(state);
6683 const struct intel_crtc_state *new_crtc_state =
6684 intel_atomic_get_new_crtc_state(state, crtc);
6685 struct intel_crtc *pipe_crtc;
6686
6687 if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state))
6688 return;
6689
6690 for_each_intel_crtc_in_pipe_mask_reverse(display->drm, pipe_crtc,
6691 intel_crtc_joined_pipe_mask(new_crtc_state)) {
6692 const struct intel_crtc_state *pipe_crtc_state =
6693 intel_atomic_get_new_crtc_state(state, crtc: pipe_crtc);
6694
6695 /* VRR will be enable later, if required */
6696 intel_crtc_update_active_timings(crtc_state: pipe_crtc_state, vrr_enable: false);
6697 }
6698
6699 intel_psr_notify_pipe_change(state, crtc, enable: true);
6700
6701 display->funcs.display->crtc_enable(state, crtc);
6702
6703 /* vblanks work again, re-enable pipe CRC. */
6704 intel_crtc_enable_pipe_crc(crtc);
6705}
6706
6707static void intel_pre_update_crtc(struct intel_atomic_state *state,
6708 struct intel_crtc *crtc)
6709{
6710 struct intel_display *display = to_intel_display(state);
6711 const struct intel_crtc_state *old_crtc_state =
6712 intel_atomic_get_old_crtc_state(state, crtc);
6713 struct intel_crtc_state *new_crtc_state =
6714 intel_atomic_get_new_crtc_state(state, crtc);
6715 bool modeset = intel_crtc_needs_modeset(crtc_state: new_crtc_state);
6716
6717 if (old_crtc_state->inherited ||
6718 intel_crtc_needs_modeset(crtc_state: new_crtc_state)) {
6719 if (HAS_DPT(display))
6720 intel_dpt_configure(crtc);
6721 }
6722
6723 if (!modeset) {
6724 if (new_crtc_state->preload_luts &&
6725 intel_crtc_needs_color_update(crtc_state: new_crtc_state))
6726 intel_color_load_luts(crtc_state: new_crtc_state);
6727
6728 intel_pre_plane_update(state, crtc);
6729
6730 if (intel_crtc_needs_fastset(crtc_state: new_crtc_state))
6731 intel_encoders_update_pipe(state, crtc);
6732
6733 if (DISPLAY_VER(display) >= 11 &&
6734 intel_crtc_needs_fastset(crtc_state: new_crtc_state))
6735 icl_set_pipe_chicken(crtc_state: new_crtc_state);
6736
6737 if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
6738 cmrr_params_changed(old_crtc_state, new_crtc_state))
6739 intel_vrr_set_transcoder_timings(crtc_state: new_crtc_state);
6740 }
6741
6742 intel_fbc_update(state, crtc);
6743
6744 drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF));
6745
6746 if (!modeset &&
6747 intel_crtc_needs_color_update(crtc_state: new_crtc_state) &&
6748 !new_crtc_state->use_dsb && !new_crtc_state->use_flipq)
6749 intel_color_commit_noarm(NULL, crtc_state: new_crtc_state);
6750
6751 if (!new_crtc_state->use_dsb && !new_crtc_state->use_flipq)
6752 intel_crtc_planes_update_noarm(NULL, state, crtc);
6753}
6754
6755static void intel_update_crtc(struct intel_atomic_state *state,
6756 struct intel_crtc *crtc)
6757{
6758 const struct intel_crtc_state *old_crtc_state =
6759 intel_atomic_get_old_crtc_state(state, crtc);
6760 struct intel_crtc_state *new_crtc_state =
6761 intel_atomic_get_new_crtc_state(state, crtc);
6762
6763 if (new_crtc_state->use_flipq) {
6764 intel_flipq_enable(crtc_state: new_crtc_state);
6765
6766 intel_crtc_prepare_vblank_event(crtc_state: new_crtc_state, event: &crtc->flipq_event);
6767
6768 intel_flipq_add(crtc, flip_queue_id: INTEL_FLIPQ_PLANE_1, pts: 0, dsb_id: INTEL_DSB_0,
6769 dsb: new_crtc_state->dsb_commit);
6770 } else if (new_crtc_state->use_dsb) {
6771 intel_crtc_prepare_vblank_event(crtc_state: new_crtc_state, event: &crtc->dsb_event);
6772
6773 intel_dsb_commit(dsb: new_crtc_state->dsb_commit);
6774 } else {
6775 /* Perform vblank evasion around commit operation */
6776 intel_pipe_update_start(state, crtc);
6777
6778 if (new_crtc_state->dsb_commit)
6779 intel_dsb_commit(dsb: new_crtc_state->dsb_commit);
6780
6781 commit_pipe_pre_planes(state, crtc);
6782
6783 intel_crtc_planes_update_arm(NULL, state, crtc);
6784
6785 commit_pipe_post_planes(state, crtc);
6786
6787 intel_pipe_update_end(state, crtc);
6788 }
6789
6790 /*
6791 * VRR/Seamless M/N update may need to update frame timings.
6792 *
6793 * FIXME Should be synchronized with the start of vblank somehow...
6794 */
6795 if (intel_crtc_vrr_enabling(state, crtc) ||
6796 new_crtc_state->update_m_n || new_crtc_state->update_lrr)
6797 intel_crtc_update_active_timings(crtc_state: new_crtc_state,
6798 vrr_enable: new_crtc_state->vrr.enable);
6799
6800 /*
6801 * We usually enable FIFO underrun interrupts as part of the
6802 * CRTC enable sequence during modesets. But when we inherit a
6803 * valid pipe configuration from the BIOS we need to take care
6804 * of enabling them on the CRTC's first fastset.
6805 */
6806 if (intel_crtc_needs_fastset(crtc_state: new_crtc_state) &&
6807 old_crtc_state->inherited)
6808 intel_crtc_arm_fifo_underrun(crtc, crtc_state: new_crtc_state);
6809}
6810
6811static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
6812 struct intel_crtc *crtc)
6813{
6814 struct intel_display *display = to_intel_display(state);
6815 const struct intel_crtc_state *old_crtc_state =
6816 intel_atomic_get_old_crtc_state(state, crtc);
6817 struct intel_crtc *pipe_crtc;
6818
6819 /*
6820 * We need to disable pipe CRC before disabling the pipe,
6821 * or we race against vblank off.
6822 */
6823 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
6824 intel_crtc_joined_pipe_mask(old_crtc_state))
6825 intel_crtc_disable_pipe_crc(crtc: pipe_crtc);
6826
6827 intel_psr_notify_pipe_change(state, crtc, enable: false);
6828
6829 display->funcs.display->crtc_disable(state, crtc);
6830
6831 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
6832 intel_crtc_joined_pipe_mask(old_crtc_state)) {
6833 const struct intel_crtc_state *new_pipe_crtc_state =
6834 intel_atomic_get_new_crtc_state(state, crtc: pipe_crtc);
6835
6836 pipe_crtc->active = false;
6837 intel_fbc_disable(crtc: pipe_crtc);
6838
6839 if (!new_pipe_crtc_state->hw.active)
6840 intel_initial_watermarks(state, crtc: pipe_crtc);
6841 }
6842}
6843
6844static void intel_commit_modeset_disables(struct intel_atomic_state *state)
6845{
6846 struct intel_display *display = to_intel_display(state);
6847 const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
6848 struct intel_crtc *crtc;
6849 u8 disable_pipes = 0;
6850 int i;
6851
6852 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6853 new_crtc_state, i) {
6854 if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state))
6855 continue;
6856
6857 /*
6858 * Needs to be done even for pipes
6859 * that weren't enabled previously.
6860 */
6861 intel_pre_plane_update(state, crtc);
6862
6863 if (!old_crtc_state->hw.active)
6864 continue;
6865
6866 disable_pipes |= BIT(crtc->pipe);
6867 }
6868
6869 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
6870 if ((disable_pipes & BIT(crtc->pipe)) == 0)
6871 continue;
6872
6873 intel_crtc_disable_planes(state, crtc);
6874
6875 drm_vblank_work_flush_all(crtc: &crtc->base);
6876 }
6877
6878 /* Only disable port sync and MST slaves */
6879 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
6880 if ((disable_pipes & BIT(crtc->pipe)) == 0)
6881 continue;
6882
6883 if (intel_crtc_is_joiner_secondary(crtc_state: old_crtc_state))
6884 continue;
6885
6886 /* In case of Transcoder port Sync master slave CRTCs can be
6887 * assigned in any order and we need to make sure that
6888 * slave CRTCs are disabled first and then master CRTC since
6889 * Slave vblanks are masked till Master Vblanks.
6890 */
6891 if (!is_trans_port_sync_slave(crtc_state: old_crtc_state) &&
6892 !intel_dp_mst_is_slave_trans(crtc_state: old_crtc_state))
6893 continue;
6894
6895 intel_old_crtc_state_disables(state, crtc);
6896
6897 disable_pipes &= ~intel_crtc_joined_pipe_mask(crtc_state: old_crtc_state);
6898 }
6899
6900 /* Disable everything else left on */
6901 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
6902 if ((disable_pipes & BIT(crtc->pipe)) == 0)
6903 continue;
6904
6905 if (intel_crtc_is_joiner_secondary(crtc_state: old_crtc_state))
6906 continue;
6907
6908 intel_old_crtc_state_disables(state, crtc);
6909
6910 disable_pipes &= ~intel_crtc_joined_pipe_mask(crtc_state: old_crtc_state);
6911 }
6912
6913 drm_WARN_ON(display->drm, disable_pipes);
6914}
6915
6916static void intel_commit_modeset_enables(struct intel_atomic_state *state)
6917{
6918 struct intel_crtc_state *new_crtc_state;
6919 struct intel_crtc *crtc;
6920 int i;
6921
6922 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6923 if (!new_crtc_state->hw.active)
6924 continue;
6925
6926 intel_enable_crtc(state, crtc);
6927 intel_pre_update_crtc(state, crtc);
6928 }
6929
6930 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6931 if (!new_crtc_state->hw.active)
6932 continue;
6933
6934 intel_update_crtc(state, crtc);
6935 }
6936}
6937
6938static void skl_commit_modeset_enables(struct intel_atomic_state *state)
6939{
6940 struct intel_display *display = to_intel_display(state);
6941 struct intel_crtc *crtc;
6942 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6943 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
6944 u8 update_pipes = 0, modeset_pipes = 0;
6945 int i;
6946
6947 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6948 enum pipe pipe = crtc->pipe;
6949
6950 if (!new_crtc_state->hw.active)
6951 continue;
6952
6953 /* ignore allocations for crtc's that have been turned off. */
6954 if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state)) {
6955 entries[pipe] = old_crtc_state->wm.skl.ddb;
6956 update_pipes |= BIT(pipe);
6957 } else {
6958 modeset_pipes |= BIT(pipe);
6959 }
6960 }
6961
6962 /*
6963 * Whenever the number of active pipes changes, we need to make sure we
6964 * update the pipes in the right order so that their ddb allocations
6965 * never overlap with each other between CRTC updates. Otherwise we'll
6966 * cause pipe underruns and other bad stuff.
6967 *
6968 * So first lets enable all pipes that do not need a fullmodeset as
6969 * those don't have any external dependency.
6970 */
6971 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6972 enum pipe pipe = crtc->pipe;
6973
6974 if ((update_pipes & BIT(pipe)) == 0)
6975 continue;
6976
6977 intel_pre_update_crtc(state, crtc);
6978 }
6979
6980 intel_dbuf_mbus_pre_ddb_update(state);
6981
6982 while (update_pipes) {
6983 /*
6984 * Commit in reverse order to make joiner primary
6985 * send the uapi events after secondaries are done.
6986 */
6987 for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
6988 new_crtc_state, i) {
6989 enum pipe pipe = crtc->pipe;
6990
6991 if ((update_pipes & BIT(pipe)) == 0)
6992 continue;
6993
6994 if (skl_ddb_allocation_overlaps(ddb: &new_crtc_state->wm.skl.ddb,
6995 entries, num_entries: I915_MAX_PIPES, ignore_idx: pipe))
6996 continue;
6997
6998 entries[pipe] = new_crtc_state->wm.skl.ddb;
6999 update_pipes &= ~BIT(pipe);
7000
7001 intel_update_crtc(state, crtc);
7002
7003 /*
7004 * If this is an already active pipe, it's DDB changed,
7005 * and this isn't the last pipe that needs updating
7006 * then we need to wait for a vblank to pass for the
7007 * new ddb allocation to take effect.
7008 */
7009 if (!skl_ddb_entry_equal(e1: &new_crtc_state->wm.skl.ddb,
7010 e2: &old_crtc_state->wm.skl.ddb) &&
7011 (update_pipes | modeset_pipes))
7012 intel_crtc_wait_for_next_vblank(crtc);
7013 }
7014 }
7015
7016 intel_dbuf_mbus_post_ddb_update(state);
7017
7018 update_pipes = modeset_pipes;
7019
7020 /*
7021 * Enable all pipes that needs a modeset and do not depends on other
7022 * pipes
7023 */
7024 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7025 enum pipe pipe = crtc->pipe;
7026
7027 if ((modeset_pipes & BIT(pipe)) == 0)
7028 continue;
7029
7030 if (intel_crtc_is_joiner_secondary(crtc_state: new_crtc_state))
7031 continue;
7032
7033 if (intel_dp_mst_is_slave_trans(crtc_state: new_crtc_state) ||
7034 is_trans_port_sync_master(crtc_state: new_crtc_state))
7035 continue;
7036
7037 modeset_pipes &= ~intel_crtc_joined_pipe_mask(crtc_state: new_crtc_state);
7038
7039 intel_enable_crtc(state, crtc);
7040 }
7041
7042 /*
7043 * Then we enable all remaining pipes that depend on other
7044 * pipes: MST slaves and port sync masters
7045 */
7046 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7047 enum pipe pipe = crtc->pipe;
7048
7049 if ((modeset_pipes & BIT(pipe)) == 0)
7050 continue;
7051
7052 if (intel_crtc_is_joiner_secondary(crtc_state: new_crtc_state))
7053 continue;
7054
7055 modeset_pipes &= ~intel_crtc_joined_pipe_mask(crtc_state: new_crtc_state);
7056
7057 intel_enable_crtc(state, crtc);
7058 }
7059
7060 /*
7061 * Finally we do the plane updates/etc. for all pipes that got enabled.
7062 */
7063 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7064 enum pipe pipe = crtc->pipe;
7065
7066 if ((update_pipes & BIT(pipe)) == 0)
7067 continue;
7068
7069 intel_pre_update_crtc(state, crtc);
7070 }
7071
7072 /*
7073 * Commit in reverse order to make joiner primary
7074 * send the uapi events after secondaries are done.
7075 */
7076 for_each_new_intel_crtc_in_state_reverse(state, crtc, new_crtc_state, i) {
7077 enum pipe pipe = crtc->pipe;
7078
7079 if ((update_pipes & BIT(pipe)) == 0)
7080 continue;
7081
7082 drm_WARN_ON(display->drm,
7083 skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7084 entries, I915_MAX_PIPES, pipe));
7085
7086 entries[pipe] = new_crtc_state->wm.skl.ddb;
7087 update_pipes &= ~BIT(pipe);
7088
7089 intel_update_crtc(state, crtc);
7090 }
7091
7092 drm_WARN_ON(display->drm, modeset_pipes);
7093 drm_WARN_ON(display->drm, update_pipes);
7094}
7095
7096static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
7097{
7098 struct drm_i915_private *i915 = to_i915(dev: intel_state->base.dev);
7099 struct drm_plane *plane;
7100 struct drm_plane_state *new_plane_state;
7101 long ret;
7102 int i;
7103
7104 for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) {
7105 if (new_plane_state->fence) {
7106 ret = dma_fence_wait_timeout(new_plane_state->fence, intr: false,
7107 timeout: i915_fence_timeout(i915));
7108 if (ret <= 0)
7109 break;
7110
7111 dma_fence_put(fence: new_plane_state->fence);
7112 new_plane_state->fence = NULL;
7113 }
7114 }
7115}
7116
7117static void intel_atomic_dsb_wait_commit(struct intel_crtc_state *crtc_state)
7118{
7119 if (crtc_state->dsb_commit)
7120 intel_dsb_wait(dsb: crtc_state->dsb_commit);
7121
7122 intel_color_wait_commit(crtc_state);
7123}
7124
7125static void intel_atomic_dsb_cleanup(struct intel_crtc_state *crtc_state)
7126{
7127 if (crtc_state->dsb_commit) {
7128 intel_dsb_cleanup(dsb: crtc_state->dsb_commit);
7129 crtc_state->dsb_commit = NULL;
7130 }
7131
7132 intel_color_cleanup_commit(crtc_state);
7133}
7134
7135static void intel_atomic_cleanup_work(struct work_struct *work)
7136{
7137 struct intel_atomic_state *state =
7138 container_of(work, struct intel_atomic_state, cleanup_work);
7139 struct intel_display *display = to_intel_display(state);
7140 struct intel_crtc_state *old_crtc_state;
7141 struct intel_crtc *crtc;
7142 int i;
7143
7144 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i)
7145 intel_atomic_dsb_cleanup(crtc_state: old_crtc_state);
7146
7147 drm_atomic_helper_cleanup_planes(dev: display->drm, old_state: &state->base);
7148 drm_atomic_helper_commit_cleanup_done(state: &state->base);
7149 drm_atomic_state_put(state: &state->base);
7150}
7151
7152static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
7153{
7154 struct intel_display *display = to_intel_display(state);
7155 struct intel_plane *plane;
7156 struct intel_plane_state *plane_state;
7157 int i;
7158
7159 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7160 struct drm_framebuffer *fb = plane_state->hw.fb;
7161 int cc_plane;
7162 int ret;
7163
7164 if (!fb)
7165 continue;
7166
7167 cc_plane = intel_fb_rc_ccs_cc_plane(fb);
7168 if (cc_plane < 0)
7169 continue;
7170
7171 /*
7172 * The layout of the fast clear color value expected by HW
7173 * (the DRM ABI requiring this value to be located in fb at
7174 * offset 0 of cc plane, plane #2 previous generations or
7175 * plane #1 for flat ccs):
7176 * - 4 x 4 bytes per-channel value
7177 * (in surface type specific float/int format provided by the fb user)
7178 * - 8 bytes native color value used by the display
7179 * (converted/written by GPU during a fast clear operation using the
7180 * above per-channel values)
7181 *
7182 * The commit's FB prepare hook already ensured that FB obj is pinned and the
7183 * caller made sure that the object is synced wrt. the related color clear value
7184 * GPU write on it.
7185 */
7186 ret = intel_bo_read_from_page(obj: intel_fb_bo(fb),
7187 offset: fb->offsets[cc_plane] + 16,
7188 dst: &plane_state->ccval,
7189 size: sizeof(plane_state->ccval));
7190 /* The above could only fail if the FB obj has an unexpected backing store type. */
7191 drm_WARN_ON(display->drm, ret);
7192 }
7193}
7194
7195static void intel_atomic_dsb_prepare(struct intel_atomic_state *state,
7196 struct intel_crtc *crtc)
7197{
7198 struct intel_display *display = to_intel_display(state);
7199 struct intel_crtc_state *new_crtc_state =
7200 intel_atomic_get_new_crtc_state(state, crtc);
7201
7202 if (!new_crtc_state->hw.active)
7203 return;
7204
7205 if (state->base.legacy_cursor_update)
7206 return;
7207
7208 /* FIXME deal with everything */
7209 new_crtc_state->use_flipq =
7210 intel_flipq_supported(display) &&
7211 !new_crtc_state->do_async_flip &&
7212 !new_crtc_state->vrr.enable &&
7213 !new_crtc_state->has_psr &&
7214 !intel_crtc_needs_modeset(crtc_state: new_crtc_state) &&
7215 !intel_crtc_needs_fastset(crtc_state: new_crtc_state) &&
7216 !intel_crtc_needs_color_update(crtc_state: new_crtc_state);
7217
7218 new_crtc_state->use_dsb =
7219 !new_crtc_state->use_flipq &&
7220 !new_crtc_state->do_async_flip &&
7221 (DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) &&
7222 !intel_crtc_needs_modeset(crtc_state: new_crtc_state) &&
7223 !intel_crtc_needs_fastset(crtc_state: new_crtc_state);
7224
7225 intel_color_prepare_commit(state, crtc);
7226}
7227
7228static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
7229 struct intel_crtc *crtc)
7230{
7231 struct intel_display *display = to_intel_display(state);
7232 struct intel_crtc_state *new_crtc_state =
7233 intel_atomic_get_new_crtc_state(state, crtc);
7234
7235 if (!new_crtc_state->use_flipq &&
7236 !new_crtc_state->use_dsb &&
7237 !new_crtc_state->dsb_color)
7238 return;
7239
7240 /*
7241 * Rough estimate:
7242 * ~64 registers per each plane * 8 planes = 512
7243 * Double that for pipe stuff and other overhead.
7244 */
7245 new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc, dsb_id: INTEL_DSB_0,
7246 max_cmds: new_crtc_state->use_dsb ||
7247 new_crtc_state->use_flipq ? 1024 : 16);
7248 if (!new_crtc_state->dsb_commit) {
7249 new_crtc_state->use_flipq = false;
7250 new_crtc_state->use_dsb = false;
7251 intel_color_cleanup_commit(crtc_state: new_crtc_state);
7252 return;
7253 }
7254
7255 if (new_crtc_state->use_flipq || new_crtc_state->use_dsb) {
7256 /* Wa_18034343758 */
7257 if (new_crtc_state->use_flipq)
7258 intel_flipq_wait_dmc_halt(dsb: new_crtc_state->dsb_commit, crtc);
7259
7260 if (intel_crtc_needs_color_update(crtc_state: new_crtc_state))
7261 intel_color_commit_noarm(dsb: new_crtc_state->dsb_commit,
7262 crtc_state: new_crtc_state);
7263 intel_crtc_planes_update_noarm(dsb: new_crtc_state->dsb_commit,
7264 state, crtc);
7265
7266 /*
7267 * Ensure we have "Frame Change" event when PSR state is
7268 * SRDENT(PSR1) or DEEP_SLEEP(PSR2). Otherwise DSB vblank
7269 * evasion hangs as PIPEDSL is reading as 0.
7270 */
7271 intel_psr_trigger_frame_change_event(dsb: new_crtc_state->dsb_commit,
7272 state, crtc);
7273
7274 intel_psr_wait_for_idle_dsb(dsb: new_crtc_state->dsb_commit,
7275 new_crtc_state);
7276
7277 if (new_crtc_state->use_dsb)
7278 intel_dsb_vblank_evade(state, dsb: new_crtc_state->dsb_commit);
7279
7280 if (intel_crtc_needs_color_update(crtc_state: new_crtc_state))
7281 intel_color_commit_arm(dsb: new_crtc_state->dsb_commit,
7282 crtc_state: new_crtc_state);
7283 bdw_set_pipe_misc(dsb: new_crtc_state->dsb_commit,
7284 crtc_state: new_crtc_state);
7285 intel_psr2_program_trans_man_trk_ctl(dsb: new_crtc_state->dsb_commit,
7286 crtc_state: new_crtc_state);
7287 intel_crtc_planes_update_arm(dsbx: new_crtc_state->dsb_commit,
7288 state, crtc);
7289
7290 if (DISPLAY_VER(display) >= 9)
7291 skl_detach_scalers(dsb: new_crtc_state->dsb_commit,
7292 crtc_state: new_crtc_state);
7293
7294 /* Wa_18034343758 */
7295 if (new_crtc_state->use_flipq)
7296 intel_flipq_unhalt_dmc(dsb: new_crtc_state->dsb_commit, crtc);
7297 }
7298
7299 if (intel_color_uses_chained_dsb(crtc_state: new_crtc_state))
7300 intel_dsb_chain(state, dsb: new_crtc_state->dsb_commit,
7301 chained_dsb: new_crtc_state->dsb_color, wait_for_vblank: true);
7302 else if (intel_color_uses_gosub_dsb(crtc_state: new_crtc_state))
7303 intel_dsb_gosub(dsb: new_crtc_state->dsb_commit,
7304 sub_dsb: new_crtc_state->dsb_color);
7305
7306 if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(crtc_state: new_crtc_state)) {
7307 intel_dsb_wait_vblanks(dsb: new_crtc_state->dsb_commit, count: 1);
7308
7309 intel_vrr_send_push(dsb: new_crtc_state->dsb_commit, crtc_state: new_crtc_state);
7310 intel_dsb_wait_vblank_delay(state, dsb: new_crtc_state->dsb_commit);
7311 intel_vrr_check_push_sent(dsb: new_crtc_state->dsb_commit,
7312 crtc_state: new_crtc_state);
7313 intel_dsb_interrupt(dsb: new_crtc_state->dsb_commit);
7314 }
7315
7316 intel_dsb_finish(dsb: new_crtc_state->dsb_commit);
7317}
7318
7319static void intel_atomic_commit_tail(struct intel_atomic_state *state)
7320{
7321 struct intel_display *display = to_intel_display(state);
7322 struct drm_i915_private __maybe_unused *dev_priv = to_i915(dev: display->drm);
7323 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7324 struct intel_crtc *crtc;
7325 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
7326 intel_wakeref_t wakeref = NULL;
7327 int i;
7328
7329 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7330 intel_atomic_dsb_prepare(state, crtc);
7331
7332 intel_atomic_commit_fence_wait(intel_state: state);
7333
7334 intel_td_flush(display);
7335
7336 intel_atomic_prepare_plane_clear_colors(state);
7337
7338 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7339 intel_fbc_prepare_dirty_rect(state, crtc);
7340
7341 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7342 intel_atomic_dsb_finish(state, crtc);
7343
7344 drm_atomic_helper_wait_for_dependencies(state: &state->base);
7345 drm_dp_mst_atomic_wait_for_dependencies(state: &state->base);
7346 intel_atomic_global_state_wait_for_dependencies(state);
7347
7348 /*
7349 * During full modesets we write a lot of registers, wait
7350 * for PLLs, etc. Doing that while DC states are enabled
7351 * is not a good idea.
7352 *
7353 * During fastsets and other updates we also need to
7354 * disable DC states due to the following scenario:
7355 * 1. DC5 exit and PSR exit happen
7356 * 2. Some or all _noarm() registers are written
7357 * 3. Due to some long delay PSR is re-entered
7358 * 4. DC5 entry -> DMC saves the already written new
7359 * _noarm() registers and the old not yet written
7360 * _arm() registers
7361 * 5. DC5 exit -> DMC restores a mixture of old and
7362 * new register values and arms the update
7363 * 6. PSR exit -> hardware latches a mixture of old and
7364 * new register values -> corrupted frame, or worse
7365 * 7. New _arm() registers are finally written
7366 * 8. Hardware finally latches a complete set of new
7367 * register values, and subsequent frames will be OK again
7368 *
7369 * Also note that due to the pipe CSC hardware issues on
7370 * SKL/GLK DC states must remain off until the pipe CSC
7371 * state readout has happened. Otherwise we risk corrupting
7372 * the CSC latched register values with the readout (see
7373 * skl_read_csc() and skl_color_commit_noarm()).
7374 */
7375 wakeref = intel_display_power_get(display, domain: POWER_DOMAIN_DC_OFF);
7376
7377 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7378 new_crtc_state, i) {
7379 if (intel_crtc_needs_modeset(crtc_state: new_crtc_state) ||
7380 intel_crtc_needs_fastset(crtc_state: new_crtc_state))
7381 intel_modeset_get_crtc_power_domains(crtc_state: new_crtc_state, old_domains: &put_domains[crtc->pipe]);
7382 }
7383
7384 intel_commit_modeset_disables(state);
7385
7386 intel_dp_tunnel_atomic_alloc_bw(state);
7387
7388 /* FIXME: Eventually get rid of our crtc->config pointer */
7389 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7390 crtc->config = new_crtc_state;
7391
7392 /*
7393 * In XE_LPD+ Pmdemand combines many parameters such as voltage index,
7394 * plls, cdclk frequency, QGV point selection parameter etc. Voltage
7395 * index, cdclk/ddiclk frequencies are supposed to be configured before
7396 * the cdclk config is set.
7397 */
7398 intel_pmdemand_pre_plane_update(state);
7399
7400 if (state->modeset) {
7401 drm_atomic_helper_update_legacy_modeset_state(dev: display->drm, old_state: &state->base);
7402
7403 intel_set_cdclk_pre_plane_update(state);
7404
7405 intel_modeset_verify_disabled(state);
7406 }
7407
7408 intel_sagv_pre_plane_update(state);
7409
7410 /* Complete the events for pipes that have now been disabled */
7411 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7412 bool modeset = intel_crtc_needs_modeset(crtc_state: new_crtc_state);
7413
7414 /* Complete events for now disable pipes here. */
7415 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
7416 spin_lock_irq(lock: &display->drm->event_lock);
7417 drm_crtc_send_vblank_event(crtc: &crtc->base,
7418 e: new_crtc_state->uapi.event);
7419 spin_unlock_irq(lock: &display->drm->event_lock);
7420
7421 new_crtc_state->uapi.event = NULL;
7422 }
7423 }
7424
7425 intel_encoders_update_prepare(state);
7426
7427 intel_dbuf_pre_plane_update(state);
7428
7429 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7430 if (new_crtc_state->do_async_flip)
7431 intel_crtc_enable_flip_done(state, crtc);
7432 }
7433
7434 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7435 display->funcs.display->commit_modeset_enables(state);
7436
7437 /* FIXME probably need to sequence this properly */
7438 intel_program_dpkgc_latency(state);
7439
7440 intel_wait_for_vblank_workers(state);
7441
7442 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7443 * already, but still need the state for the delayed optimization. To
7444 * fix this:
7445 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
7446 * - schedule that vblank worker _before_ calling hw_done
7447 * - at the start of commit_tail, cancel it _synchrously
7448 * - switch over to the vblank wait helper in the core after that since
7449 * we don't need out special handling any more.
7450 */
7451 drm_atomic_helper_wait_for_flip_done(dev: display->drm, old_state: &state->base);
7452
7453 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7454 if (new_crtc_state->do_async_flip)
7455 intel_crtc_disable_flip_done(state, crtc);
7456
7457 intel_atomic_dsb_wait_commit(crtc_state: new_crtc_state);
7458
7459 if (!state->base.legacy_cursor_update && !new_crtc_state->use_dsb)
7460 intel_vrr_check_push_sent(NULL, crtc_state: new_crtc_state);
7461
7462 if (new_crtc_state->use_flipq)
7463 intel_flipq_disable(old_crtc_state: new_crtc_state);
7464 }
7465
7466 /*
7467 * Now that the vblank has passed, we can go ahead and program the
7468 * optimal watermarks on platforms that need two-step watermark
7469 * programming.
7470 *
7471 * TODO: Move this (and other cleanup) to an async worker eventually.
7472 */
7473 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7474 new_crtc_state, i) {
7475 /*
7476 * Gen2 reports pipe underruns whenever all planes are disabled.
7477 * So re-enable underrun reporting after some planes get enabled.
7478 *
7479 * We do this before .optimize_watermarks() so that we have a
7480 * chance of catching underruns with the intermediate watermarks
7481 * vs. the new plane configuration.
7482 */
7483 if (DISPLAY_VER(display) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7484 intel_set_cpu_fifo_underrun_reporting(display, pipe: crtc->pipe, enable: true);
7485
7486 intel_optimize_watermarks(state, crtc);
7487 }
7488
7489 intel_dbuf_post_plane_update(state);
7490
7491 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7492 intel_post_plane_update(state, crtc);
7493
7494 intel_modeset_put_crtc_power_domains(crtc, domains: &put_domains[crtc->pipe]);
7495
7496 intel_modeset_verify_crtc(state, crtc);
7497
7498 intel_post_plane_update_after_readout(state, crtc);
7499
7500 /*
7501 * DSB cleanup is done in cleanup_work aligning with framebuffer
7502 * cleanup. So copy and reset the dsb structure to sync with
7503 * commit_done and later do dsb cleanup in cleanup_work.
7504 *
7505 * FIXME get rid of this funny new->old swapping
7506 */
7507 old_crtc_state->dsb_color = fetch_and_zero(&new_crtc_state->dsb_color);
7508 old_crtc_state->dsb_commit = fetch_and_zero(&new_crtc_state->dsb_commit);
7509 }
7510
7511 /* Underruns don't always raise interrupts, so check manually */
7512 intel_check_cpu_fifo_underruns(display);
7513 intel_check_pch_fifo_underruns(display);
7514
7515 if (state->modeset)
7516 intel_verify_planes(state);
7517
7518 intel_sagv_post_plane_update(state);
7519 if (state->modeset)
7520 intel_set_cdclk_post_plane_update(state);
7521 intel_pmdemand_post_plane_update(state);
7522
7523 drm_atomic_helper_commit_hw_done(state: &state->base);
7524 intel_atomic_global_state_commit_done(state);
7525
7526 if (state->modeset) {
7527 /* As one of the primary mmio accessors, KMS has a high
7528 * likelihood of triggering bugs in unclaimed access. After we
7529 * finish modesetting, see if an error has been flagged, and if
7530 * so enable debugging for the next modeset - and hope we catch
7531 * the culprit.
7532 */
7533 intel_uncore_arm_unclaimed_mmio_detection(uncore: &dev_priv->uncore);
7534 }
7535 /*
7536 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
7537 * toggling overhead at and above 60 FPS.
7538 */
7539 intel_display_power_put_async_delay(display, domain: POWER_DOMAIN_DC_OFF, wakeref, delay_ms: 17);
7540 intel_display_rpm_put(display, wakeref: state->wakeref);
7541
7542 /*
7543 * Defer the cleanup of the old state to a separate worker to not
7544 * impede the current task (userspace for blocking modesets) that
7545 * are executed inline. For out-of-line asynchronous modesets/flips,
7546 * deferring to a new worker seems overkill, but we would place a
7547 * schedule point (cond_resched()) here anyway to keep latencies
7548 * down.
7549 */
7550 INIT_WORK(&state->cleanup_work, intel_atomic_cleanup_work);
7551 queue_work(wq: display->wq.cleanup, work: &state->cleanup_work);
7552}
7553
7554static void intel_atomic_commit_work(struct work_struct *work)
7555{
7556 struct intel_atomic_state *state =
7557 container_of(work, struct intel_atomic_state, base.commit_work);
7558
7559 intel_atomic_commit_tail(state);
7560}
7561
7562static void intel_atomic_track_fbs(struct intel_atomic_state *state)
7563{
7564 struct intel_plane_state *old_plane_state, *new_plane_state;
7565 struct intel_plane *plane;
7566 int i;
7567
7568 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
7569 new_plane_state, i)
7570 intel_frontbuffer_track(old: to_intel_frontbuffer(fb: old_plane_state->hw.fb),
7571 new: to_intel_frontbuffer(fb: new_plane_state->hw.fb),
7572 frontbuffer_bits: plane->frontbuffer_bit);
7573}
7574
7575static int intel_atomic_setup_commit(struct intel_atomic_state *state, bool nonblock)
7576{
7577 int ret;
7578
7579 ret = drm_atomic_helper_setup_commit(state: &state->base, nonblock);
7580 if (ret)
7581 return ret;
7582
7583 ret = intel_atomic_global_state_setup_commit(state);
7584 if (ret)
7585 return ret;
7586
7587 return 0;
7588}
7589
7590static int intel_atomic_swap_state(struct intel_atomic_state *state)
7591{
7592 int ret;
7593
7594 ret = drm_atomic_helper_swap_state(state: &state->base, stall: true);
7595 if (ret)
7596 return ret;
7597
7598 intel_atomic_swap_global_state(state);
7599
7600 intel_dpll_swap_state(state);
7601
7602 intel_atomic_track_fbs(state);
7603
7604 return 0;
7605}
7606
7607int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
7608 bool nonblock)
7609{
7610 struct intel_display *display = to_intel_display(dev);
7611 struct intel_atomic_state *state = to_intel_atomic_state(_state);
7612 int ret = 0;
7613
7614 state->wakeref = intel_display_rpm_get(display);
7615
7616 /*
7617 * The intel_legacy_cursor_update() fast path takes care
7618 * of avoiding the vblank waits for simple cursor
7619 * movement and flips. For cursor on/off and size changes,
7620 * we want to perform the vblank waits so that watermark
7621 * updates happen during the correct frames. Gen9+ have
7622 * double buffered watermarks and so shouldn't need this.
7623 *
7624 * Unset state->legacy_cursor_update before the call to
7625 * drm_atomic_helper_setup_commit() because otherwise
7626 * drm_atomic_helper_wait_for_flip_done() is a noop and
7627 * we get FIFO underruns because we didn't wait
7628 * for vblank.
7629 *
7630 * FIXME doing watermarks and fb cleanup from a vblank worker
7631 * (assuming we had any) would solve these problems.
7632 */
7633 if (DISPLAY_VER(display) < 9 && state->base.legacy_cursor_update) {
7634 struct intel_crtc_state *new_crtc_state;
7635 struct intel_crtc *crtc;
7636 int i;
7637
7638 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7639 if (new_crtc_state->wm.need_postvbl_update ||
7640 new_crtc_state->update_wm_post)
7641 state->base.legacy_cursor_update = false;
7642 }
7643
7644 ret = intel_atomic_prepare_commit(state);
7645 if (ret) {
7646 drm_dbg_atomic(display->drm,
7647 "Preparing state failed with %i\n", ret);
7648 intel_display_rpm_put(display, wakeref: state->wakeref);
7649 return ret;
7650 }
7651
7652 ret = intel_atomic_setup_commit(state, nonblock);
7653 if (!ret)
7654 ret = intel_atomic_swap_state(state);
7655
7656 if (ret) {
7657 drm_atomic_helper_unprepare_planes(dev, state: &state->base);
7658 intel_display_rpm_put(display, wakeref: state->wakeref);
7659 return ret;
7660 }
7661
7662 drm_atomic_state_get(state: &state->base);
7663 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
7664
7665 if (nonblock && state->modeset) {
7666 queue_work(wq: display->wq.modeset, work: &state->base.commit_work);
7667 } else if (nonblock) {
7668 queue_work(wq: display->wq.flip, work: &state->base.commit_work);
7669 } else {
7670 if (state->modeset)
7671 flush_workqueue(display->wq.modeset);
7672 intel_atomic_commit_tail(state);
7673 }
7674
7675 return 0;
7676}
7677
7678static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
7679{
7680 struct intel_display *display = to_intel_display(encoder);
7681 struct intel_encoder *source_encoder;
7682 u32 possible_clones = 0;
7683
7684 for_each_intel_encoder(display->drm, source_encoder) {
7685 if (encoders_cloneable(a: encoder, b: source_encoder))
7686 possible_clones |= drm_encoder_mask(encoder: &source_encoder->base);
7687 }
7688
7689 return possible_clones;
7690}
7691
7692static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
7693{
7694 struct intel_display *display = to_intel_display(encoder);
7695 struct intel_crtc *crtc;
7696 u32 possible_crtcs = 0;
7697
7698 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, encoder->pipe_mask)
7699 possible_crtcs |= drm_crtc_mask(crtc: &crtc->base);
7700
7701 return possible_crtcs;
7702}
7703
7704static bool ilk_has_edp_a(struct intel_display *display)
7705{
7706 if (!display->platform.mobile)
7707 return false;
7708
7709 if ((intel_de_read(display, DP_A) & DP_DETECTED) == 0)
7710 return false;
7711
7712 if (display->platform.ironlake && (intel_de_read(display, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7713 return false;
7714
7715 return true;
7716}
7717
7718static bool intel_ddi_crt_present(struct intel_display *display)
7719{
7720 if (DISPLAY_VER(display) >= 9)
7721 return false;
7722
7723 if (display->platform.haswell_ult || display->platform.broadwell_ult)
7724 return false;
7725
7726 if (HAS_PCH_LPT_H(display) &&
7727 intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7728 return false;
7729
7730 /* DDI E can't be used if DDI A requires 4 lanes */
7731 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7732 return false;
7733
7734 if (!display->vbt.int_crt_support)
7735 return false;
7736
7737 return true;
7738}
7739
7740bool assert_port_valid(struct intel_display *display, enum port port)
7741{
7742 return !drm_WARN(display->drm, !(DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)),
7743 "Platform does not support port %c\n", port_name(port));
7744}
7745
7746void intel_setup_outputs(struct intel_display *display)
7747{
7748 struct intel_encoder *encoder;
7749 bool dpd_is_edp = false;
7750
7751 intel_pps_unlock_regs_wa(display);
7752
7753 if (!HAS_DISPLAY(display))
7754 return;
7755
7756 if (HAS_DDI(display)) {
7757 if (intel_ddi_crt_present(display))
7758 intel_crt_init(display);
7759
7760 intel_bios_for_each_encoder(display, func: intel_ddi_init);
7761
7762 if (display->platform.geminilake || display->platform.broxton)
7763 vlv_dsi_init(display);
7764 } else if (HAS_PCH_SPLIT(display)) {
7765 int found;
7766
7767 /*
7768 * intel_edp_init_connector() depends on this completing first,
7769 * to prevent the registration of both eDP and LVDS and the
7770 * incorrect sharing of the PPS.
7771 */
7772 intel_lvds_init(display);
7773 intel_crt_init(display);
7774
7775 dpd_is_edp = intel_dp_is_port_edp(display, port: PORT_D);
7776
7777 if (ilk_has_edp_a(display))
7778 g4x_dp_init(display, DP_A, port: PORT_A);
7779
7780 if (intel_de_read(display, PCH_HDMIB) & SDVO_DETECTED) {
7781 /* PCH SDVOB multiplex with HDMIB */
7782 found = intel_sdvo_init(display, PCH_SDVOB, port: PORT_B);
7783 if (!found)
7784 g4x_hdmi_init(display, PCH_HDMIB, port: PORT_B);
7785 if (!found && (intel_de_read(display, PCH_DP_B) & DP_DETECTED))
7786 g4x_dp_init(display, PCH_DP_B, port: PORT_B);
7787 }
7788
7789 if (intel_de_read(display, PCH_HDMIC) & SDVO_DETECTED)
7790 g4x_hdmi_init(display, PCH_HDMIC, port: PORT_C);
7791
7792 if (!dpd_is_edp && intel_de_read(display, PCH_HDMID) & SDVO_DETECTED)
7793 g4x_hdmi_init(display, PCH_HDMID, port: PORT_D);
7794
7795 if (intel_de_read(display, PCH_DP_C) & DP_DETECTED)
7796 g4x_dp_init(display, PCH_DP_C, port: PORT_C);
7797
7798 if (intel_de_read(display, PCH_DP_D) & DP_DETECTED)
7799 g4x_dp_init(display, PCH_DP_D, port: PORT_D);
7800 } else if (display->platform.valleyview || display->platform.cherryview) {
7801 bool has_edp, has_port;
7802
7803 if (display->platform.valleyview && display->vbt.int_crt_support)
7804 intel_crt_init(display);
7805
7806 /*
7807 * The DP_DETECTED bit is the latched state of the DDC
7808 * SDA pin at boot. However since eDP doesn't require DDC
7809 * (no way to plug in a DP->HDMI dongle) the DDC pins for
7810 * eDP ports may have been muxed to an alternate function.
7811 * Thus we can't rely on the DP_DETECTED bit alone to detect
7812 * eDP ports. Consult the VBT as well as DP_DETECTED to
7813 * detect eDP ports.
7814 *
7815 * Sadly the straps seem to be missing sometimes even for HDMI
7816 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
7817 * and VBT for the presence of the port. Additionally we can't
7818 * trust the port type the VBT declares as we've seen at least
7819 * HDMI ports that the VBT claim are DP or eDP.
7820 */
7821 has_edp = intel_dp_is_port_edp(display, port: PORT_B);
7822 has_port = intel_bios_is_port_present(display, port: PORT_B);
7823 if (intel_de_read(display, VLV_DP_B) & DP_DETECTED || has_port)
7824 has_edp &= g4x_dp_init(display, VLV_DP_B, port: PORT_B);
7825 if ((intel_de_read(display, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
7826 g4x_hdmi_init(display, VLV_HDMIB, port: PORT_B);
7827
7828 has_edp = intel_dp_is_port_edp(display, port: PORT_C);
7829 has_port = intel_bios_is_port_present(display, port: PORT_C);
7830 if (intel_de_read(display, VLV_DP_C) & DP_DETECTED || has_port)
7831 has_edp &= g4x_dp_init(display, VLV_DP_C, port: PORT_C);
7832 if ((intel_de_read(display, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
7833 g4x_hdmi_init(display, VLV_HDMIC, port: PORT_C);
7834
7835 if (display->platform.cherryview) {
7836 /*
7837 * eDP not supported on port D,
7838 * so no need to worry about it
7839 */
7840 has_port = intel_bios_is_port_present(display, port: PORT_D);
7841 if (intel_de_read(display, CHV_DP_D) & DP_DETECTED || has_port)
7842 g4x_dp_init(display, CHV_DP_D, port: PORT_D);
7843 if (intel_de_read(display, CHV_HDMID) & SDVO_DETECTED || has_port)
7844 g4x_hdmi_init(display, CHV_HDMID, port: PORT_D);
7845 }
7846
7847 vlv_dsi_init(display);
7848 } else if (display->platform.pineview) {
7849 intel_lvds_init(display);
7850 intel_crt_init(display);
7851 } else if (IS_DISPLAY_VER(display, 3, 4)) {
7852 bool found = false;
7853
7854 if (display->platform.mobile)
7855 intel_lvds_init(display);
7856
7857 intel_crt_init(display);
7858
7859 if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {
7860 drm_dbg_kms(display->drm, "probing SDVOB\n");
7861 found = intel_sdvo_init(display, GEN3_SDVOB, port: PORT_B);
7862 if (!found && display->platform.g4x) {
7863 drm_dbg_kms(display->drm,
7864 "probing HDMI on SDVOB\n");
7865 g4x_hdmi_init(display, GEN4_HDMIB, port: PORT_B);
7866 }
7867
7868 if (!found && display->platform.g4x)
7869 g4x_dp_init(display, DP_B, port: PORT_B);
7870 }
7871
7872 /* Before G4X SDVOC doesn't have its own detect register */
7873
7874 if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {
7875 drm_dbg_kms(display->drm, "probing SDVOC\n");
7876 found = intel_sdvo_init(display, GEN3_SDVOC, port: PORT_C);
7877 }
7878
7879 if (!found && (intel_de_read(display, GEN3_SDVOC) & SDVO_DETECTED)) {
7880
7881 if (display->platform.g4x) {
7882 drm_dbg_kms(display->drm,
7883 "probing HDMI on SDVOC\n");
7884 g4x_hdmi_init(display, GEN4_HDMIC, port: PORT_C);
7885 }
7886 if (display->platform.g4x)
7887 g4x_dp_init(display, DP_C, port: PORT_C);
7888 }
7889
7890 if (display->platform.g4x && (intel_de_read(display, DP_D) & DP_DETECTED))
7891 g4x_dp_init(display, DP_D, port: PORT_D);
7892
7893 if (SUPPORTS_TV(display))
7894 intel_tv_init(display);
7895 } else if (DISPLAY_VER(display) == 2) {
7896 if (display->platform.i85x)
7897 intel_lvds_init(display);
7898
7899 intel_crt_init(display);
7900 intel_dvo_init(display);
7901 }
7902
7903 for_each_intel_encoder(display->drm, encoder) {
7904 encoder->base.possible_crtcs =
7905 intel_encoder_possible_crtcs(encoder);
7906 encoder->base.possible_clones =
7907 intel_encoder_possible_clones(encoder);
7908 }
7909
7910 intel_init_pch_refclk(display);
7911
7912 drm_helper_move_panel_connectors_to_head(display->drm);
7913}
7914
7915static int max_dotclock(struct intel_display *display)
7916{
7917 int max_dotclock = display->cdclk.max_dotclk_freq;
7918
7919 if (HAS_ULTRAJOINER(display))
7920 max_dotclock *= 4;
7921 else if (HAS_UNCOMPRESSED_JOINER(display) || HAS_BIGJOINER(display))
7922 max_dotclock *= 2;
7923
7924 return max_dotclock;
7925}
7926
7927enum drm_mode_status intel_mode_valid(struct drm_device *dev,
7928 const struct drm_display_mode *mode)
7929{
7930 struct intel_display *display = to_intel_display(dev);
7931 int hdisplay_max, htotal_max;
7932 int vdisplay_max, vtotal_max;
7933
7934 /*
7935 * Can't reject DBLSCAN here because Xorg ddxen can add piles
7936 * of DBLSCAN modes to the output's mode list when they detect
7937 * the scaling mode property on the connector. And they don't
7938 * ask the kernel to validate those modes in any way until
7939 * modeset time at which point the client gets a protocol error.
7940 * So in order to not upset those clients we silently ignore the
7941 * DBLSCAN flag on such connectors. For other connectors we will
7942 * reject modes with the DBLSCAN flag in encoder->compute_config().
7943 * And we always reject DBLSCAN modes in connector->mode_valid()
7944 * as we never want such modes on the connector's mode list.
7945 */
7946
7947 if (mode->vscan > 1)
7948 return MODE_NO_VSCAN;
7949
7950 if (mode->flags & DRM_MODE_FLAG_HSKEW)
7951 return MODE_H_ILLEGAL;
7952
7953 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
7954 DRM_MODE_FLAG_NCSYNC |
7955 DRM_MODE_FLAG_PCSYNC))
7956 return MODE_HSYNC;
7957
7958 if (mode->flags & (DRM_MODE_FLAG_BCAST |
7959 DRM_MODE_FLAG_PIXMUX |
7960 DRM_MODE_FLAG_CLKDIV2))
7961 return MODE_BAD;
7962
7963 /*
7964 * Reject clearly excessive dotclocks early to
7965 * avoid having to worry about huge integers later.
7966 */
7967 if (mode->clock > max_dotclock(display))
7968 return MODE_CLOCK_HIGH;
7969
7970 /* Transcoder timing limits */
7971 if (DISPLAY_VER(display) >= 11) {
7972 hdisplay_max = 16384;
7973 vdisplay_max = 8192;
7974 htotal_max = 16384;
7975 vtotal_max = 8192;
7976 } else if (DISPLAY_VER(display) >= 9 ||
7977 display->platform.broadwell || display->platform.haswell) {
7978 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
7979 vdisplay_max = 4096;
7980 htotal_max = 8192;
7981 vtotal_max = 8192;
7982 } else if (DISPLAY_VER(display) >= 3) {
7983 hdisplay_max = 4096;
7984 vdisplay_max = 4096;
7985 htotal_max = 8192;
7986 vtotal_max = 8192;
7987 } else {
7988 hdisplay_max = 2048;
7989 vdisplay_max = 2048;
7990 htotal_max = 4096;
7991 vtotal_max = 4096;
7992 }
7993
7994 if (mode->hdisplay > hdisplay_max ||
7995 mode->hsync_start > htotal_max ||
7996 mode->hsync_end > htotal_max ||
7997 mode->htotal > htotal_max)
7998 return MODE_H_ILLEGAL;
7999
8000 if (mode->vdisplay > vdisplay_max ||
8001 mode->vsync_start > vtotal_max ||
8002 mode->vsync_end > vtotal_max ||
8003 mode->vtotal > vtotal_max)
8004 return MODE_V_ILLEGAL;
8005
8006 return MODE_OK;
8007}
8008
8009enum drm_mode_status intel_cpu_transcoder_mode_valid(struct intel_display *display,
8010 const struct drm_display_mode *mode)
8011{
8012 /*
8013 * Additional transcoder timing limits,
8014 * excluding BXT/GLK DSI transcoders.
8015 */
8016 if (DISPLAY_VER(display) >= 5) {
8017 if (mode->hdisplay < 64 ||
8018 mode->htotal - mode->hdisplay < 32)
8019 return MODE_H_ILLEGAL;
8020
8021 if (mode->vtotal - mode->vdisplay < 5)
8022 return MODE_V_ILLEGAL;
8023 } else {
8024 if (mode->htotal - mode->hdisplay < 32)
8025 return MODE_H_ILLEGAL;
8026
8027 if (mode->vtotal - mode->vdisplay < 3)
8028 return MODE_V_ILLEGAL;
8029 }
8030
8031 /*
8032 * Cantiga+ cannot handle modes with a hsync front porch of 0.
8033 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8034 */
8035 if ((DISPLAY_VER(display) >= 5 || display->platform.g4x) &&
8036 mode->hsync_start == mode->hdisplay)
8037 return MODE_H_ILLEGAL;
8038
8039 return MODE_OK;
8040}
8041
8042enum drm_mode_status
8043intel_mode_valid_max_plane_size(struct intel_display *display,
8044 const struct drm_display_mode *mode,
8045 int num_joined_pipes)
8046{
8047 int plane_width_max, plane_height_max;
8048
8049 /*
8050 * intel_mode_valid() should be
8051 * sufficient on older platforms.
8052 */
8053 if (DISPLAY_VER(display) < 9)
8054 return MODE_OK;
8055
8056 /*
8057 * Most people will probably want a fullscreen
8058 * plane so let's not advertize modes that are
8059 * too big for that.
8060 */
8061 if (DISPLAY_VER(display) >= 30) {
8062 plane_width_max = 6144 * num_joined_pipes;
8063 plane_height_max = 4800;
8064 } else if (DISPLAY_VER(display) >= 11) {
8065 plane_width_max = 5120 * num_joined_pipes;
8066 plane_height_max = 4320;
8067 } else {
8068 plane_width_max = 5120;
8069 plane_height_max = 4096;
8070 }
8071
8072 if (mode->hdisplay > plane_width_max)
8073 return MODE_H_ILLEGAL;
8074
8075 if (mode->vdisplay > plane_height_max)
8076 return MODE_V_ILLEGAL;
8077
8078 return MODE_OK;
8079}
8080
8081static const struct intel_display_funcs skl_display_funcs = {
8082 .get_pipe_config = hsw_get_pipe_config,
8083 .crtc_enable = hsw_crtc_enable,
8084 .crtc_disable = hsw_crtc_disable,
8085 .commit_modeset_enables = skl_commit_modeset_enables,
8086 .get_initial_plane_config = skl_get_initial_plane_config,
8087 .fixup_initial_plane_config = skl_fixup_initial_plane_config,
8088};
8089
8090static const struct intel_display_funcs ddi_display_funcs = {
8091 .get_pipe_config = hsw_get_pipe_config,
8092 .crtc_enable = hsw_crtc_enable,
8093 .crtc_disable = hsw_crtc_disable,
8094 .commit_modeset_enables = intel_commit_modeset_enables,
8095 .get_initial_plane_config = i9xx_get_initial_plane_config,
8096 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8097};
8098
8099static const struct intel_display_funcs pch_split_display_funcs = {
8100 .get_pipe_config = ilk_get_pipe_config,
8101 .crtc_enable = ilk_crtc_enable,
8102 .crtc_disable = ilk_crtc_disable,
8103 .commit_modeset_enables = intel_commit_modeset_enables,
8104 .get_initial_plane_config = i9xx_get_initial_plane_config,
8105 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8106};
8107
8108static const struct intel_display_funcs vlv_display_funcs = {
8109 .get_pipe_config = i9xx_get_pipe_config,
8110 .crtc_enable = valleyview_crtc_enable,
8111 .crtc_disable = i9xx_crtc_disable,
8112 .commit_modeset_enables = intel_commit_modeset_enables,
8113 .get_initial_plane_config = i9xx_get_initial_plane_config,
8114 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8115};
8116
8117static const struct intel_display_funcs i9xx_display_funcs = {
8118 .get_pipe_config = i9xx_get_pipe_config,
8119 .crtc_enable = i9xx_crtc_enable,
8120 .crtc_disable = i9xx_crtc_disable,
8121 .commit_modeset_enables = intel_commit_modeset_enables,
8122 .get_initial_plane_config = i9xx_get_initial_plane_config,
8123 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8124};
8125
8126/**
8127 * intel_init_display_hooks - initialize the display modesetting hooks
8128 * @display: display device private
8129 */
8130void intel_init_display_hooks(struct intel_display *display)
8131{
8132 if (DISPLAY_VER(display) >= 9) {
8133 display->funcs.display = &skl_display_funcs;
8134 } else if (HAS_DDI(display)) {
8135 display->funcs.display = &ddi_display_funcs;
8136 } else if (HAS_PCH_SPLIT(display)) {
8137 display->funcs.display = &pch_split_display_funcs;
8138 } else if (display->platform.cherryview ||
8139 display->platform.valleyview) {
8140 display->funcs.display = &vlv_display_funcs;
8141 } else {
8142 display->funcs.display = &i9xx_display_funcs;
8143 }
8144}
8145
8146int intel_initial_commit(struct intel_display *display)
8147{
8148 struct drm_atomic_state *state = NULL;
8149 struct drm_modeset_acquire_ctx ctx;
8150 struct intel_crtc *crtc;
8151 int ret = 0;
8152
8153 state = drm_atomic_state_alloc(dev: display->drm);
8154 if (!state)
8155 return -ENOMEM;
8156
8157 drm_modeset_acquire_init(ctx: &ctx, flags: 0);
8158
8159 state->acquire_ctx = &ctx;
8160 to_intel_atomic_state(state)->internal = true;
8161
8162retry:
8163 for_each_intel_crtc(display->drm, crtc) {
8164 struct intel_crtc_state *crtc_state =
8165 intel_atomic_get_crtc_state(state, crtc);
8166
8167 if (IS_ERR(ptr: crtc_state)) {
8168 ret = PTR_ERR(ptr: crtc_state);
8169 goto out;
8170 }
8171
8172 if (!crtc_state->hw.active)
8173 crtc_state->inherited = false;
8174
8175 if (crtc_state->hw.active) {
8176 struct intel_encoder *encoder;
8177
8178 ret = drm_atomic_add_affected_planes(state, crtc: &crtc->base);
8179 if (ret)
8180 goto out;
8181
8182 /*
8183 * FIXME hack to force a LUT update to avoid the
8184 * plane update forcing the pipe gamma on without
8185 * having a proper LUT loaded. Remove once we
8186 * have readout for pipe gamma enable.
8187 */
8188 crtc_state->uapi.color_mgmt_changed = true;
8189
8190 for_each_intel_encoder_mask(display->drm, encoder,
8191 crtc_state->uapi.encoder_mask) {
8192 if (encoder->initial_fastset_check &&
8193 !encoder->initial_fastset_check(encoder, crtc_state)) {
8194 ret = drm_atomic_add_affected_connectors(state,
8195 crtc: &crtc->base);
8196 if (ret)
8197 goto out;
8198 }
8199 }
8200 }
8201 }
8202
8203 ret = drm_atomic_commit(state);
8204
8205out:
8206 if (ret == -EDEADLK) {
8207 drm_atomic_state_clear(state);
8208 drm_modeset_backoff(ctx: &ctx);
8209 goto retry;
8210 }
8211
8212 drm_atomic_state_put(state);
8213
8214 drm_modeset_drop_locks(ctx: &ctx);
8215 drm_modeset_acquire_fini(ctx: &ctx);
8216
8217 return ret;
8218}
8219
8220void i830_enable_pipe(struct intel_display *display, enum pipe pipe)
8221{
8222 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
8223 enum transcoder cpu_transcoder = (enum transcoder)pipe;
8224 /* 640x480@60Hz, ~25175 kHz */
8225 struct dpll clock = {
8226 .m1 = 18,
8227 .m2 = 7,
8228 .p1 = 13,
8229 .p2 = 4,
8230 .n = 2,
8231 };
8232 u32 dpll, fp;
8233 int i;
8234
8235 drm_WARN_ON(display->drm,
8236 i9xx_calc_dpll_params(48000, &clock) != 25154);
8237
8238 drm_dbg_kms(display->drm,
8239 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
8240 pipe_name(pipe), clock.vco, clock.dot);
8241
8242 fp = i9xx_dpll_compute_fp(dpll: &clock);
8243 dpll = DPLL_DVO_2X_MODE |
8244 DPLL_VGA_MODE_DIS |
8245 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
8246 PLL_P2_DIVIDE_BY_4 |
8247 PLL_REF_INPUT_DREFCLK |
8248 DPLL_VCO_ENABLE;
8249
8250 intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
8251 HACTIVE(640 - 1) | HTOTAL(800 - 1));
8252 intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
8253 HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
8254 intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
8255 HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
8256 intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
8257 VACTIVE(480 - 1) | VTOTAL(525 - 1));
8258 intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
8259 VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
8260 intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
8261 VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
8262 intel_de_write(display, PIPESRC(display, pipe),
8263 PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
8264
8265 intel_de_write(display, FP0(pipe), val: fp);
8266 intel_de_write(display, FP1(pipe), val: fp);
8267
8268 /*
8269 * Apparently we need to have VGA mode enabled prior to changing
8270 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
8271 * dividers, even though the register value does change.
8272 */
8273 intel_de_write(display, DPLL(display, pipe),
8274 val: dpll & ~DPLL_VGA_MODE_DIS);
8275 intel_de_write(display, DPLL(display, pipe), val: dpll);
8276
8277 /* Wait for the clocks to stabilize. */
8278 intel_de_posting_read(display, DPLL(display, pipe));
8279 udelay(usec: 150);
8280
8281 /* The pixel multiplier can only be updated once the
8282 * DPLL is enabled and the clocks are stable.
8283 *
8284 * So write it again.
8285 */
8286 intel_de_write(display, DPLL(display, pipe), val: dpll);
8287
8288 /* We do this three times for luck */
8289 for (i = 0; i < 3 ; i++) {
8290 intel_de_write(display, DPLL(display, pipe), val: dpll);
8291 intel_de_posting_read(display, DPLL(display, pipe));
8292 udelay(usec: 150); /* wait for warmup */
8293 }
8294
8295 intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE);
8296 intel_de_posting_read(display, TRANSCONF(display, pipe));
8297
8298 intel_wait_for_pipe_scanline_moving(crtc);
8299}
8300
8301void i830_disable_pipe(struct intel_display *display, enum pipe pipe)
8302{
8303 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
8304
8305 drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n",
8306 pipe_name(pipe));
8307
8308 drm_WARN_ON(display->drm,
8309 intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE);
8310 drm_WARN_ON(display->drm,
8311 intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE);
8312 drm_WARN_ON(display->drm,
8313 intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE);
8314 drm_WARN_ON(display->drm,
8315 intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK);
8316 drm_WARN_ON(display->drm,
8317 intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK);
8318
8319 intel_de_write(display, TRANSCONF(display, pipe), val: 0);
8320 intel_de_posting_read(display, TRANSCONF(display, pipe));
8321
8322 intel_wait_for_pipe_scanline_stopped(crtc);
8323
8324 intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);
8325 intel_de_posting_read(display, DPLL(display, pipe));
8326}
8327
8328bool intel_scanout_needs_vtd_wa(struct intel_display *display)
8329{
8330 struct drm_i915_private *i915 = to_i915(dev: display->drm);
8331
8332 return IS_DISPLAY_VER(display, 6, 11) && i915_vtd_active(i915);
8333}
8334