1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2023 Intel Corporation
4 */
5
6#include <linux/pci.h>
7#include <linux/pnp.h>
8#include <linux/vgaarb.h>
9
10#include <drm/drm_managed.h>
11#include <drm/intel/i915_drm.h>
12
13#include "../display/intel_display_core.h" /* FIXME */
14
15#include "i915_drv.h"
16#include "intel_gmch.h"
17#include "intel_pci_config.h"
18
19static void intel_gmch_bridge_release(struct drm_device *dev, void *bridge)
20{
21 pci_dev_put(dev: bridge);
22}
23
24int intel_gmch_bridge_setup(struct drm_i915_private *i915)
25{
26 int domain = pci_domain_nr(to_pci_dev(i915->drm.dev)->bus);
27
28 i915->gmch.pdev = pci_get_domain_bus_and_slot(domain, bus: 0, PCI_DEVFN(0, 0));
29 if (!i915->gmch.pdev) {
30 drm_err(&i915->drm, "bridge device not found\n");
31 return -EIO;
32 }
33
34 return drmm_add_action_or_reset(&i915->drm, intel_gmch_bridge_release,
35 i915->gmch.pdev);
36}
37
38static int mchbar_reg(struct drm_i915_private *i915)
39{
40 return GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
41}
42
43/* Allocate space for the MCH regs if needed, return nonzero on error */
44static int
45intel_alloc_mchbar_resource(struct drm_i915_private *i915)
46{
47 u32 temp_lo, temp_hi = 0;
48 u64 mchbar_addr;
49 int ret;
50
51 if (GRAPHICS_VER(i915) >= 4)
52 pci_read_config_dword(dev: i915->gmch.pdev, where: mchbar_reg(i915) + 4, val: &temp_hi);
53 pci_read_config_dword(dev: i915->gmch.pdev, where: mchbar_reg(i915), val: &temp_lo);
54 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
55
56 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
57 if (IS_ENABLED(CONFIG_PNP) && mchbar_addr &&
58 pnp_range_reserved(start: mchbar_addr, end: mchbar_addr + MCHBAR_SIZE))
59 return 0;
60
61 /* Get some space for it */
62 i915->gmch.mch_res.name = "i915 MCHBAR";
63 i915->gmch.mch_res.flags = IORESOURCE_MEM;
64 ret = pci_bus_alloc_resource(bus: i915->gmch.pdev->bus,
65 res: &i915->gmch.mch_res,
66 MCHBAR_SIZE, MCHBAR_SIZE,
67 PCIBIOS_MIN_MEM,
68 type_mask: 0, alignf: pcibios_align_resource,
69 alignf_data: i915->gmch.pdev);
70 if (ret) {
71 drm_dbg(&i915->drm, "failed bus alloc: %d\n", ret);
72 i915->gmch.mch_res.start = 0;
73 return ret;
74 }
75
76 if (GRAPHICS_VER(i915) >= 4)
77 pci_write_config_dword(dev: i915->gmch.pdev, where: mchbar_reg(i915) + 4,
78 upper_32_bits(i915->gmch.mch_res.start));
79
80 pci_write_config_dword(dev: i915->gmch.pdev, where: mchbar_reg(i915),
81 lower_32_bits(i915->gmch.mch_res.start));
82 return 0;
83}
84
85/* Setup MCHBAR if possible, return true if we should disable it again */
86void intel_gmch_bar_setup(struct drm_i915_private *i915)
87{
88 u32 temp;
89 bool enabled;
90
91 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
92 return;
93
94 i915->gmch.mchbar_need_disable = false;
95
96 if (IS_I915G(i915) || IS_I915GM(i915)) {
97 pci_read_config_dword(dev: i915->gmch.pdev, DEVEN, val: &temp);
98 enabled = !!(temp & DEVEN_MCHBAR_EN);
99 } else {
100 pci_read_config_dword(dev: i915->gmch.pdev, where: mchbar_reg(i915), val: &temp);
101 enabled = temp & 1;
102 }
103
104 /* If it's already enabled, don't have to do anything */
105 if (enabled)
106 return;
107
108 if (intel_alloc_mchbar_resource(i915))
109 return;
110
111 i915->gmch.mchbar_need_disable = true;
112
113 /* Space is allocated or reserved, so enable it. */
114 if (IS_I915G(i915) || IS_I915GM(i915)) {
115 pci_write_config_dword(dev: i915->gmch.pdev, DEVEN,
116 val: temp | DEVEN_MCHBAR_EN);
117 } else {
118 pci_read_config_dword(dev: i915->gmch.pdev, where: mchbar_reg(i915), val: &temp);
119 pci_write_config_dword(dev: i915->gmch.pdev, where: mchbar_reg(i915), val: temp | 1);
120 }
121}
122
123void intel_gmch_bar_teardown(struct drm_i915_private *i915)
124{
125 if (i915->gmch.mchbar_need_disable) {
126 if (IS_I915G(i915) || IS_I915GM(i915)) {
127 u32 deven_val;
128
129 pci_read_config_dword(dev: i915->gmch.pdev, DEVEN,
130 val: &deven_val);
131 deven_val &= ~DEVEN_MCHBAR_EN;
132 pci_write_config_dword(dev: i915->gmch.pdev, DEVEN,
133 val: deven_val);
134 } else {
135 u32 mchbar_val;
136
137 pci_read_config_dword(dev: i915->gmch.pdev, where: mchbar_reg(i915),
138 val: &mchbar_val);
139 mchbar_val &= ~1;
140 pci_write_config_dword(dev: i915->gmch.pdev, where: mchbar_reg(i915),
141 val: mchbar_val);
142 }
143 }
144
145 if (i915->gmch.mch_res.start)
146 release_resource(new: &i915->gmch.mch_res);
147}
148
149int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode)
150{
151 struct intel_display *display = i915->display;
152 unsigned int reg = DISPLAY_VER(display) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
153 u16 gmch_ctrl;
154
155 if (pci_read_config_word(dev: i915->gmch.pdev, where: reg, val: &gmch_ctrl)) {
156 drm_err(&i915->drm, "failed to read control word\n");
157 return -EIO;
158 }
159
160 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !enable_decode)
161 return 0;
162
163 if (enable_decode)
164 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
165 else
166 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
167
168 if (pci_write_config_word(dev: i915->gmch.pdev, where: reg, val: gmch_ctrl)) {
169 drm_err(&i915->drm, "failed to write control word\n");
170 return -EIO;
171 }
172
173 return 0;
174}
175
176unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode)
177{
178 struct drm_i915_private *i915 = pdev_to_i915(pdev);
179
180 intel_gmch_vga_set_state(i915, enable_decode);
181
182 if (enable_decode)
183 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
184 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
185 else
186 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
187}
188